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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN1PEPF00004689.mail.protection.outlook.com (10.167.243.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.10 via Frontend Transport; Thu, 21 Mar 2024 14:25:07 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Thu, 21 Mar 2024 07:24:47 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 21 Mar 2024 07:24:43 -0700 From: Yevgeny Kliteynik To: , , , , Dariusz Sosnowski , Ori Kam , Matan Azrad , Erez Shitrit , Alex Vesker CC: , , Subject: [PATCH 2/2] net/mlx5/hws: fix port ID for root table Date: Thu, 21 Mar 2024 16:24:14 +0200 Message-ID: <20240321142414.1573453-2-kliteyn@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20240321142414.1573453-1-kliteyn@nvidia.com> References: <20240321142414.1573453-1-kliteyn@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004689:EE_|DM4PR12MB6109:EE_ X-MS-Office365-Filtering-Correlation-Id: c5a15ada-8904-40ce-3a60-08dc49b2b552 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2024 14:25:07.2651 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c5a15ada-8904-40ce-3a60-08dc49b2b552 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004689.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6109 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Erez Shitrit In root tables matcher and rule need to have their port-id, otherwise the translate function that done in dpdk layer will not get the right attributes. For that whenever the matcher is matching the source-port we need to get the relevant port-id before calling the translate function. Fixes: 405242c52dd5 ("net/mlx5/hws: add rule object") Cc: stable@dpdk.org Signed-off-by: Yevgeny Kliteynik Signed-off-by: Erez Shitrit Acked-by: Matan Azrad Signed-off-by: Yevgeny Kliteynik --- drivers/net/mlx5/hws/mlx5dr_matcher.c | 17 +++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_rule.c | 18 ++++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 22 ++++++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c index 1c64abfa57..aeff300467 100644 --- a/drivers/net/mlx5/hws/mlx5dr_matcher.c +++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c @@ -1220,6 +1220,7 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher) struct mlx5dv_flow_match_parameters *mask; struct mlx5_flow_attr flow_attr = {0}; struct rte_flow_error rte_error; + struct rte_flow_item *item; uint8_t match_criteria; int ret; @@ -1248,6 +1249,22 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher) return rte_errno; } + /* We need the port id in case of matching representor */ + item = matcher->mt[0].items; + while (item->type != RTE_FLOW_ITEM_TYPE_END) { + if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR || + item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { + ret = flow_hw_get_port_id_from_ctx(ctx, &flow_attr.port_id); + if (ret) { + DR_LOG(ERR, "Failed to get port id for dev %s", + ctx->ibv_ctx->device->name); + rte_errno = EINVAL; + return rte_errno; + } + } + ++item; + } + mask = simple_calloc(1, MLX5_ST_SZ_BYTES(fte_match_param) + offsetof(struct mlx5dv_flow_match_parameters, match_buf)); if (!mask) { diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c index 784f614d87..022263eb1d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_rule.c +++ b/drivers/net/mlx5/hws/mlx5dr_rule.c @@ -687,10 +687,28 @@ static int mlx5dr_rule_create_root(struct mlx5dr_rule *rule, struct mlx5dv_flow_match_parameters *value; struct mlx5_flow_attr flow_attr = {0}; struct mlx5dv_flow_action_attr *attr; + const struct rte_flow_item *cur_item; struct rte_flow_error error; uint8_t match_criteria; int ret; + /* We need the port id in case of matching representor */ + cur_item = items; + while (cur_item->type != RTE_FLOW_ITEM_TYPE_END) { + if (cur_item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR || + cur_item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { + ret = flow_hw_get_port_id_from_ctx(rule->matcher->tbl->ctx, + &flow_attr.port_id); + if (ret) { + DR_LOG(ERR, "Failed to get port id for dev %s", + rule->matcher->tbl->ctx->ibv_ctx->device->name); + rte_errno = EINVAL; + return rte_errno; + } + } + ++cur_item; + } + attr = simple_calloc(num_actions, sizeof(*attr)); if (!attr) { rte_errno = ENOMEM; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 34b5e0f45b..0065727a67 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2001,6 +2001,28 @@ flow_hw_get_reg_id(struct rte_eth_dev *dev, #endif } +static __rte_always_inline int +flow_hw_get_port_id_from_ctx(void *dr_ctx, uint32_t *port_val) +{ +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) + uint32_t port; + + MLX5_ETH_FOREACH_DEV(port, NULL) { + struct mlx5_priv *priv; + priv = rte_eth_devices[port].data->dev_private; + + if (priv->dr_ctx == dr_ctx) { + *port_val = port; + return 0; + } + } +#else + RTE_SET_USED(dr_ctx); + RTE_SET_USED(port_val); +#endif + return -EINVAL; +} + /** * Get GENEVE TLV option FW information according type and class. * -- 2.27.0