From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ECD7C43D16; Thu, 21 Mar 2024 15:48:47 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2D24B42DC7; Thu, 21 Mar 2024 15:48:47 +0100 (CET) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2084.outbound.protection.outlook.com [40.107.237.84]) by mails.dpdk.org (Postfix) with ESMTP id 9B888427E1; Thu, 21 Mar 2024 15:48:45 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LbHqark8q0CIyyOJaatYBYxeUjz+CR1SL6WXshWMNdQTJ8yLx0JZGxl/IAo3LoQ/m1XrXwlk35GZAdefToqy4Ioo6+uczMrelpurXANFstqNBrYNw2q23KVR3hLPZ4ZZvrkZNNNxNMeW2JPKPnLpUWNxKSxIjz50iOKEyIj9BRRInM1OPJz7DCbiMMO1OZ3M/sVsNQ1ADIA/xw9/oJPuQ5M/TapS2yadm80KwwJmg7pBx7XrQAJmgCQ0xdJs0xhnFlPVmQygJJ01KZ58igkHWjL3zm2cRT4YRPwbTQLMrpzNt6Y11N5abZCFzBKn4bt6klpS0SiMLdrlrhOZzJvt8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fh2zDLTxxtS0wmBmeDy7sGeVvyVvbbY/+hkvkGLu7B4=; b=IjFuAnmZL25dBK3G3LXpQpAHDsIOkMTd8cD534cFVkLO0rbZf+m391YGXXgcv+96oeuPjnphpESHQV/sszfDojFldBcKfr1fy4jGXUmuZ30OTXW0ighpVCaCGu6FLWoP+/UdH5Az3jL2EB9mQcokQmsQRwCMxTzJFQFEaEd9mOnL1zHULgY2B1dPWxrAVLGM1ePKciBI+WXyzEOz5oKdbiwtknDGR5GcL1tQz1xg6J/+iDWYz4BXLh7ZqtQ+IXYQNuqvwf29+cFXJioJhPQcxIApvXYTOzR5Vha6H/LC8UgjRR29XDZzKL3eMiQEqBrVR3qI+uTFs1v3iJVeJWGDaw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fh2zDLTxxtS0wmBmeDy7sGeVvyVvbbY/+hkvkGLu7B4=; b=EWds/MkUOinmia671zdAPBWwD/FdiGdrl1ZPNVm1YxW7j8BJ5bqktrjKgFWu/CuzUdimCPXsNp0TpvbcUnEImKsOIjdez5a938Xp9maKxdqbCbXEMRnmzhA63eyKM1lgEgC1+Bjjy/dtzmNEVJKDhaOMED5h3qEm4O7WlInDzZ7BntjObQDivz2PAWx6ZjkvijqjyXh1H5MWiBBfWgn9FsMbc5vK4qUvQ3PI8SZL38pOHwoyfAd0vj5ZNYC2IxtuChbvozIcfQkSxV5DrQ7Hzlpx6frK8str7Lb27K96hlk0Vnmv+AU73Y9h6t1Vb227b3JzGqlg2htoYxhsxDbB8Q== Received: from CH5P222CA0021.NAMP222.PROD.OUTLOOK.COM (2603:10b6:610:1ee::10) by DM4PR12MB5769.namprd12.prod.outlook.com (2603:10b6:8:60::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7386.30; Thu, 21 Mar 2024 14:48:41 +0000 Received: from DS3PEPF000099DC.namprd04.prod.outlook.com (2603:10b6:610:1ee:cafe::2f) by CH5P222CA0021.outlook.office365.com (2603:10b6:610:1ee::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7386.28 via Frontend Transport; Thu, 21 Mar 2024 14:48:41 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS3PEPF000099DC.mail.protection.outlook.com (10.167.17.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.10 via Frontend Transport; Thu, 21 Mar 2024 14:48:41 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Thu, 21 Mar 2024 07:48:24 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 21 Mar 2024 07:48:21 -0700 From: Yevgeny Kliteynik To: , , , , Dariusz Sosnowski , Ori Kam , Matan Azrad , Erez Shitrit , Alex Vesker CC: , , Subject: [PATCH v2] net/mlx5/hws: fix port ID for root table Date: Thu, 21 Mar 2024 16:48:11 +0200 Message-ID: <20240321144811.1574579-1-kliteyn@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20240321142414.1573453-2-kliteyn@nvidia.com> References: <20240321142414.1573453-2-kliteyn@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DC:EE_|DM4PR12MB5769:EE_ X-MS-Office365-Filtering-Correlation-Id: 3cdfaf73-eba2-4ef5-bd75-08dc49b6000e X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 95nIn4G01f91m3lXly6KdgDLRv584DhKvhq5MxU6zRiU2i3fMphai5jERg6K7MpMRW+pTlM2n1SKiRAdxQlfJUoj6EZQEiTUQBYjXLlke8EYP0RtUYfDdtzfgBD5p0z8GNzwCuKRyLB4bjg4phLBNeXCvsLX7NUinNaRL/PpMMKdiwvJCzNU9Q1rUhJh7G89fNiW5ujarXTIkc0Q7Sk2nFGP6hp2l+k9mSOOgFbaQbUbyjhwV9keKN/H+TcS/pjwgsbp2IrjZrR+74A7LXE6Af9bXB4rTFA5j8ujxhChBFo4pEoVcsrghNrDoV4FROOrJ1BIKwlTRt8jUaYdbaxgkBM7D3f7BLARJ8goY7JR+YgAgKrKopbn0zldnvGQZD0uf/iI9KgkVj1vs446DMJTIjaeha5HHmG46UXKYGW6o4sKEuo7b6mrCW0QS0R4bCE49KMUaIFOl8bbR7muNTKJF2TOmEpz0RKx3WCv92V/DgqNcu+Ig07Eh9nB9mqxscAhFR8tP3kETkgROqeOw537M/VNEpudUgSmREyB+Ce83jDDpmAg+wDFAGBr726KbGcHl3ePWFrhskasvhO1fzaDrKfZmuB2UvyXeBi9M7IAXWo3v3A5bX6CojUIs6yLNqMDg1IPTCaJtIkyvu4LBQeVHbbXQA/E4VQZ/rbYUP8UAGTq8Bx6Y/drcUohDgvei6OPZqjuXlvEohe43Z1P0wje2yFfgyWckZRnyKvoYM58R3P4auvLmk5j8qbBAQ2x0Lks X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(376005)(36860700004)(82310400014)(1800799015); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2024 14:48:41.2203 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3cdfaf73-eba2-4ef5-bd75-08dc49b6000e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DC.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5769 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Erez Shitrit In root tables matcher and rule need to have their port-id, otherwise the translate function that done in dpdk layer will not get the right attributes. For that whenever the matcher is matching the source-port we need to get the relevant port-id before calling the translate function. Fixes: 405242c52dd5 ("net/mlx5/hws: add rule object") Cc: stable@dpdk.org Signed-off-by: Yevgeny Kliteynik Signed-off-by: Erez Shitrit Acked-by: Matan Azrad --- V2 - removed duplicated sign-off line drivers/net/mlx5/hws/mlx5dr_matcher.c | 17 +++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_rule.c | 18 ++++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 22 ++++++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c index 1c64abfa57..aeff300467 100644 --- a/drivers/net/mlx5/hws/mlx5dr_matcher.c +++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c @@ -1220,6 +1220,7 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher) struct mlx5dv_flow_match_parameters *mask; struct mlx5_flow_attr flow_attr = {0}; struct rte_flow_error rte_error; + struct rte_flow_item *item; uint8_t match_criteria; int ret; @@ -1248,6 +1249,22 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher) return rte_errno; } + /* We need the port id in case of matching representor */ + item = matcher->mt[0].items; + while (item->type != RTE_FLOW_ITEM_TYPE_END) { + if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR || + item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { + ret = flow_hw_get_port_id_from_ctx(ctx, &flow_attr.port_id); + if (ret) { + DR_LOG(ERR, "Failed to get port id for dev %s", + ctx->ibv_ctx->device->name); + rte_errno = EINVAL; + return rte_errno; + } + } + ++item; + } + mask = simple_calloc(1, MLX5_ST_SZ_BYTES(fte_match_param) + offsetof(struct mlx5dv_flow_match_parameters, match_buf)); if (!mask) { diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c index 784f614d87..022263eb1d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_rule.c +++ b/drivers/net/mlx5/hws/mlx5dr_rule.c @@ -687,10 +687,28 @@ static int mlx5dr_rule_create_root(struct mlx5dr_rule *rule, struct mlx5dv_flow_match_parameters *value; struct mlx5_flow_attr flow_attr = {0}; struct mlx5dv_flow_action_attr *attr; + const struct rte_flow_item *cur_item; struct rte_flow_error error; uint8_t match_criteria; int ret; + /* We need the port id in case of matching representor */ + cur_item = items; + while (cur_item->type != RTE_FLOW_ITEM_TYPE_END) { + if (cur_item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR || + cur_item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { + ret = flow_hw_get_port_id_from_ctx(rule->matcher->tbl->ctx, + &flow_attr.port_id); + if (ret) { + DR_LOG(ERR, "Failed to get port id for dev %s", + rule->matcher->tbl->ctx->ibv_ctx->device->name); + rte_errno = EINVAL; + return rte_errno; + } + } + ++cur_item; + } + attr = simple_calloc(num_actions, sizeof(*attr)); if (!attr) { rte_errno = ENOMEM; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 34b5e0f45b..0065727a67 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2001,6 +2001,28 @@ flow_hw_get_reg_id(struct rte_eth_dev *dev, #endif } +static __rte_always_inline int +flow_hw_get_port_id_from_ctx(void *dr_ctx, uint32_t *port_val) +{ +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) + uint32_t port; + + MLX5_ETH_FOREACH_DEV(port, NULL) { + struct mlx5_priv *priv; + priv = rte_eth_devices[port].data->dev_private; + + if (priv->dr_ctx == dr_ctx) { + *port_val = port; + return 0; + } + } +#else + RTE_SET_USED(dr_ctx); + RTE_SET_USED(port_val); +#endif + return -EINVAL; +} + /** * Get GENEVE TLV option FW information according type and class. * -- 2.27.0