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* [PATCH] Spelling: Fixed a spelling mistake.
@ 2024-03-21 23:16 hollynichols04
  2024-03-25  2:41 ` Thomas Monjalon
  0 siblings, 1 reply; 4+ messages in thread
From: hollynichols04 @ 2024-03-21 23:16 UTC (permalink / raw)
  To: dev; +Cc: Holly Nichols

From: Holly Nichols <hollynichols04@gmail.com>

Caught by codespell.

Signed-off-by: Holly Nichols <hollynichols04@gmail.com>
---
 app/test/test_cfgfile.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/app/test/test_cfgfile.c b/app/test/test_cfgfile.c
index 2f596affee..21bf34a718 100644
--- a/app/test/test_cfgfile.c
+++ b/app/test/test_cfgfile.c
@@ -196,7 +196,7 @@ test_cfgfile_invalid_key_value_pair(void)
 	struct rte_cfgfile *cfgfile;
 
 	cfgfile = rte_cfgfile_load(CFG_FILES_ETC "/empty_key_value.ini", 0);
-	TEST_ASSERT_NULL(cfgfile, "Expected failured did not occur");
+	TEST_ASSERT_NULL(cfgfile, "Expected failure did not occur");
 
 	return 0;
 }
-- 
2.44.0.windows.1


^ permalink raw reply	[flat|nested] 4+ messages in thread
* [PATCH] Spelling: Fixed a spelling mistake.
@ 2024-03-21 23:03 Flore
  2024-03-25  1:05 ` Thomas Monjalon
  0 siblings, 1 reply; 4+ messages in thread
From: Flore @ 2024-03-21 23:03 UTC (permalink / raw)
  To: dev; +Cc: Flore

Caught by codespell

Signed-off-by: Flore Norceide <florestecien@gmail.com>
---
 doc/guides/prog_guide/packet_framework.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/doc/guides/prog_guide/packet_framework.rst b/doc/guides/prog_guide/packet_framework.rst
index ebc69d8c3e..9987ead6c5 100644
--- a/doc/guides/prog_guide/packet_framework.rst
+++ b/doc/guides/prog_guide/packet_framework.rst
@@ -509,7 +509,7 @@ the number of L2 or L3 cache memory misses is greatly reduced, hence one of the
 This is because the cost of L2/L3 cache memory miss on memory read accesses is high, as usually due to data dependency between instructions,
 the CPU execution units have to stall until the read operation is completed from L3 cache memory or external DRAM memory.
 By using prefetch instructions, the latency of memory read accesses is hidden,
-provided that it is preformed early enough before the respective data structure is actually used.
+provided that it is performed early enough before the respective data structure is actually used.
 
 By splitting the processing into several stages that are executed on different packets (the packets from the input burst are interlaced),
 enough work is created to allow the prefetch instructions to complete successfully (before the prefetched data structures are actually accessed) and
-- 
2.42.0.windows.2


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2024-03-25  2:41 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2024-03-21 23:16 [PATCH] Spelling: Fixed a spelling mistake hollynichols04
2024-03-25  2:41 ` Thomas Monjalon
  -- strict thread matches above, loose matches on Subject: below --
2024-03-21 23:03 Flore
2024-03-25  1:05 ` Thomas Monjalon

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