From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 74CDF43F54; Tue, 30 Apr 2024 14:19:07 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1594F402E8; Tue, 30 Apr 2024 14:18:40 +0200 (CEST) Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2047.outbound.protection.outlook.com [40.107.7.47]) by mails.dpdk.org (Postfix) with ESMTP id 8FBCE402C6 for ; Tue, 30 Apr 2024 14:18:36 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=mCI9mJxgxWkTol2fU8VoTCrYgebudE4JEd57oKu7FFmSu8xNaDAX0LjF5Iwyn+4pjicy7wnP6wpOS/Ysb+s30tkRQh4ADHIt1NVb1bHztx6/pEID/hfoFOh1QMxPWUeASKwozBw4coS/VEFkxO2AYGaBfUFEUpafaQorbeL1qqtelxQWWJwwONaY9TqiFjQNpqqZl6LcVY449HXWLzycw0hhtrLPvfjWVH3XItP+/rog8icfPS6cMpTpleBr841YaLmcVH23wDTs31Vd0BymzXNWkhH7v1w3WLRZJ2hG2I6bUA2vKu7Uk4IowDJQx2VWTsX27NxRwRHN5Zb7h4gLtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=gk1oIO/yUGX1588KPUNyJxk5Ae9kYVDguUQ6UVG4UyE=; b=DD51rVCdYBSniA4ao92VxZWJ2BZCdS2uS7dPB8YuTAHWqi5V5CVEEi83nwXhYVQ86Jr+d+DUYvO9I6024BVXMPZ9+kaPui7Mn0hwE0nBYoGaT1UWH51hWk/n1qFqcRlhlCG1oT5UY5I2OUWjWcCCtNoKit9gpaiI5CRkkFVYaOdci5IjoyOPfNUfH6kV0VA+V/HxS9HOxV0a/mzeVSuA9b9AGkxnGEA9biy0A3KqV+MwIi+AfZd5TUiMnwz8YruuN59Mytghv1KK4vKF9n+4F6vS/3QmVQrBl0MRC2DuT3wHd4I7ELM0CA8EOUaQOdc7+2gMcEcXEKTJjnZ3uun/lA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gk1oIO/yUGX1588KPUNyJxk5Ae9kYVDguUQ6UVG4UyE=; b=abbYd3ex59m5VtXXkSrKeMluxWyT8ly83FE7Hr7kY6uZwHhBdLv2ndV17qUD9SB4JhScYMrMtGKxgVf8OVjACeERY6NWDHRV8gdVmdhJxMeH80GawE7ibTr3m8jH+JBT10u/O9ikjq2MmMy0aNx3soDAfzZYje4pQYuNZdII1+bdFKM9B2IHqUFV43C1gBfv0wZcegyCzqY83FXtEFlq5bj/5WXenvINOvPW3r+sfJh1NXdmcBVMsGAh4mzf2ytr4xVYam9Smn2pG/SrN8MP7ZKelMjmR3uSRQKlZQ0DBs5fCRlV6219kPPJpliLOhkaHDG1Uh46JwOAvF+XB9CGsQ== Received: from DU2PR04CA0163.eurprd04.prod.outlook.com (2603:10a6:10:2b0::18) by PAWPR07MB9976.eurprd07.prod.outlook.com (2603:10a6:102:38e::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.34; Tue, 30 Apr 2024 12:18:34 +0000 Received: from DB1PEPF000509F3.eurprd02.prod.outlook.com (2603:10a6:10:2b0:cafe::73) by DU2PR04CA0163.outlook.office365.com (2603:10a6:10:2b0::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.36 via Frontend Transport; Tue, 30 Apr 2024 12:18:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by DB1PEPF000509F3.mail.protection.outlook.com (10.167.242.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Tue, 30 Apr 2024 12:18:33 +0000 Received: from seliicinfr00049.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.65) with Microsoft SMTP Server id 15.2.1544.9; Tue, 30 Apr 2024 14:18:33 +0200 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00049.seli.gic.ericsson.se (Postfix) with ESMTP id 0CB4A380061; Tue, 30 Apr 2024 14:18:33 +0200 (CEST) From: =?UTF-8?q?Mattias=20R=C3=B6nnblom?= To: CC: , Heng Wang , "Stephen Hemminger" , Tyler Retzlaff , =?UTF-8?q?Morten=20Br=C3=B8rup?= , =?UTF-8?q?Mattias=20R=C3=B6nnblom?= Subject: [RFC v5 5/6] eal: add atomic bit operations Date: Tue, 30 Apr 2024 14:08:09 +0200 Message-ID: <20240430120810.108928-6-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430120810.108928-1-mattias.ronnblom@ericsson.com> References: <20240430095523.108688-2-mattias.ronnblom@ericsson.com> <20240430120810.108928-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB1PEPF000509F3:EE_|PAWPR07MB9976:EE_ X-MS-Office365-Filtering-Correlation-Id: 760967a0-fffe-4e1c-1810-08dc690fa7a1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|376005|82310400014|1800799015|36860700004; X-Microsoft-Antispam-Message-Info: =?utf-8?B?aUppdU85QzRVaFQwMkxtSjdROEZ1TEtTR2pYVkt0VkNQM2ZJQmdySnM3RVJw?= =?utf-8?B?RzEzUzRvWXlYVFdEb1QwYStFeDNoOExud3BJK3ROS1lQSUJvcitvWGozSlRx?= =?utf-8?B?Q2pXMkNmT0ZpQ3hvNG9aUGlycmdscVBjSFRyUzFGWkpKbzVNdGJiWDIzdWFC?= =?utf-8?B?eHhvWDJ6Qi9tRmVMakZNNnFhc1pkKy92U3Z0QlNtSks0cTRNNnYwUVBHY3Jr?= =?utf-8?B?dXJyYUxHVU9HdjhVTWQrSXlCUGk4dWJGKzc4emJPdmVvV2hXemlSMUJvcExr?= =?utf-8?B?MkxLaUpVazd5cW1FYzhrQ1FrQkkwMmk2VGI2SVRUbE8ycVFvVTZ2VWY3TDQr?= =?utf-8?B?bGJISlVQcnlQYlRRWk1SN1dXb2tkRnBQV1RhT2VqcitLT0xxWk0xSk9Va2Ja?= =?utf-8?B?dlg5Q3lwTk90OGZDdTk1STRQd1QzSWFqT0ViV2ZjbXFEdGplRDZUT2RxZGRT?= =?utf-8?B?OGZ6R3F4dW03UXFScGZkZWNKRURSbFM0KzdUZGZhcW9KK1JjVDVBVTRLN3l5?= =?utf-8?B?cndGZ3J5dVN5UkRDdUQwdWpEYXI1Y3NVVjNnV3NWSDZMZ1VQR3F2Nmh3dXpH?= =?utf-8?B?QlJEcDByRHowYnc1cGNnN08yRHBzWFAvdXBBMnk2eFFaUUQrUUpZM3BiVkRz?= =?utf-8?B?WjVQdXpOOWxscGIzbm9ONFJiU2k0RlBCMFArSU42MjdZWFU1amY3Y3hDN2dQ?= =?utf-8?B?YVBrZGZHSVFYcFNUb1UvVkFwQnhrQ0k2cnppT25LM2R4TUxIcE1qalZBM0xM?= =?utf-8?B?ME96ZTd6azBYS2pZTVRUb3ZEbmVGMEFDK1lRS0RndC96Q3VoMlozeC96S0lO?= =?utf-8?B?Q3RxSktNWi92cUZ2UGhremlBeGZFcFJRbjZXdFg5am5wOFZqV2RKQkR0VjVD?= =?utf-8?B?czh1ako4WFBUZzlxZWNCekZqaHNHVTY3Z1QwbDFGUlh1cktWNlRDSUNJY0ZU?= =?utf-8?B?OHlzQldhVTF4MkpLR0FURDYwMzZIdVArWDlnK3NzUFNFZytwbklHT1NVRlhW?= =?utf-8?B?dDUzK2l6VGtyOGgvMWNoeVp5RENXVFU1NnZPcmxNRHE3L3BkcUVuUkNTZEFB?= =?utf-8?B?dmM0VmloR1Y2dWJ3VnM0K2M0Z2tVVVZNd0djY2R6eWN2d0h3ZUJYbFZxeXYv?= =?utf-8?B?aDV1UTFKNkRHbnRoOTR2d0NxdzZ5SWM3OVhwY09obW5qUVpHMVl4NDZTbkw1?= =?utf-8?B?QW1EcTVrTTBvQzRkMTVKUXZqaURwWXlCWEpSRnphaVBwNXZMZDAzZVNpbW1t?= =?utf-8?B?djJaRHJ3alJBTm8vbXkwT0QvUXUrVHh0Sit4VGoyVzFlTnB2ZG1MV2NUVnJB?= =?utf-8?B?ckk2eko0cm1tdXFHQmpiWlRMcVlUWEIyWXBqNHlxbXdMYkVHanZoaktYWFJ0?= =?utf-8?B?ejI1UnR3S3FZdXQ5bUkrK3Y0N3RSMkQ2OGRDc3JEWTRtV29JYXFxL0phZlZS?= =?utf-8?B?OE5xbGd6Ry9raGNnSFA2clhKREdFTWJ6RjVRNnJ4dE4yRDFEZ2V3em1SbGh0?= =?utf-8?B?TlI3ajRIN3JnQlgwL1BKbEdvYzFHRnhQWnUxeUFFMlQ3YlNtTi9va25CWlNZ?= =?utf-8?B?N0hLSmFtaHprd3ZlNStpdkJlejN2OVlxYkg2V2RLSFlUWUx0RmxxU0RKQlVX?= =?utf-8?B?WFFaSW5IclZjcEZOM1EySG1lVjVadGZ1ZHV1bm5EczNSZW9vZUR4ZmRaL2Mz?= =?utf-8?B?ZWh0bEg1REl2VThZdXpvbzhnTGt4L3MySGtHcGZkaGZPQXNtV1I4Z3ZIekhn?= =?utf-8?B?NHByRGh6KzNLc1NrN2FUQXo2R25jamVaN1RWcUdaZG4xcEVLZzZROThjeTJ6?= =?utf-8?B?cEV0MFY0bHRYRVlPcmFCL3ZuZCsxNTlqN3F2YWIwdjh1VEROZVI5Mzltb2dC?= =?utf-8?Q?qWAuxIH+eA33/?= X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(376005)(82310400014)(1800799015)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 12:18:33.6608 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 760967a0-fffe-4e1c-1810-08dc690fa7a1 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509F3.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR07MB9976 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add atomic bit test/set/clear/assign and test-and-set/clear functions. All atomic bit functions allow (and indeed, require) the caller to specify a memory order. RFC v4: * Add atomic bit flip. * Mark macro-generated private functions experimental. RFC v3: * Work around lack of C++ support for _Generic (Tyler Retzlaff). RFC v2: o Add rte_bit_atomic_test_and_assign() (for consistency). o Fix bugs in rte_bit_atomic_test_and_[set|clear](). o Use to support MSVC. Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup Acked-by: Tyler Retzlaff --- lib/eal/include/rte_bitops.h | 425 +++++++++++++++++++++++++++++++++++ 1 file changed, 425 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index f77bd83e97..abfe96d531 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -21,6 +21,7 @@ #include #include +#include #ifdef __cplusplus extern "C" { @@ -395,6 +396,199 @@ extern "C" { uint32_t *: __rte_bit_once_flip32, \ uint64_t *: __rte_bit_once_flip64)(addr, nr) +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Test if a particular bit in a word is set with a particular memory + * order. + * + * Test a bit with the resulting memory load ordered as per the + * specified memory order. + * + * @param addr + * A pointer to the word to query. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit is set, and false otherwise. + */ +#define rte_bit_atomic_test(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test32, \ + uint64_t *: __rte_bit_atomic_test64)(addr, nr, memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically set bit in word. + * + * Atomically set bit specified by @c nr in the word pointed to by @c + * addr to '1', with the memory ordering as specified by @c + * memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + */ +#define rte_bit_atomic_set(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_set32, \ + uint64_t *: __rte_bit_atomic_set64)(addr, nr, memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically clear bit in word. + * + * Atomically set bit specified by @c nr in the word pointed to by @c + * addr to '0', with the memory ordering as specified by @c + * memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + */ +#define rte_bit_atomic_clear(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_clear32, \ + uint64_t *: __rte_bit_atomic_clear64)(addr, nr, memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically assign a value to bit in word. + * + * Atomically set bit specified by @c nr in the word pointed to by @c + * addr to the value indicated by @c value, with the memory ordering + * as specified with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + * @param memory_order + * The memory order to use. See for details. + */ +#define rte_bit_atomic_assign(addr, nr, value, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_assign32, \ + uint64_t *: __rte_bit_atomic_assign64)(addr, nr, value, \ + memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically flip bit in word. + * + * Atomically negate the value of the bit specified by @c nr in the + * word pointed to by @c addr to the value indicated by @c value, with + * the memory ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + */ +#define rte_bit_atomic_flip(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_flip32, \ + uint64_t *: __rte_bit_atomic_flip64)(addr, nr, memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically test and set a bit in word. + * + * Atomically test and set bit specified by @c nr in the word pointed + * to by @c addr to '1', with the memory ordering as specified with @c + * memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +#define rte_bit_atomic_test_and_set(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test_and_set32, \ + uint64_t *: __rte_bit_atomic_test_and_set64)(addr, nr, \ + memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically test and clear a bit in word. + * + * Atomically test and clear bit specified by @c nr in the word + * pointed to by @c addr to '0', with the memory ordering as specified + * with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +#define rte_bit_atomic_test_and_clear(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test_and_clear32, \ + uint64_t *: __rte_bit_atomic_test_and_clear64)(addr, nr, \ + memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically test and assign a bit in word. + * + * Atomically test and assign bit specified by @c nr in the word + * pointed to by @c addr the value specified by @c value, with the + * memory ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + * @param memory_order + * The memory order to use. See for details. + * @return + * Returns true if the bit was set, and false otherwise. + */ +#define rte_bit_atomic_test_and_assign(addr, nr, value, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test_and_assign32, \ + uint64_t *: __rte_bit_atomic_test_and_assign64)(addr, nr, \ + value, \ + memory_order) + #define __RTE_GEN_BIT_TEST(family, fun, qualifier, size) \ __rte_experimental \ static inline bool \ @@ -479,6 +673,162 @@ __RTE_GEN_BIT_CLEAR(once_, clear, volatile, 64) __RTE_GEN_BIT_ASSIGN(once_, assign, volatile, 64) __RTE_GEN_BIT_FLIP(once_, flip, volatile, 64) +#define __RTE_GEN_BIT_ATOMIC_TEST(size) \ + __rte_experimental \ + static inline bool \ + __rte_bit_atomic_test ## size(const uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + const RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (const RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + return rte_atomic_load_explicit(a_addr, memory_order) & mask; \ + } + +#define __RTE_GEN_BIT_ATOMIC_SET(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_set ## size(uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + rte_atomic_fetch_or_explicit(a_addr, mask, memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_CLEAR(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_clear ## size(uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + rte_atomic_fetch_and_explicit(a_addr, ~mask, memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_ASSIGN(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_assign ## size(uint ## size ## _t *addr, \ + unsigned int nr, bool value, \ + int memory_order) \ + { \ + if (value) \ + __rte_bit_atomic_set ## size(addr, nr, memory_order); \ + else \ + __rte_bit_atomic_clear ## size(addr, nr, \ + memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size) \ + __rte_experimental \ + static inline bool \ + __rte_bit_atomic_test_and_assign ## size(uint ## size ## _t *addr, \ + unsigned int nr, \ + bool value, \ + int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t before; \ + uint ## size ## _t target; \ + \ + before = rte_atomic_load_explicit(a_addr, \ + rte_memory_order_relaxed); \ + \ + do { \ + target = before; \ + __rte_bit_assign ## size(&target, nr, value); \ + } while (!rte_atomic_compare_exchange_weak_explicit( \ + a_addr, &before, target, \ + rte_memory_order_relaxed, \ + memory_order)); \ + return __rte_bit_test ## size(&before, nr); \ + } + +#define __RTE_GEN_BIT_ATOMIC_FLIP(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_flip ## size(uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t before; \ + uint ## size ## _t target; \ + \ + before = rte_atomic_load_explicit(a_addr, \ + rte_memory_order_relaxed); \ + \ + do { \ + target = before; \ + __rte_bit_flip ## size(&target, nr); \ + } while (!rte_atomic_compare_exchange_weak_explicit( \ + a_addr, &before, target, \ + rte_memory_order_relaxed, \ + memory_order)); \ + } + +#define __RTE_GEN_BIT_ATOMIC_OPS(size) \ + __RTE_GEN_BIT_ATOMIC_TEST(size) \ + __RTE_GEN_BIT_ATOMIC_SET(size) \ + __RTE_GEN_BIT_ATOMIC_CLEAR(size) \ + __RTE_GEN_BIT_ATOMIC_ASSIGN(size) \ + __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size) \ + __RTE_GEN_BIT_ATOMIC_FLIP(size) + +__RTE_GEN_BIT_ATOMIC_OPS(32) +__RTE_GEN_BIT_ATOMIC_OPS(64) + +__rte_experimental +static inline bool +__rte_bit_atomic_test_and_set32(uint32_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign32(addr, nr, true, + memory_order); +} + +__rte_experimental +static inline bool +__rte_bit_atomic_test_and_clear32(uint32_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign32(addr, nr, false, + memory_order); +} + +__rte_experimental +static inline bool +__rte_bit_atomic_test_and_set64(uint64_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign64(addr, nr, true, + memory_order); +} + +__rte_experimental +static inline bool +__rte_bit_atomic_test_and_clear64(uint64_t *addr, unsigned int nr, + int memory_order) +{ + return __rte_bit_atomic_test_and_assign64(addr, nr, false, + memory_order); +} + /*------------------------ 32-bit relaxed operations ------------------------*/ /** @@ -1180,6 +1530,14 @@ rte_log2_u64(uint64_t v) #undef rte_bit_once_assign #undef rte_bit_once_flip +#undef rte_bit_atomic_test +#undef rte_bit_atomic_set +#undef rte_bit_atomic_clear +#undef rte_bit_atomic_assign +#undef rte_bit_atomic_test_and_set +#undef rte_bit_atomic_test_and_clear +#undef rte_bit_atomic_test_and_assign + #define __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, size, arg1_type, arg1_name) \ static inline void \ rte_bit_ ## fun(qualifier uint ## size ## _t *addr, \ @@ -1223,6 +1581,59 @@ rte_log2_u64(uint64_t v) __RTE_BIT_OVERLOAD_SZ_3(fun, qualifier, 64, arg1_type, arg1_name, \ arg2_type, arg2_name) +#define __RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, size, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name) \ + static inline ret_type \ + rte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name, \ + arg2_type arg2_name) \ + { \ + return __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name); \ + } + +#define __RTE_BIT_OVERLOAD_3R(fun, qualifier, ret_type, arg1_type, arg1_name, \ + arg2_type, arg2_name) \ + __RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, 32, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name) \ + __RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, 64, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name) + +#define __RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, size, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) \ + static inline void \ + rte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name, \ + arg2_type arg2_name, arg3_type arg3_name) \ + { \ + __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name, \ + arg3_name); \ + } + +#define __RTE_BIT_OVERLOAD_4(fun, qualifier, arg1_type, arg1_name, arg2_type, \ + arg2_name, arg3_type, arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, 32, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, 64, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) + +#define __RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, size, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name, arg3_type, \ + arg3_name) \ + static inline ret_type \ + rte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name, \ + arg2_type arg2_name, arg3_type arg3_name) \ + { \ + return __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name, \ + arg3_name); \ + } + +#define __RTE_BIT_OVERLOAD_4R(fun, qualifier, ret_type, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, 32, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name, arg3_type, \ + arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, 64, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name, arg3_type, \ + arg3_name) + __RTE_BIT_OVERLOAD_2R(test, const, bool, unsigned int, nr) __RTE_BIT_OVERLOAD_2(set,, unsigned int, nr) __RTE_BIT_OVERLOAD_2(clear,, unsigned int, nr) @@ -1235,6 +1646,20 @@ __RTE_BIT_OVERLOAD_2(once_clear, volatile, unsigned int, nr) __RTE_BIT_OVERLOAD_3(once_assign, volatile, unsigned int, nr, bool, value) __RTE_BIT_OVERLOAD_2(once_flip, volatile, unsigned int, nr) +__RTE_BIT_OVERLOAD_3R(atomic_test, const, bool, unsigned int, nr, + int, memory_order) +__RTE_BIT_OVERLOAD_3(atomic_set,, unsigned int, nr, int, memory_order) +__RTE_BIT_OVERLOAD_3(atomic_clear,, unsigned int, nr, int, memory_order) +__RTE_BIT_OVERLOAD_4(atomic_assign,, unsigned int, nr, bool, value, + int, memory_order) +__RTE_BIT_OVERLOAD_3(atomic_flip,, unsigned int, nr, int, memory_order) +__RTE_BIT_OVERLOAD_3R(atomic_test_and_set,, bool, unsigned int, nr, + int, memory_order) +__RTE_BIT_OVERLOAD_3R(atomic_test_and_clear,, bool, unsigned int, nr, + int, memory_order) +__RTE_BIT_OVERLOAD_4R(atomic_test_and_assign,, bool, unsigned int, nr, + bool, value, int, memory_order) + #endif #endif /* _RTE_BITOPS_H_ */ -- 2.34.1