[PATCH 01/10] common/cnxk: sync VF root weight with kernel

[PATCH 01/10] common/cnxk: sync VF root weight with kernel

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

By default set VF root scheduling weight same as other kernel
configured VFs. Also fix a compilation issue when cflags has
-Werror=shadow=compatible-local.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/common/cnxk/roc_nix.h       | 1 +
 drivers/common/cnxk/roc_nix_queue.c | 3 ++-
 drivers/common/cnxk/roc_nix_tm.c    | 6 +++++-
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index bd3e540f45..63bcd5b25e 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -473,6 +473,7 @@ struct roc_nix {
 	bool force_rx_aura_bp;
 	bool custom_meta_aura_ena;
 	bool rx_inj_ena;
+	uint32_t root_sched_weight;
 	/* End of input parameters */
 	/* LMT line base for "Per Core Tx LMT line" mode*/
 	uintptr_t lmt_base;
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index ae4e0ea40c..f5441e0e6b 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -1030,7 +1030,8 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
 	thr = PLT_DIV_CEIL((nb_sqb_bufs * ROC_NIX_SQB_THRESH), 100);
 	nb_sqb_bufs += NIX_SQB_PREFETCH;
 	/* Clamp up the SQB count */
-	nb_sqb_bufs = PLT_MIN(roc_nix->max_sqb_count, (uint16_t)PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs));
+	nb_sqb_bufs = PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs);
+	nb_sqb_bufs = PLT_MIN(roc_nix->max_sqb_count, (uint16_t)nb_sqb_bufs);
 
 	sq->nb_sqb_bufs = nb_sqb_bufs;
 	sq->sqes_per_sqb_log2 = (uint16_t)plt_log2_u32(sqes_per_sqb);
diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c
index 4e6a28f827..ac522f8235 100644
--- a/drivers/common/cnxk/roc_nix_tm.c
+++ b/drivers/common/cnxk/roc_nix_tm.c
@@ -1589,7 +1589,11 @@ nix_tm_prepare_default_tree(struct roc_nix *roc_nix)
 		node->id = nonleaf_id;
 		node->parent_id = parent;
 		node->priority = 0;
-		node->weight = NIX_TM_DFLT_RR_WT;
+		/* Default VF root RR_QUANTUM is in sync with kernel */
+		if (lvl == ROC_TM_LVL_ROOT && !nix_tm_have_tl1_access(nix))
+			node->weight = roc_nix->root_sched_weight;
+		else
+			node->weight = NIX_TM_DFLT_RR_WT;
 		node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
 		node->lvl = lvl;
 		node->tree = ROC_NIX_TM_DEFAULT;
-- 
2.25.1

[PATCH 02/10] net/cnxk: set VF default root schedule weight

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

To get better performance on LBK or VF interfaces, set the default
root schedule weight to known tested value.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 95a3d8aaf9..1bccebad9f 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -7,6 +7,8 @@
 
 #define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL)
 
+#define NIX_TM_DFLT_RR_WT 71
+
 static inline uint64_t
 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
 {
@@ -1884,6 +1886,8 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
 	nix->pci_dev = pci_dev;
 	nix->hw_vlan_ins = true;
 	nix->port_id = eth_dev->data->port_id;
+	/* For better performance set default VF root schedule weight */
+	nix->root_sched_weight = NIX_TM_DFLT_RR_WT;
 	if (roc_feature_nix_has_own_meta_aura())
 		nix->local_meta_aura_ena = true;
 	rc = roc_nix_dev_init(nix);
-- 
2.25.1

[PATCH 03/10] net/cnxk: fix extbuf handling for multisegment packet

[Nithin Dabilpuram]

From: Rakesh Kudurumalla <rkudurumalla@marvell.com>

Avoid double free of extbuf when during TX path in
multisegmented packet with extbuf as one of segment.

Fixes: dd9446991212 ("net/cnxk: add transmit completion handler")
Cc: stable@dpdk.org

Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
 drivers/net/cnxk/cn9k_tx.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h
index 6fc9e4d758..b56881c561 100644
--- a/drivers/net/cnxk/cn9k_tx.h
+++ b/drivers/net/cnxk/cn9k_tx.h
@@ -117,6 +117,7 @@ cn9k_nix_prefree_seg(struct rte_mbuf *m, struct rte_mbuf **extm, struct cn9k_eth
 			send_hdr->w1.sqe_id = sqe_id &
 				txq->tx_compl.nb_desc_mask;
 			txq->tx_compl.ptr[send_hdr->w1.sqe_id] = m;
+			m->next = NULL;
 		}
 		return 1;
 	} else {
-- 
2.25.1

[PATCH 04/10] common/cnxk: override UDP encap ports with session data

[Nithin Dabilpuram]

Override UDP encap ports with session info when non-zero on cn10k.
This makes the UDP encap ports configurable by user as needed.
Default UDP source and destination ports will still be 4500.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/cnxk_security.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
index bab015e3b3..15b0bedf43 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -308,6 +308,7 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 			  struct rte_crypto_sym_xform *crypto_xfrm,
 			  bool is_inline)
 {
+	uint16_t sport = 4500, dport = 4500;
 	union roc_ot_ipsec_sa_word2 w2;
 	uint32_t replay_win_sz;
 	size_t offset;
@@ -353,8 +354,14 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 	/* ESN */
 	sa->w2.s.esn_en = !!ipsec_xfrm->options.esn;
 	if (ipsec_xfrm->options.udp_encap) {
-		sa->w10.s.udp_src_port = 4500;
-		sa->w10.s.udp_dst_port = 4500;
+		if (ipsec_xfrm->udp.sport)
+			sport = ipsec_xfrm->udp.sport;
+
+		if (ipsec_xfrm->udp.dport)
+			dport = ipsec_xfrm->udp.dport;
+
+		sa->w10.s.udp_src_port = sport;
+		sa->w10.s.udp_dst_port = dport;
 	}
 
 	if (ipsec_xfrm->options.udp_ports_verify)
@@ -411,6 +418,7 @@ cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
 			   struct rte_crypto_sym_xform *crypto_xfrm)
 {
 	struct rte_security_ipsec_tunnel_param *tunnel = &ipsec_xfrm->tunnel;
+	uint16_t sport = 4500, dport = 4500;
 	union roc_ot_ipsec_sa_word2 w2;
 	size_t offset;
 	int rc;
@@ -506,8 +514,14 @@ cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
 		sa->ctx.esn_val = ipsec_xfrm->esn.value - 1;
 
 	if (ipsec_xfrm->options.udp_encap) {
-		sa->w10.s.udp_src_port = 4500;
-		sa->w10.s.udp_dst_port = 4500;
+		if (ipsec_xfrm->udp.sport)
+			sport = ipsec_xfrm->udp.sport;
+
+		if (ipsec_xfrm->udp.dport)
+			dport = ipsec_xfrm->udp.dport;
+
+		sa->w10.s.udp_src_port = sport;
+		sa->w10.s.udp_dst_port = dport;
 	}
 
 	offset = offsetof(struct roc_ot_ipsec_outb_sa, ctx);
-- 
2.25.1

[PATCH 05/10] net/cnxk: update SA userdata and keep original cookie

[Nithin Dabilpuram]

Update SA userdata as part of session_update() and
keep the original cookie that is used to identify
SA.

Fixes: 8efa348e8160 ("net/cnxk: support custom SA index")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 57 ++++++++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 2 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index af27d3bbc1..eed4c29218 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -1101,8 +1101,8 @@ cn10k_eth_sec_session_update(void *device, struct rte_security_session *sess,
 {
 	struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device;
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
-	struct roc_ot_ipsec_inb_sa *inb_sa_dptr;
 	struct rte_security_ipsec_xform *ipsec;
+	struct cn10k_sec_sess_priv sess_priv;
 	struct rte_crypto_sym_xform *crypto;
 	struct cnxk_eth_sec_sess *eth_sec;
 	bool inbound;
@@ -1123,6 +1123,11 @@ cn10k_eth_sec_session_update(void *device, struct rte_security_session *sess,
 	eth_sec->spi = conf->ipsec.spi;
 
 	if (inbound) {
+		struct roc_ot_ipsec_inb_sa *inb_sa_dptr, *inb_sa;
+		struct cn10k_inb_priv_data *inb_priv;
+
+		inb_sa = eth_sec->sa;
+		inb_priv = roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(inb_sa);
 		inb_sa_dptr = (struct roc_ot_ipsec_inb_sa *)dev->inb.sa_dptr;
 		memset(inb_sa_dptr, 0, sizeof(struct roc_ot_ipsec_inb_sa));
 
@@ -1130,26 +1135,74 @@ cn10k_eth_sec_session_update(void *device, struct rte_security_session *sess,
 					       true);
 		if (rc)
 			return -EINVAL;
+		/* Use cookie for original data */
+		inb_sa_dptr->w1.s.cookie = inb_sa->w1.s.cookie;
+
+		if (ipsec->options.stats == 1) {
+			/* Enable mib counters */
+			inb_sa_dptr->w0.s.count_mib_bytes = 1;
+			inb_sa_dptr->w0.s.count_mib_pkts = 1;
+		}
+
+		/* Enable out-of-place processing */
+		if (ipsec->options.ingress_oop)
+			inb_sa_dptr->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_FULL;
 
 		rc = roc_nix_inl_ctx_write(&dev->nix, inb_sa_dptr, eth_sec->sa,
 					   eth_sec->inb,
 					   sizeof(struct roc_ot_ipsec_inb_sa));
 		if (rc)
 			return -EINVAL;
+
+		/* Save userdata in inb private area */
+		inb_priv->userdata = conf->userdata;
 	} else {
-		struct roc_ot_ipsec_outb_sa *outb_sa_dptr;
+		struct roc_ot_ipsec_outb_sa *outb_sa_dptr, *outb_sa;
+		struct cn10k_outb_priv_data *outb_priv;
+		struct cnxk_ipsec_outb_rlens *rlens;
 
+		outb_sa = eth_sec->sa;
+		outb_priv = roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(outb_sa);
+		rlens = &outb_priv->rlens;
 		outb_sa_dptr = (struct roc_ot_ipsec_outb_sa *)dev->outb.sa_dptr;
 		memset(outb_sa_dptr, 0, sizeof(struct roc_ot_ipsec_outb_sa));
 
 		rc = cnxk_ot_ipsec_outb_sa_fill(outb_sa_dptr, ipsec, crypto);
 		if (rc)
 			return -EINVAL;
+
+		/* Save rlen info */
+		cnxk_ipsec_outb_rlens_get(rlens, ipsec, crypto);
+
+		if (ipsec->options.stats == 1) {
+			/* Enable mib counters */
+			outb_sa_dptr->w0.s.count_mib_bytes = 1;
+			outb_sa_dptr->w0.s.count_mib_pkts = 1;
+		}
+
+		sess_priv.u64 = 0;
+		sess_priv.sa_idx = outb_priv->sa_idx;
+		sess_priv.roundup_byte = rlens->roundup_byte;
+		sess_priv.roundup_len = rlens->roundup_len;
+		sess_priv.partial_len = rlens->partial_len;
+		sess_priv.mode = outb_sa_dptr->w2.s.ipsec_mode;
+		sess_priv.outer_ip_ver = outb_sa_dptr->w2.s.outer_ip_ver;
+		/* Propagate inner checksum enable from SA to fast path */
+		sess_priv.chksum =
+			(!ipsec->options.ip_csum_enable << 1 | !ipsec->options.l4_csum_enable);
+		sess_priv.dec_ttl = ipsec->options.dec_ttl;
+		if (roc_feature_nix_has_inl_ipsec_mseg() && dev->outb.cpt_eng_caps & BIT_ULL(35))
+			sess_priv.nixtx_off = 1;
+
 		rc = roc_nix_inl_ctx_write(&dev->nix, outb_sa_dptr, eth_sec->sa,
 					   eth_sec->inb,
 					   sizeof(struct roc_ot_ipsec_outb_sa));
 		if (rc)
 			return -EINVAL;
+
+		/* Save userdata */
+		outb_priv->userdata = conf->userdata;
+		sess->fast_mdata = sess_priv.u64;
 	}
 
 	return 0;
-- 
2.25.1

[PATCH 06/10] net/cnxk: add option to disable custom meta aura

[Nithin Dabilpuram]

Add option to explicitly disable custom meta aura. Currently
custom meta aura is enabled automatically when inl_cpt_channel
is set i.e inline dev is masking CHAN field in IPsec rules.

Also decouple the custom meta aura feature from custom sa action
so that the custom sa action can independently be used.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 doc/guides/nics/cnxk.rst               | 13 +++++++++++++
 drivers/common/cnxk/roc_nix_inl.c      | 19 +++++++++++++------
 drivers/common/cnxk/roc_nix_inl.h      |  1 +
 drivers/common/cnxk/version.map        |  1 +
 drivers/net/cnxk/cnxk_ethdev.c         |  5 +++++
 drivers/net/cnxk/cnxk_ethdev.h         |  3 +++
 drivers/net/cnxk/cnxk_ethdev_devargs.c |  8 +++++++-
 7 files changed, 43 insertions(+), 7 deletions(-)

diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index f5f296ee36..99ad224efd 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -444,6 +444,19 @@ Runtime Config Options
    With the above configuration, driver would enable packet inject from ARM cores
    to crypto to process and send back in Rx path.
 
+- ``Disable custom meta aura feature`` (default ``0``)
+
+   Custom meta aura i.e 1:N meta aura is enabled for second pass traffic by default when
+   ``inl_cpt_channel`` devarg is provided. Provide an option to disable the custom
+   meta aura feature by setting devarg ``custom_meta_aura_dis`` to ``1``.
+
+   For example::
+
+     -a 0002:02:00.0,custom_meta_aura_dis=1
+
+   With the above configuration, driver would disable custom meta aura feature for
+   ``0002:02:00.0`` ethdev.
+
 .. note::
 
    Above devarg parameters are configurable per device, user needs to pass the
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 7dbeae5017..74a688abbd 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -872,7 +872,6 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)
 	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct roc_cpt_inline_ipsec_inb_cfg cfg;
 	struct idev_cfg *idev = idev_get_cfg();
-	struct nix_inl_dev *inl_dev;
 	uint16_t bpids[ROC_NIX_MAX_BPID_CNT];
 	struct roc_cpt *roc_cpt;
 	int rc;
@@ -929,11 +928,6 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)
 	if (rc)
 		return rc;
 
-	inl_dev = idev->nix_inl_dev;
-
-	roc_nix->custom_meta_aura_ena = (roc_nix->local_meta_aura_ena &&
-					 ((inl_dev && inl_dev->is_multi_channel) ||
-					  roc_nix->custom_sa_action));
 	if (!roc_model_is_cn9k() && !roc_errata_nix_no_meta_aura()) {
 		nix->need_meta_aura = true;
 		if (!roc_nix->local_meta_aura_ena || roc_nix->custom_meta_aura_ena)
@@ -1245,6 +1239,19 @@ roc_nix_inl_dev_is_probed(void)
 	return !!idev->nix_inl_dev;
 }
 
+bool
+roc_nix_inl_dev_is_multi_channel(void)
+{
+	struct idev_cfg *idev = idev_get_cfg();
+	struct nix_inl_dev *inl_dev;
+
+	if (idev == NULL || !idev->nix_inl_dev)
+		return false;
+
+	inl_dev = idev->nix_inl_dev;
+	return inl_dev->is_multi_channel;
+}
+
 bool
 roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix)
 {
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index 8acd7e0545..ab0965e512 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -115,6 +115,7 @@ int __roc_api roc_nix_inl_dev_stats_get(struct roc_nix_stats *stats);
 uint16_t __roc_api roc_nix_inl_dev_pffunc_get(void);
 int __roc_api roc_nix_inl_dev_cpt_setup(bool use_inl_dev_sso);
 int __roc_api roc_nix_inl_dev_cpt_release(void);
+bool __roc_api roc_nix_inl_dev_is_multi_channel(void);
 
 /* NIX Inline Inbound API */
 int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 424ad7f484..e8d32b331e 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -238,6 +238,7 @@ INTERNAL {
 	roc_nix_inl_dev_dump;
 	roc_nix_inl_dev_fini;
 	roc_nix_inl_dev_init;
+	roc_nix_inl_dev_is_multi_channel;
 	roc_nix_inl_dev_is_probed;
 	roc_nix_inl_dev_stats_get;
 	roc_nix_inl_dev_lock;
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 1bccebad9f..db8feca620 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -107,6 +107,11 @@ nix_security_setup(struct cnxk_eth_dev *dev)
 		nix->ipsec_in_min_spi = dev->inb.no_inl_dev ? dev->inb.min_spi : 0;
 		nix->ipsec_in_max_spi = dev->inb.no_inl_dev ? dev->inb.max_spi : 1;
 
+		/* Enable custom meta aura when multi-chan is used */
+		if (nix->local_meta_aura_ena && roc_nix_inl_dev_is_multi_channel() &&
+		    !dev->inb.custom_meta_aura_dis)
+			nix->custom_meta_aura_ena = true;
+
 		/* Setup Inline Inbound */
 		rc = roc_nix_inl_inb_init(nix);
 		if (rc) {
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 5e040643ab..687c60c27d 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -257,6 +257,9 @@ struct cnxk_eth_dev_sec_inb {
 
 	/* Lock to synchronize sa setup/release */
 	rte_spinlock_t lock;
+
+	/* Disable custom meta aura */
+	bool custom_meta_aura_dis;
 };
 
 /* Outbound security data */
diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index 1bab19fc23..3454295d7d 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -280,6 +280,7 @@ parse_val_u16(const char *key, const char *value, void *extra_args)
 #define CNXK_NIX_META_BUF_SZ	"meta_buf_sz"
 #define CNXK_FLOW_AGING_POLL_FREQ	"aging_poll_freq"
 #define CNXK_NIX_RX_INJ_ENABLE	"rx_inj_ena"
+#define CNXK_CUSTOM_META_AURA_DIS "custom_meta_aura_dis"
 
 int
 cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
@@ -291,6 +292,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	uint32_t ipsec_in_max_spi = BIT(8) - 1;
 	uint16_t sqb_slack = ROC_NIX_SQB_SLACK;
 	uint32_t ipsec_out_max_sa = BIT(12);
+	uint16_t custom_meta_aura_dis = 0;
 	uint16_t flow_prealloc_size = 1;
 	uint16_t switch_header_type = 0;
 	uint16_t flow_max_priority = 3;
@@ -358,6 +360,8 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	rte_kvargs_process(kvlist, CNXK_FLOW_AGING_POLL_FREQ, &parse_val_u16,
 			   &aging_thread_poll_freq);
 	rte_kvargs_process(kvlist, CNXK_NIX_RX_INJ_ENABLE, &parse_flag, &rx_inj_ena);
+	rte_kvargs_process(kvlist, CNXK_CUSTOM_META_AURA_DIS, &parse_flag,
+			   &custom_meta_aura_dis);
 	rte_kvargs_free(kvlist);
 
 null_devargs:
@@ -366,6 +370,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	dev->inb.no_inl_dev = !!no_inl_dev;
 	dev->inb.min_spi = ipsec_in_min_spi;
 	dev->inb.max_spi = ipsec_in_max_spi;
+	dev->inb.custom_meta_aura_dis = custom_meta_aura_dis;
 	dev->outb.max_sa = ipsec_out_max_sa;
 	dev->outb.nb_desc = outb_nb_desc;
 	dev->outb.nb_crypto_qs = outb_nb_crypto_qs;
@@ -415,4 +420,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_cnxk,
 			      CNXK_CUSTOM_SA_ACT "=1"
 			      CNXK_SQB_SLACK "=<12-512>"
 			      CNXK_FLOW_AGING_POLL_FREQ "=<10-65535>"
-			      CNXK_NIX_RX_INJ_ENABLE "=1");
+			      CNXK_NIX_RX_INJ_ENABLE "=1"
+			      CNXK_CUSTOM_META_AURA_DIS "=1");
-- 
2.25.1

Re: [PATCH 06/10] net/cnxk: add option to disable custom meta aura

[Jerin Jacob]

On Fri, May 17, 2024 at 1:23 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> Add option to explicitly disable custom meta aura. Currently
> custom meta aura is enabled automatically when inl_cpt_channel
> is set i.e inline dev is masking CHAN field in IPsec rules.
>
> Also decouple the custom meta aura feature from custom sa action
> so that the custom sa action can independently be used.
>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> ---
>  doc/guides/nics/cnxk.rst               | 13 +++++++++++++
>  drivers/common/cnxk/roc_nix_inl.c      | 19 +++++++++++++------
>  drivers/common/cnxk/roc_nix_inl.h      |  1 +
>  drivers/common/cnxk/version.map        |  1 +
>  drivers/net/cnxk/cnxk_ethdev.c         |  5 +++++
>  drivers/net/cnxk/cnxk_ethdev.h         |  3 +++
>  drivers/net/cnxk/cnxk_ethdev_devargs.c |  8 +++++++-
>  7 files changed, 43 insertions(+), 7 deletions(-)
>
> diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
> index f5f296ee36..99ad224efd 100644
> --- a/doc/guides/nics/cnxk.rst
> +++ b/doc/guides/nics/cnxk.rst
> @@ -444,6 +444,19 @@ Runtime Config Options
>     With the above configuration, driver would enable packet inject from ARM cores
>     to crypto to process and send back in Rx path.
>
> +- ``Disable custom meta aura feature`` (default ``0``)
> +
> +   Custom meta aura i.e 1:N meta aura is enabled for second pass traffic by default when
> +   ``inl_cpt_channel`` devarg is provided. Provide an option to disable the custom
> +   meta aura feature by setting devarg ``custom_meta_aura_dis`` to ``1``.


Update release notes for PMD section for this new feature.

> +
> +   For example::
> +
> +     -a 0002:02:00.0,custom_meta_aura_dis=1
> +
> +   With the above configuration, driver would disable custom meta aura feature for
> +   ``0002:02:00.0`` ethdev.
> +
>  .. note::

[PATCH 07/10] net/cnxk: fix issue with outbound security higher pkt burst

[Nithin Dabilpuram]

Fix issue with outbound security path while handling mixed traffic i.e
both plain and inline outbound pkts being present as part of burst
and burst size is > 32. The loop needs to be broken when
we don't have space for 4 pkts in LMT lines for CPT considering
both the full lmt lines and partial lmt lines used.

Fixes: 55bfac717c72 ("net/cnxk: support Tx security offload on cn10k")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_tx.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 3818b0445a..84b08403c0 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -2272,7 +2272,8 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,
 	}
 
 	for (i = 0; i < burst; i += NIX_DESCS_PER_LOOP) {
-		if (flags & NIX_TX_OFFLOAD_SECURITY_F && c_lnum + 2 > 16) {
+		if (flags & NIX_TX_OFFLOAD_SECURITY_F &&
+		    (((int)((16 - c_lnum) << 1) - c_loff) < 4)) {
 			burst = i;
 			break;
 		}
-- 
2.25.1

[PATCH 08/10] common/cnxk: add API to reset CGX stats

[Nithin Dabilpuram]

From: Sunil Kumar Kori <skori@marvell.com>

Similar to NIX stats reset API, adding API to reset
CGX stats.

When user requests to reset the stats then it clears
if nix_lf is PF otherwise silently discard the request.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
 drivers/common/cnxk/roc_nix.h     |  1 +
 drivers/common/cnxk/roc_nix_mac.c | 29 +++++++++++++++++++++++++++++
 drivers/common/cnxk/version.map   |  1 +
 3 files changed, 31 insertions(+)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 63bcd5b25e..25cf261348 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -849,6 +849,7 @@ int __roc_api roc_nix_mac_link_info_get_cb_register(
 void __roc_api roc_nix_mac_link_info_get_cb_unregister(struct roc_nix *roc_nix);
 int __roc_api roc_nix_q_err_cb_register(struct roc_nix *roc_nix, q_err_get_t sq_err_handle);
 void __roc_api roc_nix_q_err_cb_unregister(struct roc_nix *roc_nix);
+int __roc_api roc_nix_mac_stats_reset(struct roc_nix *roc_nix);
 
 /* Ops */
 int __roc_api roc_nix_switch_hdr_set(struct roc_nix *roc_nix,
diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c
index 2d1c29dd66..f79aaec4a5 100644
--- a/drivers/common/cnxk/roc_nix_mac.c
+++ b/drivers/common/cnxk/roc_nix_mac.c
@@ -354,6 +354,35 @@ roc_nix_mac_max_rx_len_set(struct roc_nix *roc_nix, uint16_t maxlen)
 	return rc;
 }
 
+int
+roc_nix_mac_stats_reset(struct roc_nix *roc_nix)
+{
+	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+	struct dev *dev = &nix->dev;
+	struct mbox *mbox = mbox_get(dev->mbox);
+	struct msg_req *req;
+	int rc = -ENOSPC;
+
+	if (roc_model_is_cn10k()) {
+		rc = 0;
+		goto exit;
+	}
+
+	if (roc_nix_is_vf_or_sdp(roc_nix)) {
+		rc = 0;
+		goto exit;
+	}
+
+	req = mbox_alloc_msg_cgx_stats_rst(mbox);
+	if (req == NULL)
+		goto exit;
+
+	rc = mbox_process(mbox);
+exit:
+	mbox_put(mbox);
+	return rc;
+}
+
 int
 roc_nix_mac_link_cb_register(struct roc_nix *roc_nix, link_status_t link_update)
 {
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index e8d32b331e..e37c1c7b7d 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -308,6 +308,7 @@ INTERNAL {
 	roc_nix_mac_mtu_set;
 	roc_nix_mac_promisc_mode_enable;
 	roc_nix_mac_rxtx_start_stop;
+	roc_nix_mac_stats_reset;
 	roc_nix_max_pkt_len;
 	roc_nix_mcast_list_free;
 	roc_nix_mcast_list_setup;
-- 
2.25.1

[PATCH 09/10] net/cnxk: clear CGX stats during xstats reset

[Nithin Dabilpuram]

From: Sunil Kumar Kori <skori@marvell.com>

Currently only NIX stats are cleared during xstats
reset and CGX stats are left as it is.

Clearing CGX stats too during xstats reset.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
 drivers/net/cnxk/cnxk_stats.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_stats.c b/drivers/net/cnxk/cnxk_stats.c
index f2f2222c89..469faff405 100644
--- a/drivers/net/cnxk/cnxk_stats.c
+++ b/drivers/net/cnxk/cnxk_stats.c
@@ -316,6 +316,8 @@ cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev)
 			goto exit;
 	}
 
+	/* Reset MAC stats */
+	rc = roc_nix_mac_stats_reset(nix);
 exit:
 	return rc;
 }
-- 
2.25.1

Re: [PATCH 09/10] net/cnxk: clear CGX stats during xstats reset

[Jerin Jacob]

On Fri, May 17, 2024 at 1:16 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Sunil Kumar Kori <skori@marvell.com>
>
> Currently only NIX stats are cleared during xstats
> reset and CGX stats are left as it is.
>
> Clearing CGX stats too during xstats reset.
>
> Signed-off-by: Sunil Kumar Kori <skori@marvell.com>


Change to fix and add Fixes: tag


> ---
>  drivers/net/cnxk/cnxk_stats.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/net/cnxk/cnxk_stats.c b/drivers/net/cnxk/cnxk_stats.c
> index f2f2222c89..469faff405 100644
> --- a/drivers/net/cnxk/cnxk_stats.c
> +++ b/drivers/net/cnxk/cnxk_stats.c
> @@ -316,6 +316,8 @@ cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev)
>                         goto exit;
>         }
>
> +       /* Reset MAC stats */
> +       rc = roc_nix_mac_stats_reset(nix);
>  exit:
>         return rc;
>  }
> --
> 2.25.1
>

[PATCH 10/10] net/cnxk: define CPT HW result format for PMD API

[Nithin Dabilpuram]

From: Srujana Challa <schalla@marvell.com>

Defines CPT HW result format for PMD API,
rte_pmd_cnxk_inl_ipsec_res().

Signed-off-by: Srujana Challa <schalla@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev_sec.c |  4 ++--
 drivers/net/cnxk/rte_pmd_cnxk.h     | 28 ++++++++++++++++++++++++++--
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index eed4c29218..b8b0da5ea9 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -1251,7 +1251,7 @@ rte_pmd_cnxk_hw_sa_write(void *device, struct rte_security_session *sess,
 	return 0;
 }
 
-void *
+union rte_pmd_cnxk_cpt_res_s *
 rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf)
 {
 	const union nix_rx_parse_u *rx;
@@ -1265,7 +1265,7 @@ rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf)
 	rx = (const union nix_rx_parse_u *)(wqe + 8);
 	desc_size = (rx->desc_sizem1 + 1) * 16;
 
-	/* cpt_res_s sits after SG list at 16B aligned address */
+	/* rte_pmd_cnxk_cpt_res_s sits after SG list at 16B aligned address */
 	return (void *)(wqe + 64 + desc_size);
 }
 
diff --git a/drivers/net/cnxk/rte_pmd_cnxk.h b/drivers/net/cnxk/rte_pmd_cnxk.h
index 43f2a7ed9b..67c8329abd 100644
--- a/drivers/net/cnxk/rte_pmd_cnxk.h
+++ b/drivers/net/cnxk/rte_pmd_cnxk.h
@@ -453,6 +453,30 @@ union rte_pmd_cnxk_ipsec_hw_sa {
 	struct rte_pmd_cnxk_ipsec_outb_sa outb;
 };
 
+/** CPT HW result format */
+union rte_pmd_cnxk_cpt_res_s {
+	struct rte_pmd_cpt_cn10k_res_s {
+		uint64_t compcode : 7;
+		uint64_t doneint : 1;
+		uint64_t uc_compcode : 8;
+		uint64_t rlen : 16;
+		uint64_t spi : 32;
+
+		uint64_t esn;
+	} cn10k;
+
+	struct rte_pmd_cpt_cn9k_res_s {
+		uint64_t compcode : 8;
+		uint64_t uc_compcode : 8;
+		uint64_t doneint : 1;
+		uint64_t reserved_17_63 : 47;
+
+		uint64_t reserved_64_127;
+	} cn9k;
+
+	uint64_t u64[2];
+};
+
 /**
  * Read HW SA context from session.
  *
@@ -501,9 +525,9 @@ int rte_pmd_cnxk_hw_sa_write(void *device, struct rte_security_session *sess,
  *   Pointer to packet that was just received and was processed with Inline IPsec.
  *
  * @return
- *   - Pointer to mbuf location where CPT result info is stored on success.
+ *   - Pointer to mbuf location where `union rte_pmd_cnxk_cpt_res_s` is stored on success.
  *   - NULL on failure.
  */
 __rte_experimental
-void *rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf);
+union rte_pmd_cnxk_cpt_res_s *rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf);
 #endif /* _PMD_CNXK_H_ */
-- 
2.25.1

Re: [PATCH 10/10] net/cnxk: define CPT HW result format for PMD API

[Jerin Jacob]

On Fri, May 17, 2024 at 1:16 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Srujana Challa <schalla@marvell.com>
>
> Defines CPT HW result format for PMD API,
> rte_pmd_cnxk_inl_ipsec_res().
>
> Signed-off-by: Srujana Challa <schalla@marvell.com>
> ---
>  drivers/net/cnxk/cn10k_ethdev_sec.c |  4 ++--
>  drivers/net/cnxk/rte_pmd_cnxk.h     | 28 ++++++++++++++++++++++++++--
>  2 files changed, 28 insertions(+), 4 deletions(-)
>

>
> +/** CPT HW result format */
> +union rte_pmd_cnxk_cpt_res_s {
> +       struct rte_pmd_cpt_cn10k_res_s {
> +               uint64_t compcode : 7;

Public API, Please add Doxygen for every symbol and check the
generated HTML files.


> +               uint64_t doneint : 1;
> +               uint64_t uc_compcode : 8;
> +               uint64_t rlen : 16;
> +               uint64_t spi : 32;
> +
> +               uint64_t esn;
> +       } cn10k;
> +
> +       struct rte_pmd_cpt_cn9k_res_s {
> +               uint64_t compcode : 8;
> +               uint64_t uc_compcode : 8;
> +               uint64_t doneint : 1;
> +               uint64_t reserved_17_63 : 47;
> +
> +               uint64_t reserved_64_127;
> +       } cn9k;
> +
> +       uint64_t u64[2];
> +};
> +

> 2.25.1
>

[PATCH v2 01/10] common/cnxk: sync VF root weight with kernel

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

By default set VF root scheduling weight same as other kernel
configured VFs. Also fix a compilation issue when cflags has
-Werror=shadow=compatible-local.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---

v2:
- Added fixes tag to 9/10 and documentation to 10/10, 6/10
  patches

 drivers/common/cnxk/roc_nix.h       | 1 +
 drivers/common/cnxk/roc_nix_queue.c | 3 ++-
 drivers/common/cnxk/roc_nix_tm.c    | 6 +++++-
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index bd3e540f45..63bcd5b25e 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -473,6 +473,7 @@ struct roc_nix {
 	bool force_rx_aura_bp;
 	bool custom_meta_aura_ena;
 	bool rx_inj_ena;
+	uint32_t root_sched_weight;
 	/* End of input parameters */
 	/* LMT line base for "Per Core Tx LMT line" mode*/
 	uintptr_t lmt_base;
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index ae4e0ea40c..f5441e0e6b 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -1030,7 +1030,8 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
 	thr = PLT_DIV_CEIL((nb_sqb_bufs * ROC_NIX_SQB_THRESH), 100);
 	nb_sqb_bufs += NIX_SQB_PREFETCH;
 	/* Clamp up the SQB count */
-	nb_sqb_bufs = PLT_MIN(roc_nix->max_sqb_count, (uint16_t)PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs));
+	nb_sqb_bufs = PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs);
+	nb_sqb_bufs = PLT_MIN(roc_nix->max_sqb_count, (uint16_t)nb_sqb_bufs);
 
 	sq->nb_sqb_bufs = nb_sqb_bufs;
 	sq->sqes_per_sqb_log2 = (uint16_t)plt_log2_u32(sqes_per_sqb);
diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c
index 4e6a28f827..ac522f8235 100644
--- a/drivers/common/cnxk/roc_nix_tm.c
+++ b/drivers/common/cnxk/roc_nix_tm.c
@@ -1589,7 +1589,11 @@ nix_tm_prepare_default_tree(struct roc_nix *roc_nix)
 		node->id = nonleaf_id;
 		node->parent_id = parent;
 		node->priority = 0;
-		node->weight = NIX_TM_DFLT_RR_WT;
+		/* Default VF root RR_QUANTUM is in sync with kernel */
+		if (lvl == ROC_TM_LVL_ROOT && !nix_tm_have_tl1_access(nix))
+			node->weight = roc_nix->root_sched_weight;
+		else
+			node->weight = NIX_TM_DFLT_RR_WT;
 		node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
 		node->lvl = lvl;
 		node->tree = ROC_NIX_TM_DEFAULT;
-- 
2.25.1

[PATCH v2 02/10] net/cnxk: set VF default root schedule weight

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

To get better performance on LBK or VF interfaces, set the default
root schedule weight to known tested value.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 95a3d8aaf9..1bccebad9f 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -7,6 +7,8 @@
 
 #define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL)
 
+#define NIX_TM_DFLT_RR_WT 71
+
 static inline uint64_t
 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
 {
@@ -1884,6 +1886,8 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
 	nix->pci_dev = pci_dev;
 	nix->hw_vlan_ins = true;
 	nix->port_id = eth_dev->data->port_id;
+	/* For better performance set default VF root schedule weight */
+	nix->root_sched_weight = NIX_TM_DFLT_RR_WT;
 	if (roc_feature_nix_has_own_meta_aura())
 		nix->local_meta_aura_ena = true;
 	rc = roc_nix_dev_init(nix);
-- 
2.25.1

[PATCH v2 03/10] net/cnxk: fix extbuf handling for multisegment packet

[Nithin Dabilpuram]

From: Rakesh Kudurumalla <rkudurumalla@marvell.com>

Avoid double free of extbuf when during TX path in
multisegmented packet with extbuf as one of segment.

Fixes: dd9446991212 ("net/cnxk: add transmit completion handler")
Cc: stable@dpdk.org

Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
 drivers/net/cnxk/cn9k_tx.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h
index 6fc9e4d758..b56881c561 100644
--- a/drivers/net/cnxk/cn9k_tx.h
+++ b/drivers/net/cnxk/cn9k_tx.h
@@ -117,6 +117,7 @@ cn9k_nix_prefree_seg(struct rte_mbuf *m, struct rte_mbuf **extm, struct cn9k_eth
 			send_hdr->w1.sqe_id = sqe_id &
 				txq->tx_compl.nb_desc_mask;
 			txq->tx_compl.ptr[send_hdr->w1.sqe_id] = m;
+			m->next = NULL;
 		}
 		return 1;
 	} else {
-- 
2.25.1

[PATCH v2 04/10] common/cnxk: override UDP encap ports with session data

[Nithin Dabilpuram]

Override UDP encap ports with session info when non-zero on cn10k.
This makes the UDP encap ports configurable by user as needed.
Default UDP source and destination ports will still be 4500.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/cnxk_security.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
index bab015e3b3..15b0bedf43 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -308,6 +308,7 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 			  struct rte_crypto_sym_xform *crypto_xfrm,
 			  bool is_inline)
 {
+	uint16_t sport = 4500, dport = 4500;
 	union roc_ot_ipsec_sa_word2 w2;
 	uint32_t replay_win_sz;
 	size_t offset;
@@ -353,8 +354,14 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 	/* ESN */
 	sa->w2.s.esn_en = !!ipsec_xfrm->options.esn;
 	if (ipsec_xfrm->options.udp_encap) {
-		sa->w10.s.udp_src_port = 4500;
-		sa->w10.s.udp_dst_port = 4500;
+		if (ipsec_xfrm->udp.sport)
+			sport = ipsec_xfrm->udp.sport;
+
+		if (ipsec_xfrm->udp.dport)
+			dport = ipsec_xfrm->udp.dport;
+
+		sa->w10.s.udp_src_port = sport;
+		sa->w10.s.udp_dst_port = dport;
 	}
 
 	if (ipsec_xfrm->options.udp_ports_verify)
@@ -411,6 +418,7 @@ cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
 			   struct rte_crypto_sym_xform *crypto_xfrm)
 {
 	struct rte_security_ipsec_tunnel_param *tunnel = &ipsec_xfrm->tunnel;
+	uint16_t sport = 4500, dport = 4500;
 	union roc_ot_ipsec_sa_word2 w2;
 	size_t offset;
 	int rc;
@@ -506,8 +514,14 @@ cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
 		sa->ctx.esn_val = ipsec_xfrm->esn.value - 1;
 
 	if (ipsec_xfrm->options.udp_encap) {
-		sa->w10.s.udp_src_port = 4500;
-		sa->w10.s.udp_dst_port = 4500;
+		if (ipsec_xfrm->udp.sport)
+			sport = ipsec_xfrm->udp.sport;
+
+		if (ipsec_xfrm->udp.dport)
+			dport = ipsec_xfrm->udp.dport;
+
+		sa->w10.s.udp_src_port = sport;
+		sa->w10.s.udp_dst_port = dport;
 	}
 
 	offset = offsetof(struct roc_ot_ipsec_outb_sa, ctx);
-- 
2.25.1

[PATCH v2 05/10] net/cnxk: update SA userdata and keep original cookie

[Nithin Dabilpuram]

Update SA userdata as part of session_update() and
keep the original cookie that is used to identify
SA.

Fixes: 8efa348e8160 ("net/cnxk: support custom SA index")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 57 ++++++++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 2 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index af27d3bbc1..eed4c29218 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -1101,8 +1101,8 @@ cn10k_eth_sec_session_update(void *device, struct rte_security_session *sess,
 {
 	struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device;
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
-	struct roc_ot_ipsec_inb_sa *inb_sa_dptr;
 	struct rte_security_ipsec_xform *ipsec;
+	struct cn10k_sec_sess_priv sess_priv;
 	struct rte_crypto_sym_xform *crypto;
 	struct cnxk_eth_sec_sess *eth_sec;
 	bool inbound;
@@ -1123,6 +1123,11 @@ cn10k_eth_sec_session_update(void *device, struct rte_security_session *sess,
 	eth_sec->spi = conf->ipsec.spi;
 
 	if (inbound) {
+		struct roc_ot_ipsec_inb_sa *inb_sa_dptr, *inb_sa;
+		struct cn10k_inb_priv_data *inb_priv;
+
+		inb_sa = eth_sec->sa;
+		inb_priv = roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(inb_sa);
 		inb_sa_dptr = (struct roc_ot_ipsec_inb_sa *)dev->inb.sa_dptr;
 		memset(inb_sa_dptr, 0, sizeof(struct roc_ot_ipsec_inb_sa));
 
@@ -1130,26 +1135,74 @@ cn10k_eth_sec_session_update(void *device, struct rte_security_session *sess,
 					       true);
 		if (rc)
 			return -EINVAL;
+		/* Use cookie for original data */
+		inb_sa_dptr->w1.s.cookie = inb_sa->w1.s.cookie;
+
+		if (ipsec->options.stats == 1) {
+			/* Enable mib counters */
+			inb_sa_dptr->w0.s.count_mib_bytes = 1;
+			inb_sa_dptr->w0.s.count_mib_pkts = 1;
+		}
+
+		/* Enable out-of-place processing */
+		if (ipsec->options.ingress_oop)
+			inb_sa_dptr->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_FULL;
 
 		rc = roc_nix_inl_ctx_write(&dev->nix, inb_sa_dptr, eth_sec->sa,
 					   eth_sec->inb,
 					   sizeof(struct roc_ot_ipsec_inb_sa));
 		if (rc)
 			return -EINVAL;
+
+		/* Save userdata in inb private area */
+		inb_priv->userdata = conf->userdata;
 	} else {
-		struct roc_ot_ipsec_outb_sa *outb_sa_dptr;
+		struct roc_ot_ipsec_outb_sa *outb_sa_dptr, *outb_sa;
+		struct cn10k_outb_priv_data *outb_priv;
+		struct cnxk_ipsec_outb_rlens *rlens;
 
+		outb_sa = eth_sec->sa;
+		outb_priv = roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(outb_sa);
+		rlens = &outb_priv->rlens;
 		outb_sa_dptr = (struct roc_ot_ipsec_outb_sa *)dev->outb.sa_dptr;
 		memset(outb_sa_dptr, 0, sizeof(struct roc_ot_ipsec_outb_sa));
 
 		rc = cnxk_ot_ipsec_outb_sa_fill(outb_sa_dptr, ipsec, crypto);
 		if (rc)
 			return -EINVAL;
+
+		/* Save rlen info */
+		cnxk_ipsec_outb_rlens_get(rlens, ipsec, crypto);
+
+		if (ipsec->options.stats == 1) {
+			/* Enable mib counters */
+			outb_sa_dptr->w0.s.count_mib_bytes = 1;
+			outb_sa_dptr->w0.s.count_mib_pkts = 1;
+		}
+
+		sess_priv.u64 = 0;
+		sess_priv.sa_idx = outb_priv->sa_idx;
+		sess_priv.roundup_byte = rlens->roundup_byte;
+		sess_priv.roundup_len = rlens->roundup_len;
+		sess_priv.partial_len = rlens->partial_len;
+		sess_priv.mode = outb_sa_dptr->w2.s.ipsec_mode;
+		sess_priv.outer_ip_ver = outb_sa_dptr->w2.s.outer_ip_ver;
+		/* Propagate inner checksum enable from SA to fast path */
+		sess_priv.chksum =
+			(!ipsec->options.ip_csum_enable << 1 | !ipsec->options.l4_csum_enable);
+		sess_priv.dec_ttl = ipsec->options.dec_ttl;
+		if (roc_feature_nix_has_inl_ipsec_mseg() && dev->outb.cpt_eng_caps & BIT_ULL(35))
+			sess_priv.nixtx_off = 1;
+
 		rc = roc_nix_inl_ctx_write(&dev->nix, outb_sa_dptr, eth_sec->sa,
 					   eth_sec->inb,
 					   sizeof(struct roc_ot_ipsec_outb_sa));
 		if (rc)
 			return -EINVAL;
+
+		/* Save userdata */
+		outb_priv->userdata = conf->userdata;
+		sess->fast_mdata = sess_priv.u64;
 	}
 
 	return 0;
-- 
2.25.1

[PATCH v2 06/10] net/cnxk: add option to disable custom meta aura

[Nithin Dabilpuram]

Add option to explicitly disable custom meta aura. Currently
custom meta aura is enabled automatically when inl_cpt_channel
is set i.e inline dev is masking CHAN field in IPsec rules.

Also decouple the custom meta aura feature from custom sa action
so that the custom sa action can independently be used.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 doc/guides/nics/cnxk.rst               | 13 +++++++++++++
 doc/guides/rel_notes/release_24_07.rst |  4 ++++
 drivers/common/cnxk/roc_nix_inl.c      | 19 +++++++++++++------
 drivers/common/cnxk/roc_nix_inl.h      |  1 +
 drivers/common/cnxk/version.map        |  1 +
 drivers/net/cnxk/cnxk_ethdev.c         |  5 +++++
 drivers/net/cnxk/cnxk_ethdev.h         |  3 +++
 drivers/net/cnxk/cnxk_ethdev_devargs.c |  8 +++++++-
 8 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index f5f296ee36..99ad224efd 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -444,6 +444,19 @@ Runtime Config Options
    With the above configuration, driver would enable packet inject from ARM cores
    to crypto to process and send back in Rx path.
 
+- ``Disable custom meta aura feature`` (default ``0``)
+
+   Custom meta aura i.e 1:N meta aura is enabled for second pass traffic by default when
+   ``inl_cpt_channel`` devarg is provided. Provide an option to disable the custom
+   meta aura feature by setting devarg ``custom_meta_aura_dis`` to ``1``.
+
+   For example::
+
+     -a 0002:02:00.0,custom_meta_aura_dis=1
+
+   With the above configuration, driver would disable custom meta aura feature for
+   ``0002:02:00.0`` ethdev.
+
 .. note::
 
    Above devarg parameters are configurable per device, user needs to pass the
diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst
index a69f24cf99..37eadb24d6 100644
--- a/doc/guides/rel_notes/release_24_07.rst
+++ b/doc/guides/rel_notes/release_24_07.rst
@@ -55,6 +55,10 @@ New Features
      Also, make sure to start the actual text at the margin.
      =======================================================
 
+* **Updated Marvell cnxk net driver.**
+
+  * Added support disabling custom meta aura and seperately use custom
+    SA action support.
 
 Removed Items
 -------------
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 7dbeae5017..74a688abbd 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -872,7 +872,6 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)
 	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct roc_cpt_inline_ipsec_inb_cfg cfg;
 	struct idev_cfg *idev = idev_get_cfg();
-	struct nix_inl_dev *inl_dev;
 	uint16_t bpids[ROC_NIX_MAX_BPID_CNT];
 	struct roc_cpt *roc_cpt;
 	int rc;
@@ -929,11 +928,6 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)
 	if (rc)
 		return rc;
 
-	inl_dev = idev->nix_inl_dev;
-
-	roc_nix->custom_meta_aura_ena = (roc_nix->local_meta_aura_ena &&
-					 ((inl_dev && inl_dev->is_multi_channel) ||
-					  roc_nix->custom_sa_action));
 	if (!roc_model_is_cn9k() && !roc_errata_nix_no_meta_aura()) {
 		nix->need_meta_aura = true;
 		if (!roc_nix->local_meta_aura_ena || roc_nix->custom_meta_aura_ena)
@@ -1245,6 +1239,19 @@ roc_nix_inl_dev_is_probed(void)
 	return !!idev->nix_inl_dev;
 }
 
+bool
+roc_nix_inl_dev_is_multi_channel(void)
+{
+	struct idev_cfg *idev = idev_get_cfg();
+	struct nix_inl_dev *inl_dev;
+
+	if (idev == NULL || !idev->nix_inl_dev)
+		return false;
+
+	inl_dev = idev->nix_inl_dev;
+	return inl_dev->is_multi_channel;
+}
+
 bool
 roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix)
 {
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index 8acd7e0545..ab0965e512 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -115,6 +115,7 @@ int __roc_api roc_nix_inl_dev_stats_get(struct roc_nix_stats *stats);
 uint16_t __roc_api roc_nix_inl_dev_pffunc_get(void);
 int __roc_api roc_nix_inl_dev_cpt_setup(bool use_inl_dev_sso);
 int __roc_api roc_nix_inl_dev_cpt_release(void);
+bool __roc_api roc_nix_inl_dev_is_multi_channel(void);
 
 /* NIX Inline Inbound API */
 int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 424ad7f484..e8d32b331e 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -238,6 +238,7 @@ INTERNAL {
 	roc_nix_inl_dev_dump;
 	roc_nix_inl_dev_fini;
 	roc_nix_inl_dev_init;
+	roc_nix_inl_dev_is_multi_channel;
 	roc_nix_inl_dev_is_probed;
 	roc_nix_inl_dev_stats_get;
 	roc_nix_inl_dev_lock;
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 1bccebad9f..db8feca620 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -107,6 +107,11 @@ nix_security_setup(struct cnxk_eth_dev *dev)
 		nix->ipsec_in_min_spi = dev->inb.no_inl_dev ? dev->inb.min_spi : 0;
 		nix->ipsec_in_max_spi = dev->inb.no_inl_dev ? dev->inb.max_spi : 1;
 
+		/* Enable custom meta aura when multi-chan is used */
+		if (nix->local_meta_aura_ena && roc_nix_inl_dev_is_multi_channel() &&
+		    !dev->inb.custom_meta_aura_dis)
+			nix->custom_meta_aura_ena = true;
+
 		/* Setup Inline Inbound */
 		rc = roc_nix_inl_inb_init(nix);
 		if (rc) {
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 5e040643ab..687c60c27d 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -257,6 +257,9 @@ struct cnxk_eth_dev_sec_inb {
 
 	/* Lock to synchronize sa setup/release */
 	rte_spinlock_t lock;
+
+	/* Disable custom meta aura */
+	bool custom_meta_aura_dis;
 };
 
 /* Outbound security data */
diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index 1bab19fc23..3454295d7d 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -280,6 +280,7 @@ parse_val_u16(const char *key, const char *value, void *extra_args)
 #define CNXK_NIX_META_BUF_SZ	"meta_buf_sz"
 #define CNXK_FLOW_AGING_POLL_FREQ	"aging_poll_freq"
 #define CNXK_NIX_RX_INJ_ENABLE	"rx_inj_ena"
+#define CNXK_CUSTOM_META_AURA_DIS "custom_meta_aura_dis"
 
 int
 cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
@@ -291,6 +292,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	uint32_t ipsec_in_max_spi = BIT(8) - 1;
 	uint16_t sqb_slack = ROC_NIX_SQB_SLACK;
 	uint32_t ipsec_out_max_sa = BIT(12);
+	uint16_t custom_meta_aura_dis = 0;
 	uint16_t flow_prealloc_size = 1;
 	uint16_t switch_header_type = 0;
 	uint16_t flow_max_priority = 3;
@@ -358,6 +360,8 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	rte_kvargs_process(kvlist, CNXK_FLOW_AGING_POLL_FREQ, &parse_val_u16,
 			   &aging_thread_poll_freq);
 	rte_kvargs_process(kvlist, CNXK_NIX_RX_INJ_ENABLE, &parse_flag, &rx_inj_ena);
+	rte_kvargs_process(kvlist, CNXK_CUSTOM_META_AURA_DIS, &parse_flag,
+			   &custom_meta_aura_dis);
 	rte_kvargs_free(kvlist);
 
 null_devargs:
@@ -366,6 +370,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	dev->inb.no_inl_dev = !!no_inl_dev;
 	dev->inb.min_spi = ipsec_in_min_spi;
 	dev->inb.max_spi = ipsec_in_max_spi;
+	dev->inb.custom_meta_aura_dis = custom_meta_aura_dis;
 	dev->outb.max_sa = ipsec_out_max_sa;
 	dev->outb.nb_desc = outb_nb_desc;
 	dev->outb.nb_crypto_qs = outb_nb_crypto_qs;
@@ -415,4 +420,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_cnxk,
 			      CNXK_CUSTOM_SA_ACT "=1"
 			      CNXK_SQB_SLACK "=<12-512>"
 			      CNXK_FLOW_AGING_POLL_FREQ "=<10-65535>"
-			      CNXK_NIX_RX_INJ_ENABLE "=1");
+			      CNXK_NIX_RX_INJ_ENABLE "=1"
+			      CNXK_CUSTOM_META_AURA_DIS "=1");
-- 
2.25.1

[PATCH v2 07/10] net/cnxk: fix issue with outbound security higher pkt burst

[Nithin Dabilpuram]

Fix issue with outbound security path while handling mixed traffic i.e
both plain and inline outbound pkts being present as part of burst
and burst size is > 32. The loop needs to be broken when
we don't have space for 4 pkts in LMT lines for CPT considering
both the full lmt lines and partial lmt lines used.

Fixes: 55bfac717c72 ("net/cnxk: support Tx security offload on cn10k")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_tx.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 3818b0445a..84b08403c0 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -2272,7 +2272,8 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,
 	}
 
 	for (i = 0; i < burst; i += NIX_DESCS_PER_LOOP) {
-		if (flags & NIX_TX_OFFLOAD_SECURITY_F && c_lnum + 2 > 16) {
+		if (flags & NIX_TX_OFFLOAD_SECURITY_F &&
+		    (((int)((16 - c_lnum) << 1) - c_loff) < 4)) {
 			burst = i;
 			break;
 		}
-- 
2.25.1

[PATCH v2 08/10] common/cnxk: add API to reset CGX stats

[Nithin Dabilpuram]

From: Sunil Kumar Kori <skori@marvell.com>

Similar to NIX stats reset API, adding API to reset
CGX stats.

When user requests to reset the stats then it clears
if nix_lf is PF otherwise silently discard the request.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
 drivers/common/cnxk/roc_nix.h     |  1 +
 drivers/common/cnxk/roc_nix_mac.c | 29 +++++++++++++++++++++++++++++
 drivers/common/cnxk/version.map   |  1 +
 3 files changed, 31 insertions(+)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 63bcd5b25e..25cf261348 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -849,6 +849,7 @@ int __roc_api roc_nix_mac_link_info_get_cb_register(
 void __roc_api roc_nix_mac_link_info_get_cb_unregister(struct roc_nix *roc_nix);
 int __roc_api roc_nix_q_err_cb_register(struct roc_nix *roc_nix, q_err_get_t sq_err_handle);
 void __roc_api roc_nix_q_err_cb_unregister(struct roc_nix *roc_nix);
+int __roc_api roc_nix_mac_stats_reset(struct roc_nix *roc_nix);
 
 /* Ops */
 int __roc_api roc_nix_switch_hdr_set(struct roc_nix *roc_nix,
diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c
index 2d1c29dd66..f79aaec4a5 100644
--- a/drivers/common/cnxk/roc_nix_mac.c
+++ b/drivers/common/cnxk/roc_nix_mac.c
@@ -354,6 +354,35 @@ roc_nix_mac_max_rx_len_set(struct roc_nix *roc_nix, uint16_t maxlen)
 	return rc;
 }
 
+int
+roc_nix_mac_stats_reset(struct roc_nix *roc_nix)
+{
+	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+	struct dev *dev = &nix->dev;
+	struct mbox *mbox = mbox_get(dev->mbox);
+	struct msg_req *req;
+	int rc = -ENOSPC;
+
+	if (roc_model_is_cn10k()) {
+		rc = 0;
+		goto exit;
+	}
+
+	if (roc_nix_is_vf_or_sdp(roc_nix)) {
+		rc = 0;
+		goto exit;
+	}
+
+	req = mbox_alloc_msg_cgx_stats_rst(mbox);
+	if (req == NULL)
+		goto exit;
+
+	rc = mbox_process(mbox);
+exit:
+	mbox_put(mbox);
+	return rc;
+}
+
 int
 roc_nix_mac_link_cb_register(struct roc_nix *roc_nix, link_status_t link_update)
 {
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index e8d32b331e..e37c1c7b7d 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -308,6 +308,7 @@ INTERNAL {
 	roc_nix_mac_mtu_set;
 	roc_nix_mac_promisc_mode_enable;
 	roc_nix_mac_rxtx_start_stop;
+	roc_nix_mac_stats_reset;
 	roc_nix_max_pkt_len;
 	roc_nix_mcast_list_free;
 	roc_nix_mcast_list_setup;
-- 
2.25.1

[PATCH v2 09/10] net/cnxk: fix xstats reset

[Nithin Dabilpuram]

From: Sunil Kumar Kori <skori@marvell.com>

Currently only NIX stats are cleared during xstats
reset and CGX stats are left as it is.

Clearing CGX stats too during xstats reset.

Fixes: 8075b057b620 ("net/cnxk: support extended statistics")

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
 drivers/net/cnxk/cnxk_stats.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_stats.c b/drivers/net/cnxk/cnxk_stats.c
index f2f2222c89..469faff405 100644
--- a/drivers/net/cnxk/cnxk_stats.c
+++ b/drivers/net/cnxk/cnxk_stats.c
@@ -316,6 +316,8 @@ cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev)
 			goto exit;
 	}
 
+	/* Reset MAC stats */
+	rc = roc_nix_mac_stats_reset(nix);
 exit:
 	return rc;
 }
-- 
2.25.1

[PATCH v2 10/10] net/cnxk: define CPT HW result format for PMD API

[Nithin Dabilpuram]

From: Srujana Challa <schalla@marvell.com>

Defines CPT HW result format for PMD API,
rte_pmd_cnxk_inl_ipsec_res().

Signed-off-by: Srujana Challa <schalla@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev_sec.c |  4 +--
 drivers/net/cnxk/rte_pmd_cnxk.h     | 40 +++++++++++++++++++++++++++--
 2 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index eed4c29218..b8b0da5ea9 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -1251,7 +1251,7 @@ rte_pmd_cnxk_hw_sa_write(void *device, struct rte_security_session *sess,
 	return 0;
 }
 
-void *
+union rte_pmd_cnxk_cpt_res_s *
 rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf)
 {
 	const union nix_rx_parse_u *rx;
@@ -1265,7 +1265,7 @@ rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf)
 	rx = (const union nix_rx_parse_u *)(wqe + 8);
 	desc_size = (rx->desc_sizem1 + 1) * 16;
 
-	/* cpt_res_s sits after SG list at 16B aligned address */
+	/* rte_pmd_cnxk_cpt_res_s sits after SG list at 16B aligned address */
 	return (void *)(wqe + 64 + desc_size);
 }
 
diff --git a/drivers/net/cnxk/rte_pmd_cnxk.h b/drivers/net/cnxk/rte_pmd_cnxk.h
index 43f2a7ed9b..88030046db 100644
--- a/drivers/net/cnxk/rte_pmd_cnxk.h
+++ b/drivers/net/cnxk/rte_pmd_cnxk.h
@@ -453,6 +453,42 @@ union rte_pmd_cnxk_ipsec_hw_sa {
 	struct rte_pmd_cnxk_ipsec_outb_sa outb;
 };
 
+/** CPT HW result format */
+union rte_pmd_cnxk_cpt_res_s {
+	/** CN10K CPT result */
+	struct rte_pmd_cpt_cn10k_res_s {
+		/** Completion code */
+		uint64_t compcode : 7;
+		/** Done interrupt */
+		uint64_t doneint : 1;
+		/** Microcode completion code */
+		uint64_t uc_compcode : 8;
+		/** Result length */
+		uint64_t rlen : 16;
+		/** SPI */
+		uint64_t spi : 32;
+
+		/** Extended sequence number */
+		uint64_t esn;
+	} cn10k;
+
+	/** CN9K CPT result */
+	struct rte_pmd_cpt_cn9k_res_s {
+		/** Completion code */
+		uint64_t compcode : 8;
+		/** Microcode completion code */
+		uint64_t uc_compcode : 8;
+		/** Done interrupt */
+		uint64_t doneint : 1;
+		uint64_t reserved_17_63 : 47;
+
+		uint64_t reserved_64_127;
+	} cn9k;
+
+	/** CPT RES */
+	uint64_t u64[2];
+};
+
 /**
  * Read HW SA context from session.
  *
@@ -501,9 +537,9 @@ int rte_pmd_cnxk_hw_sa_write(void *device, struct rte_security_session *sess,
  *   Pointer to packet that was just received and was processed with Inline IPsec.
  *
  * @return
- *   - Pointer to mbuf location where CPT result info is stored on success.
+ *   - Pointer to mbuf location where `union rte_pmd_cnxk_cpt_res_s` is stored on success.
  *   - NULL on failure.
  */
 __rte_experimental
-void *rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf);
+union rte_pmd_cnxk_cpt_res_s *rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf);
 #endif /* _PMD_CNXK_H_ */
-- 
2.25.1

Re: [PATCH v2 10/10] net/cnxk: define CPT HW result format for PMD API

[Jerin Jacob]

On Tue, May 28, 2024 at 12:43 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Srujana Challa <schalla@marvell.com>
>
> Defines CPT HW result format for PMD API,
> rte_pmd_cnxk_inl_ipsec_res().
>
> Signed-off-by: Srujana Challa <schalla@marvell.com>

Series applied to dpdk-next-net-mrvl/for-main. Thanks