From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DFE8844051; Fri, 17 May 2024 17:05:32 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 67C944029F; Fri, 17 May 2024 17:05:32 +0200 (CEST) Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) by mails.dpdk.org (Postfix) with ESMTP id 0162E40268 for ; Fri, 17 May 2024 17:05:30 +0200 (CEST) Received: by mail-pg1-f180.google.com with SMTP id 41be03b00d2f7-5ce6b5e3c4eso833384a12.2 for ; Fri, 17 May 2024 08:05:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=networkplumber-org.20230601.gappssmtp.com; s=20230601; t=1715958330; x=1716563130; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:subject:cc:to:from:date:from:to:cc:subject:date :message-id:reply-to; bh=A9h33p5uQbEllOj/hRuDfet0hcxzRQob3sdPMjAoJEE=; b=PUUXSZDm5Mga+pp1kO+p++MKZImHhJhHzeekPdud+BQBuapTjb64J9oNfqX/T/7RFX hhQ+SWW7LPDz5HW8QBNdNmka+qx8iiV0HlVuPkKtCv5JmiNhqCV5jKkO718mQOooMG9t 1dBwXefkCNnMw3UY76UecwtCufdenC3Cx1McJhm8jbKYKoG1s/zDRyzU3n+bDVKPMRNf o+R3LEbLAWglU48vuUb/yRwe8AfBa2O6+9L6Nr8ngXaqeZJ186dGHcUYPO3g04NPV9aC vKHTr9h7QgjWPmOEMjoplG53vzDOfyOMt6bz7knkXfJWBq2a3wQ6VscLg5izW7zPpZo5 FI5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715958330; x=1716563130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:subject:cc:to:from:date:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A9h33p5uQbEllOj/hRuDfet0hcxzRQob3sdPMjAoJEE=; b=QwO+9EEyDDvbn/pOFNqEVFGyPGsVYgC6vL0SNFzffNxMk2WHrdfLg3f2ER+14+AyWe fIcYxCjwmELeUi6xWz/evfuhl+IWfDIVfNdk6QPphv0k22tRsvjeGP8ngm3gme45Xndh 6THGhvxxrmAFVK0KSSaBF49D0N3kkVXzttnAnfiD1LKrubZhkvvccHB3/oBoX44wom+V gPyDWDqRQtYNSGLlPMd/VtZdck0bwbLJb8Tk1D+ku7eANOxNGwZzq4KpTzidw/VJkseX BJxNPzvov8JRbdPKlBiRYjD+6RAo5tYTP+nrnQS5loeh3FBOPU5dKFezkkW2Cs3icOMM 9Bhw== X-Forwarded-Encrypted: i=1; AJvYcCVwovM/cR/sibhEpCDHdqmOe+0fyz4uDZen01u6CAzWKhbhSaGYq7zTf74gP9kDDNQVewvWZKaDiAkLkcs= X-Gm-Message-State: AOJu0Yy1ZLHKVRTt09ei6CRAoZ+k9gNZb7AAfUpMy9jkgLkicucPXCwE j+eknbn8ETZ3sX4NMa6OIMvSyxKdpZkJjHBTr2Zoq4HeSnvHKfFZq8ftB5I2PSU= X-Google-Smtp-Source: AGHT+IEajy48mWdLEyCxXaBJoMs49qL/qZFmcYxGacNkMBrmoFmoaIBahEEH7wCP4auyLDWIq0fH5g== X-Received: by 2002:a05:6a00:22c9:b0:6ea:ca90:3459 with SMTP id d2e1a72fcca58-6f4e0384f8bmr26393574b3a.32.1715958329882; Fri, 17 May 2024 08:05:29 -0700 (PDT) Received: from hermes.local (204-195-96-226.wavecable.com. [204.195.96.226]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f679df3085sm4361874b3a.193.2024.05.17.08.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 08:05:29 -0700 (PDT) Date: Fri, 17 May 2024 08:05:27 -0700 From: Stephen Hemminger To: Morten =?UTF-8?B?QnLDuHJ1cA==?= Cc: "Honnappa Nagarahalli" , , "nd" , "Richardson, Bruce" Subject: Re: [PATCH v6 1/9] eal: generic 64 bit counter Message-ID: <20240517080527.0d660d98@hermes.local> In-Reply-To: <98CBD80474FA8B44BF855DF32C47DC35E9F476@smartserver.smartshare.dk> References: <20240510050507.14381-1-stephen@networkplumber.org> <20240517001302.65514-1-stephen@networkplumber.org> <20240517001302.65514-2-stephen@networkplumber.org> <48ED00A3-1CCA-4F64-ACC3-CA1F0D2B9378@arm.com> <20240516203037.73ec13e1@hermes.local> <248621D2-C402-4DDE-92D8-F5377E816533@arm.com> <98CBD80474FA8B44BF855DF32C47DC35E9F476@smartserver.smartshare.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Fri, 17 May 2024 08:44:42 +0200 Morten Br=C3=B8rup wrote: > I guess it depends on the architecture's natural alignment size and the c= ompiler - especially on 32 bit architectures, where the natural alignment s= ize is 4 bytes. >=20 > We could play it safe and add alignment to the counter type: >=20 > #include > #ifdef RTE_ARCH_64 > #if alignof(uint64_t) < sizeof(uint64_t) I don't think this case is possible, what architecture is that broken? > typedef alignas(8) uint64_t rte_counter64_t; > #else > typedef uint64_t rte_counter64_t; > #endif > #else > #if alignof(RTE_ATOMIC(uint64_t)) < sizeof(uint64_t) > typedef alignas(8) RTE_ATOMIC(uint64_t) rte_counter64_t; > #else > typedef RTE_ATOMIC(uint64_t) rte_counter64_t; > #endif > #endif The bigger question is how to detect 32 bit x86 being safe without atomic? (and does it still matter).