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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6ab8sm17547565a91.55.2024.05.17.09.18.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 09:18:04 -0700 (PDT) Date: Fri, 17 May 2024 09:18:01 -0700 From: Stephen Hemminger To: Morten =?UTF-8?B?QnLDuHJ1cA==?= Cc: "Honnappa Nagarahalli" , , "nd" , "Richardson, Bruce" Subject: Re: [PATCH v6 1/9] eal: generic 64 bit counter Message-ID: <20240517091801.17fdef27@hermes.local> In-Reply-To: <98CBD80474FA8B44BF855DF32C47DC35E9F476@smartserver.smartshare.dk> References: <20240510050507.14381-1-stephen@networkplumber.org> <20240517001302.65514-1-stephen@networkplumber.org> <20240517001302.65514-2-stephen@networkplumber.org> <48ED00A3-1CCA-4F64-ACC3-CA1F0D2B9378@arm.com> <20240516203037.73ec13e1@hermes.local> <248621D2-C402-4DDE-92D8-F5377E816533@arm.com> <98CBD80474FA8B44BF855DF32C47DC35E9F476@smartserver.smartshare.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Fri, 17 May 2024 08:44:42 +0200 Morten Br=C3=B8rup wrote: > > From: Honnappa Nagarahalli [mailto:Honnappa.Nagarahalli@arm.com] > > Sent: Friday, 17 May 2024 06.27 > >=20 > > + Bruce for feedback on x86 architecture > > =20 > > > On May 16, 2024, at 10:30=E2=80=AFPM, Stephen Hemminger =20 > > wrote: =20 > > > > > > On Fri, 17 May 2024 02:45:12 +0000 > > > Honnappa Nagarahalli wrote: > > > =20 > > >>> + * A counter is 64 bit value that is safe from split read/write > > >>> + * on 32 bit platforms. It assumes that only one cpu at a time =20 > > >> If we are defining the counter in this manner, then implementation c= annot =20 > > be generic. I think architectures will have constraints if they have to= ensure > > the 64b variables are not split. =20 > > >> > > >> I think we at least need the counter to be aligned on 8B boundary to= have =20 > > generic code. =20 > > > > > > The C standard has always guaranteed that read and write to unsigned = log =20 > > will not be split. > > As I understand, this is true only if the variable is an atomic variabl= e. If > > not, there is no difference between atomic variables and non-atomic var= iables. > > =20 > > > Therefore if arch is 64 bit native there is no need for atomics =20 > > At least on ARM architecture, if the variable is not aligned on 8B boun= dary, > > the load or store are not atomic. I am sure it is the same on other > > architectures. =20 After reading this: Who's afraid of a big bad optimizing compiler? https://lwn.net/Articles/793253/ Looks like you are right, and atomic or read/write once is required. Perhaps introducing rte_read_once and rte_write_once is good idea? Several drivers are implementing it already.