From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1AE2C44076; Mon, 20 May 2024 11:49:01 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8083440263; Mon, 20 May 2024 11:49:00 +0200 (CEST) Received: from mail-yb1-f169.google.com (mail-yb1-f169.google.com [209.85.219.169]) by mails.dpdk.org (Postfix) with ESMTP id 6A0F6400EF for ; Mon, 20 May 2024 11:48:58 +0200 (CEST) Received: by mail-yb1-f169.google.com with SMTP id 3f1490d57ef6-dc236729a2bso2103746276.0 for ; Mon, 20 May 2024 02:48:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1716198537; x=1716803337; darn=dpdk.org; h=user-agent:in-reply-to:content-transfer-encoding :content-disposition:mime-version:references:mail-followup-to :message-id:subject:cc:to:from:date:from:to:cc:subject:date :message-id:reply-to; bh=VS08USvwWe5a66PyQzAcYFPxazRVNhNimJntmgjaAxA=; b=Mdk6dUJkUDX33PgghTKJxijsuhMTDtdlueusgZPDB+Jy82SkpLE1Mh+MvzHvnc8g0c XjMBktpIPfBUWlVR3TsfmpUGxon7La8OWdhcQoyZtCI4zhB7u8BV0V3EznoVjo8RJoNm CiLpkGPloUhroMvTIwHlItsSTnFNkCAMWcCbnVudG2eYqed6iQN+9wLmDDXoHOszfH9d TzK9bHE5QEc0D/UnJV0R8gJ5q+7Edot/Uilkz05E8xH8eSFZGe8xqtIv1eKp+8WN3d1u L/7XMsKe9R+2d/XPcRi0ryMX0Re6erNF4J93FAmOzDrvpXT8QhX2sSssR8RgSXcH3Cdr y1wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716198537; x=1716803337; h=user-agent:in-reply-to:content-transfer-encoding :content-disposition:mime-version:references:mail-followup-to :message-id:subject:cc:to:from:date:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VS08USvwWe5a66PyQzAcYFPxazRVNhNimJntmgjaAxA=; b=fsE42RU5KbYryg4Qsayx/v7daaoAHBayHqHtqMm7/JakZlnpIFlInaiix6F2qbKtiT B1XESDKdhqER7sjCMHKa54UkXv6UifMaB/cIFYqvjhQ56YWVbGAc5b5jr8YLnRa6cetR zIGFHLkk4w7mzpViT88o1QHBbNYiYeXg3hBnYitM0F6UYfFigpko99/LnKXTCPcbpg79 oqw9CovvK8/TR4AopKtiih/cBN80hjSkfymKdJM/Zt1mcbjSaa47cuY4StbpgSAHJcxR 4elxiZcVcrzvZDx7IHrCxjNHotuvlYEJTZUN72HaRqTRbIIFT19rRq+uN11TfDGsfyq9 xZww== X-Forwarded-Encrypted: i=1; AJvYcCXMOzSDLVvJFd/jWS2b3lz4vTYNRA+vNFeZY4s+kJSF2c5bfwTiRV0+bHRousT/A2DHP5OFvqFkck8M3ss= X-Gm-Message-State: AOJu0Yxk1JlNGIcd8CrCuul3sDR1/h7jyO1Ov3d5lXz0JYQt4KQVY4DP TESHNh+vib/b8TbmmFKOMss3a/fxWQoOe2SJzcl+BoIjBt5LbvJHZPbsjbEv694= X-Google-Smtp-Source: AGHT+IFiGEDj29aCaPD+Ifh1zzYhOI2JJURzan7SIAA4o9g3wIM9zL4yUo2drQZI6m1eqD31Ym38Pw== X-Received: by 2002:a05:6902:541:b0:de6:dcd:20a7 with SMTP id 3f1490d57ef6-dee4f1c5e89mr28084165276.13.1716198537625; Mon, 20 May 2024 02:48:57 -0700 (PDT) Received: from ste-uk-lab-gw ([93.115.195.2]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6a15f1cd35bsm111558476d6.87.2024.05.20.02.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 May 2024 02:48:57 -0700 (PDT) Date: Mon, 20 May 2024 10:48:54 +0100 From: Daniel Gregory To: =?utf-8?Q?Stanis=C5=82aw?= Kardach Cc: Bruce Richardson , dev@dpdk.org, Liang Ma , Punit Agrawal Subject: Re: [RFC PATCH] eal/riscv: add support for zawrs extension Message-ID: <20240520094854.GA3672529@ste-uk-lab-gw> Mail-Followup-To: =?utf-8?Q?Stanis=C5=82aw?= Kardach , Bruce Richardson , dev@dpdk.org, Liang Ma , Punit Agrawal References: <20240502144149.66446-1-daniel.gregory@bytedance.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Sun, May 12, 2024 at 09:10:49AM +0200, Stanisław Kardach wrote: > On Thu, May 2, 2024 at 4:44 PM Daniel Gregory > wrote: > > diff --git a/config/riscv/meson.build b/config/riscv/meson.build > > index 07d7d9da23..4cfdc42ecb 100644 > > --- a/config/riscv/meson.build > > +++ b/config/riscv/meson.build > > @@ -26,6 +26,11 @@ flags_common = [ > > # read from /proc/device-tree/cpus/timebase-frequency. This property is > > # guaranteed on Linux, as riscv time_init() requires it. > > ['RTE_RISCV_TIME_FREQ', 0], > > + > > + # Enable use of RISC-V Wait-on-Reservation-Set extension (Zawrs) > > + # Mitigates looping when polling on memory locations > > + # Make sure to add '_zawrs' to your target's -march below > > + ['RTE_RISCV_ZAWRS', false] > A bit orthogonal to this patch (or maybe not?) > Should we perhaps add a Qemu target in meson.build which would have > the modified -march for what qemu supports now? Yes, I can see that being worth doing as part of this patch. In addition to Zawrs for this patch, GCC 13+ should generate prefetch instructions for __builtin_prefetch() (lib/eal/include/generic/rte_prefetch.h) if the Zicbop extension is enabled. Any more in particular you think would benefit or would it be best to add every extension GCC 14 supports? > Or perhaps add machine detection logic based either on the "riscv,isa" > cpu@0 property in the DT or RHCT ACPI table? I have had a look and, at least on QEMU 9, this seems non-trivial. The RHCT acpi table at /proc/cpuinfo doesn't list every extension present (eg. it's missing Zawrs), and the DT, whilst complete, can't be fed directly into GCC because QEMU reports several newer and non-ratified extensions that GCC doesn't support yet. > Or add perhaps some other way we could specify the extension list > suffix for -march? Setting -Dcpu_instruction_set to some arbitrary ISA could work with somes minor changes to the build script to not discard it in favour of rv64gc. Then, we could add a map from ISA extensions to flags that are enabled when that extension is present in cpu_instruction_set? Thanks for your review, Daniel