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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f30fb5303csm16119075ad.166.2024.05.21.13.18.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 May 2024 13:18:03 -0700 (PDT) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , =?UTF-8?q?Morten=20Br=C3=B8rup?= , Tyler Retzlaff Subject: [PATCH v9 1/8] eal: generic 64 bit counter Date: Tue, 21 May 2024 13:16:34 -0700 Message-ID: <20240521201801.126886-2-stephen@networkplumber.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240521201801.126886-1-stephen@networkplumber.org> References: <20240510050507.14381-1-stephen@networkplumber.org> <20240521201801.126886-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This header implements 64 bit counters using atomic operations but with a weak memory ordering so that they are safe against load/store splits on 32 bit platforms. Signed-off-by: Stephen Hemminger Acked-by: Morten Brørup --- lib/eal/include/meson.build | 1 + lib/eal/include/rte_counter.h | 150 ++++++++++++++++++++++++++++++++++ 2 files changed, 151 insertions(+) create mode 100644 lib/eal/include/rte_counter.h diff --git a/lib/eal/include/meson.build b/lib/eal/include/meson.build index e94b056d46..c070dd0079 100644 --- a/lib/eal/include/meson.build +++ b/lib/eal/include/meson.build @@ -12,6 +12,7 @@ headers += files( 'rte_class.h', 'rte_common.h', 'rte_compat.h', + 'rte_counter.h', 'rte_debug.h', 'rte_dev.h', 'rte_devargs.h', diff --git a/lib/eal/include/rte_counter.h b/lib/eal/include/rte_counter.h new file mode 100644 index 0000000000..f0c2b71a6c --- /dev/null +++ b/lib/eal/include/rte_counter.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) Stephen Hemminger + */ + +#ifndef _RTE_COUNTER_H_ +#define _RTE_COUNTER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +/** + * @file + * RTE Counter + * + * A counter is 64 bit value that is safe from split read/write. + * It assumes that only one cpu at a time will update the counter, + * and another CPU may want to read it. + * + * This is a weaker subset of full atomic variables. + * + * The counters are subject to the restrictions of atomic variables + * in packed structures or unaligned. + */ + +#ifdef RTE_ARCH_64 + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * On native 64 bit platform, counter is implemented as basic + * 64 bit unsigned integer that only increases. + */ +typedef struct { + uint64_t current; + uint64_t offset; +} rte_counter64_t; + +/** + * @internal + * Macro to implement read once (compiler barrier) using stdatomic. + * This is compiler barrier only. + */ +#define __rte_read_once(var) \ + rte_atomic_load_explicit((__rte_atomic typeof(&(var)))&(var), \ + rte_memory_order_consume) + +/** + * @internal + * Macro to implement write once (compiler barrier) using stdatomic. + * This is compiler barrier only. + */ +#define __rte_write_once(var, val) \ + rte_atomic_store_explicit((__rte_atomic typeof(&(var)))&(var), val, \ + rte_memory_order_release) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Add value to counter. + * Assumes this operation is only done by one thread on the object. + * + * @param counter + * A pointer to the counter. + * @param val + * The value to add to the counter. + */ +static inline void +rte_counter64_add(rte_counter64_t *counter, uint32_t val) +{ + counter->current += val; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Read a counter. + * This operation can be done by any thread. + * + * @param counter + * A pointer to the counter. + * @return + * The current value of the counter. + */ +__rte_experimental +static inline uint64_t +rte_counter64_read(const rte_counter64_t *counter) +{ + return __rte_read_once(counter->current) - __rte_read_once(counter->offset); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Reset a counter to zero. + * This operation can be done by any thread. + * + * @param counter + * A pointer to the counter. + */ +__rte_experimental +static inline void +rte_counter64_reset(rte_counter64_t *counter) +{ + __rte_write_once(counter->offset, __rte_read_once(counter->current)); +} + +#else + +/* On 32 bit platform, need to use atomic to avoid load/store tearing */ +typedef RTE_ATOMIC(uint64_t) rte_counter64_t; + +__rte_experimental +static inline void +rte_counter64_add(rte_counter64_t *counter, uint32_t val) +{ + rte_atomic_fetch_add_explicit(counter, val, rte_memory_order_relaxed); +} + +__rte_experimental +static inline uint64_t +rte_counter64_read(const rte_counter64_t *counter) +{ + return rte_atomic_load_explicit(counter, rte_memory_order_consume); +} + +__rte_experimental +static inline void +rte_counter64_reset(rte_counter64_t *counter) +{ + rte_atomic_store_explicit(counter, 0, rte_memory_order_release); +} + +#endif /* RTE_ARCH_64 */ + + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_COUNTER_H_ */ -- 2.43.0