[PATCH 2/2] net/mlx5/hws: add match with switch manager

[Suanming Mou <suanmingm@nvidia.com>]

This commit adds HWS layer match with switch manager code.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c |  3 ++-
 drivers/net/mlx5/hws/mlx5dr_definer.h |  5 ++++-
 drivers/net/mlx5/hws/mlx5dr_rule.c    |  2 +-
 drivers/net/mlx5/mlx5_flow.h          | 30 +++++++++++++++++++++++++--
 4 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index bc128c7b99..4be9012e25 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -721,7 +721,7 @@ mlx5dr_definer_vport_set(struct mlx5dr_definer_fc *fc,
 	const struct flow_hw_port_info *port_info;
 	uint32_t regc_value;
 
-	port_info = flow_hw_conv_port_id(v->port_id);
+	port_info = flow_hw_conv_port_id(fc->dr_ctx, v->port_id);
 	if (unlikely(!port_info))
 		regc_value = BAD_PORT;
 	else
@@ -1548,6 +1548,7 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd,
 		DR_CALC_SET_HDR(fc, registers, register_c_0);
 		fc->bit_off = __builtin_ctz(caps->wire_regc_mask);
 		fc->bit_mask = caps->wire_regc_mask >> fc->bit_off;
+		fc->dr_ctx = cd->ctx;
 	} else {
 		DR_LOG(ERR, "Pord ID item mask must specify ID mask");
 		rte_errno = EINVAL;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 463e22732e..b583f78943 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -223,9 +223,12 @@ enum mlx5dr_definer_type {
 struct mlx5dr_definer_fc {
 	uint8_t item_idx;
 	uint8_t is_range;
-	uint16_t extra_data;
 	uint8_t compare_idx;
 	bool compare_set_base;
+	union {
+		uint32_t extra_data;
+		void *dr_ctx;
+	};
 	uint32_t byte_off;
 	int bit_off;
 	uint32_t bit_mask;
diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c
index 171a0bff38..ea30c37270 100644
--- a/drivers/net/mlx5/hws/mlx5dr_rule.c
+++ b/drivers/net/mlx5/hws/mlx5dr_rule.c
@@ -28,7 +28,7 @@ static void mlx5dr_rule_skip(struct mlx5dr_matcher *matcher,
 
 	if (mt->item_flags & MLX5_FLOW_ITEM_REPRESENTED_PORT) {
 		v = items[mt->vport_item_id].spec;
-		vport = flow_hw_conv_port_id(v->port_id);
+		vport = flow_hw_conv_port_id(matcher->tbl->ctx, v->port_id);
 		if (unlikely(!vport)) {
 			DR_LOG(ERR, "Fail to map port ID %d, ignoring", v->port_id);
 			return;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 0a6d33f8ee..9619985450 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -2003,15 +2003,41 @@ flow_hw_get_port_id(void *dr_ctx)
 	return UINT16_MAX;
 }
 
+/*
+ * Get given eswitch manager id.
+ * Used in HWS match with port creation.
+ */
+static __rte_always_inline const struct flow_hw_port_info *
+flow_hw_get_esw_mgr_id(void *dr_ctx)
+{
+#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
+	uint16_t port_id;
+
+	MLX5_ETH_FOREACH_DEV(port_id, NULL) {
+		struct mlx5_priv *priv;
+
+		priv = rte_eth_devices[port_id].data->dev_private;
+		if (priv->dr_ctx == dr_ctx)
+			return &priv->sh->dev_cap.esw_info;
+	}
+#else
+	RTE_SET_USED(dr_ctx);
+#endif
+	return NULL;
+}
+
 /*
  * Get metadata match tag and mask for given rte_eth_dev port.
  * Used in HWS rule creation.
  */
 static __rte_always_inline const struct flow_hw_port_info *
-flow_hw_conv_port_id(const uint16_t port_id)
+flow_hw_conv_port_id(void *ctx, const uint16_t port_id)
 {
 	struct flow_hw_port_info *port_info;
 
+	if (port_id == UINT16_MAX && ctx)
+		return flow_hw_get_esw_mgr_id(ctx);
+
 	if (port_id >= RTE_MAX_ETHPORTS)
 		return NULL;
 	port_info = &mlx5_flow_hw_port_infos[port_id];
@@ -2037,7 +2063,7 @@ flow_hw_get_wire_port(struct ibv_context *ibctx)
 			struct ibv_context *port_ibctx = priv->sh->cdev->ctx;
 
 			if (port_ibctx->device == ibdev)
-				return flow_hw_conv_port_id(port_id);
+				return flow_hw_conv_port_id(priv->dr_ctx, port_id);
 		}
 	}
 	return NULL;
-- 
2.34.1