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Mon, 3 Jun 2024 03:52:54 -0700 From: Maayan Kashani To: CC: , , , Gregory Etelson , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad Subject: [PATCH v3 3/6] net/mlx5: support indirect actions in non-template setup Date: Mon, 3 Jun 2024 13:52:38 +0300 Message-ID: <20240603105241.10482-3-mkashani@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20240603105241.10482-1-mkashani@nvidia.com> References: <20240602102841.196990-1-mkashani@nvidia.com> <20240603105241.10482-1-mkashani@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529D:EE_|PH7PR12MB6905:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ebbad44-e9dd-472b-fd38-08dc83bb548a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|36860700004|82310400017|376005|1800799015; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4VqfAkxumuvY7M1i+vsEFH6CYrq+Mv3VkJDTjFq4gffkeM/wLHs3CvvLMUnL?= =?us-ascii?Q?UdzbcJi30mh+cCAxI24aH6XHTOCRh1QEo2mh6gDTl4A5pskNFcBS7ENr7+aV?= =?us-ascii?Q?xW4WfIH4ZVPA1cGy0oBbP7XbfYmeCInwTSi6dVNd0Ud/g1WJqunGUc8aWmGb?= =?us-ascii?Q?o4LqG5bQLMq57d/fFXt7ElCRuqNduQM+aq/t8obgFPVSFoSK6lV0+C1Udg+B?= =?us-ascii?Q?l4rnXi2UFyW0B3wKca/yfUC60XQwBf8to+ZelRoadgPSFSZZJwIomk1EnBg6?= =?us-ascii?Q?pxvKyDfp2PCYMQTLh1Ll2UoPi3UiwEAOZLghEcvxaUFyu96TgStQWD4w9onZ?= =?us-ascii?Q?TyLCqpJQMkEm0UjM+SvArtxYoN9fLXBYVvbO6LoN2RwPyGC+/fEF7Xk3RssL?= =?us-ascii?Q?//CJHf6CamsjsFeWi/Jf/posNT3XHEmIugSMgCLxwQMJcZVA9defKfli1MNI?= =?us-ascii?Q?5shRAaTe3yLv0r1xyKuPqmfvEqz3Bh6sJNneDKJY8Ys8N8VK7x2Z8iSAcg6B?= =?us-ascii?Q?zaDeQCcqb+KwgBOFnLAShjbertvedS7aOgugn9DH3iEqQBW6Zsp9eBzLdNNO?= =?us-ascii?Q?+eKjMg6oBnoGG5xR2yBH4f7iseHm43ie+dryrCdhf4XnFyP6Oz8tBMEQzHuc?= =?us-ascii?Q?NZDteDjwgPukMbBDhY4OYLvFPAeundB4RtCx9g28KtRG+O/XJPPO2ZTYpJU9?= =?us-ascii?Q?5k35e7MQNDj/C8dFUhpzKqQC0o2YH6fXTrAQAWJNzN2vIJk8aiBrhV5sKdBq?= =?us-ascii?Q?butNnLh4AQJiK95cxJw7/w+UBOCKViApJukvYa2DjDgqN/qf3fuMYpCMeXWl?= =?us-ascii?Q?4nz0vYNoVPxRBwLDP6VdSMDAd98NMcDwg1KoQvA2/wNKmLycBrnyxegzRHP7?= =?us-ascii?Q?hordk97+/GshSnh84x30RLw/vfl6bY7YXNyeazDle0g6itJNb37/XfgM/hF3?= =?us-ascii?Q?yNBx7CsUaVUMLTJkwhjinHY14VEImcoMDVx8rj5Iyq80A5U/zuB44d36hkpK?= =?us-ascii?Q?5aiq2axch10Rj5zHWZ23OgobT6pT2OH++NPeE00ZcBZxnRxHBawPC1FE3KbD?= =?us-ascii?Q?cHRkkRLkKZzrRhWOK6G2D9urTpVg3zHpOqivLa8i+jX6sgk0YGEw1oIa7WKl?= =?us-ascii?Q?JHCiCxs2umV3QCbGZ94w4mhCaO1+waov3QWGZs85UIIGfgbzixRCDlRtS6ix?= =?us-ascii?Q?aP6i2X1YFDvko+OhwPbrf5O7YpaQVxvlHqFbQxrd8f2S9Gv/rknImY+13tRj?= =?us-ascii?Q?Mk4nQlipK9UwqnaRDBhazn+BjK56aouTeNYPUI/Xv2a0uSrBbb5kC45Q+WBv?= =?us-ascii?Q?2ZO1VSeFjkA5mxgnWz2io8MMcealnptGUbaWVTgcKhxppPqa2BkFFWFm6330?= =?us-ascii?Q?P4Ps71rQrhvHVatOelije5G1JUAd?= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004)(82310400017)(376005)(1800799015); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2024 10:52:57.9035 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ebbad44-e9dd-472b-fd38-08dc83bb548a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6905 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Gregory Etelson Add support for the RSS, AGE, COUNT and CONNTRACK indirect flow actions for the non-template flow rules. Signed-off-by: Gregory Etelson --- drivers/net/mlx5/mlx5_flow_hw.c | 111 +++++++++++++++++++++++++------- 1 file changed, 89 insertions(+), 22 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 7984bf2f73..9f43fbfb35 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -12431,6 +12431,91 @@ flow_hw_encap_decap_resource_register return 0; } +static enum rte_flow_action_type +flow_nta_get_indirect_action_type(const struct rte_flow_action *action) +{ + switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) { + case MLX5_INDIRECT_ACTION_TYPE_RSS: + return RTE_FLOW_ACTION_TYPE_RSS; + case MLX5_INDIRECT_ACTION_TYPE_AGE: + return RTE_FLOW_ACTION_TYPE_AGE; + case MLX5_INDIRECT_ACTION_TYPE_COUNT: + return RTE_FLOW_ACTION_TYPE_COUNT; + case MLX5_INDIRECT_ACTION_TYPE_CT: + return RTE_FLOW_ACTION_TYPE_CONNTRACK; + default: + break; + } + return RTE_FLOW_ACTION_TYPE_END; +} + +static void +flow_nta_set_mh_mask_conf(const struct rte_flow_action_modify_field *action_conf, + struct rte_flow_action_modify_field *mask_conf) +{ + memset(mask_conf, 0xff, sizeof(*mask_conf)); + mask_conf->operation = action_conf->operation; + mask_conf->dst.field = action_conf->dst.field; + mask_conf->src.field = action_conf->src.field; +} + +union actions_conf { + struct rte_flow_action_modify_field modify_field; + struct rte_flow_action_raw_encap raw_encap; + struct rte_flow_action_vxlan_encap vxlan_encap; + struct rte_flow_action_nvgre_encap nvgre_encap; +}; + +static int +flow_nta_build_template_mask(const struct rte_flow_action actions[], + struct rte_flow_action masks[MLX5_HW_MAX_ACTS], + union actions_conf mask_conf[MLX5_HW_MAX_ACTS]) +{ + int i; + + for (i = 0; i == 0 || actions[i - 1].type != RTE_FLOW_ACTION_TYPE_END; i++) { + const struct rte_flow_action *action = &actions[i]; + struct rte_flow_action *mask = &masks[i]; + union actions_conf *conf = &mask_conf[i]; + + mask->type = action->type; + switch (action->type) { + case RTE_FLOW_ACTION_TYPE_INDIRECT: + mask->type = flow_nta_get_indirect_action_type(action); + if (!mask->type) + return -EINVAL; + break; + case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: + flow_nta_set_mh_mask_conf(action->conf, (void *)conf); + mask->conf = conf; + break; + case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: + /* This mask will set this action as shared. */ + memset(conf, 0xff, sizeof(struct rte_flow_action_raw_encap)); + mask->conf = conf; + break; + case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: + /* This mask will set this action as shared. */ + conf->vxlan_encap.definition = + ((const struct rte_flow_action_vxlan_encap *) + action->conf)->definition; + mask->conf = conf; + break; + case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: + /* This mask will set this action as shared. */ + conf->nvgre_encap.definition = + ((const struct rte_flow_action_nvgre_encap *) + action->conf)->definition; + mask->conf = conf; + break; + default: + break; + } + } + return 0; +#undef NTA_CHECK_CONF_BUF_SIZE +} + static int flow_hw_translate_flow_actions(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, @@ -12454,30 +12539,12 @@ flow_hw_translate_flow_actions(struct rte_eth_dev *dev, .transfer = attr->transfer, }; struct rte_flow_action masks[MLX5_HW_MAX_ACTS]; - struct rte_flow_action_raw_encap encap_conf; - struct rte_flow_action_modify_field mh_conf[MLX5_HW_MAX_ACTS]; + union actions_conf mask_conf[MLX5_HW_MAX_ACTS]; - memset(&masks, 0, sizeof(masks)); - int i = -1; - do { - i++; - masks[i].type = actions[i].type; - if (masks[i].type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) { - memset(&encap_conf, 0x00, sizeof(encap_conf)); - encap_conf.size = ((const struct rte_flow_action_raw_encap *) - (actions[i].conf))->size; - masks[i].conf = &encap_conf; - } - if (masks[i].type == RTE_FLOW_ACTION_TYPE_MODIFY_FIELD) { - const struct rte_flow_action_modify_field *conf = actions[i].conf; - memset(&mh_conf, 0xff, sizeof(mh_conf[i])); - mh_conf[i].operation = conf->operation; - mh_conf[i].dst.field = conf->dst.field; - mh_conf[i].src.field = conf->src.field; - masks[i].conf = &mh_conf[i]; - } - } while (masks[i].type != RTE_FLOW_ACTION_TYPE_END); RTE_SET_USED(action_flags); + memset(masks, 0, sizeof(masks)); + memset(mask_conf, 0, sizeof(mask_conf)); + flow_nta_build_template_mask(actions, masks, mask_conf); /* The group in the attribute translation was done in advance. */ ret = __translate_group(dev, attr, external, attr->group, &src_group, error); if (ret) -- 2.25.1