From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 77F6E44145; Mon, 3 Jun 2024 12:53:21 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F308142E63; Mon, 3 Jun 2024 12:53:10 +0200 (CEST) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2067.outbound.protection.outlook.com [40.107.93.67]) by mails.dpdk.org (Postfix) with ESMTP id DB9E042E63 for ; Mon, 3 Jun 2024 12:53:08 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OT6NOfqvsWjHunGcZZze3nKObAs587wE2rb+beFkBioFyq4S2bQw9G0BxBB1Fik1hEqbQmVRkL+RWsdad/9shVb1ITkhlNCnCHBOtTwWZcheZQ9fx1aoGjnd6Rc97XIzYtnF1SuogQxuX61DYtOFnDViEDVZrXy9GIaAQL9YSO77trV6ZhY14r6OlvztOSuC90AzZcMBFC283yw5Pcu0XQvqgLm20/vZ42UD8rLzRzhLRL3rw4hkFjf6sf70TVuk2wUQY76slLTUj61d3AROj5atZ9zX8VViXYqcc9IjAi73R102Ub8SaC3+kX0iobv742Nlrf+i0ask29vvnpy7mQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=LL9OzaxmdWYlUPkq12YOGw+iCSIJh8qugEx6lCoekEU=; b=H5wT9jFtyu1thr01cigR7jbq9MxN7GpZpCOJ1ygbaWokfSrAxAeILx25UDHmYcOTD5RSd8Ba6K/jxFAxvvK0FI8posRNVKkyPMH7AEOlDIL/Je7rq/wrXdivrXxKIL/EGFOK+xNf2CIw2qh8VSzf8X38+5jTTSrNLAW7pnUqVNn3BMRTV+yq2Pbeo0zoY0Sw8V+Csu6CpkWqyt4FKX2UcGPK2f7mvUA5HhhDauGWtJRi23RlSZXqQUWwglphyZ9fxzrzJ6S5JQSkxL1udNTQ9mn+/osliTvPbwwWEt7An+siA4qAZiCq/whHLb04GYJONAp8wRoRIjkL8eySaUZQZg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LL9OzaxmdWYlUPkq12YOGw+iCSIJh8qugEx6lCoekEU=; b=OTfJTewUnHvn3iAxJax0rEmGpjN4uUi5mI+3U80DFJgAJJv/sxwylohBaLgD6jp4IFta6+1of8JAqIfRivIcaYE8/at2xzdJwEyVDDFsiN9EJ4rfSnvcV3rf6B4jy8/zFojRicM+1X/svMKD7yihw3ZKIsgqpCeFD90XKK0/O2bU5Jtq2iqYP9JYNg3hNJrhNfrE1jyLLKVQfy0M6dI737A4ioMr1n8c4t5hLl5lzlmcIr9Q4GxnbtBNQzB+H8B6LGrFo+iiitz9V/txOkTVmCwLkKq1m1QD7bxd0iPqFQo4vfuFIOx06v1IdtckwY5SGpC4aihO1sR8QSV4N56aMg== Received: from PH8PR20CA0001.namprd20.prod.outlook.com (2603:10b6:510:23c::15) by SA0PR12MB7461.namprd12.prod.outlook.com (2603:10b6:806:24b::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.22; Mon, 3 Jun 2024 10:53:05 +0000 Received: from SN1PEPF0002529E.namprd05.prod.outlook.com (2603:10b6:510:23c:cafe::29) by PH8PR20CA0001.outlook.office365.com (2603:10b6:510:23c::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.30 via Frontend Transport; Mon, 3 Jun 2024 10:53:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SN1PEPF0002529E.mail.protection.outlook.com (10.167.242.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.15 via Frontend Transport; Mon, 3 Jun 2024 10:53:04 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 3 Jun 2024 03:53:01 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 3 Jun 2024 03:53:00 -0700 Received: from nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4 via Frontend Transport; Mon, 3 Jun 2024 03:52:58 -0700 From: Maayan Kashani To: CC: , , , Gregory Etelson , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad Subject: [PATCH v3 4/6] net/mlx5: update ASO resources in non-template setup Date: Mon, 3 Jun 2024 13:52:39 +0300 Message-ID: <20240603105241.10482-4-mkashani@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20240603105241.10482-1-mkashani@nvidia.com> References: <20240602102841.196990-1-mkashani@nvidia.com> <20240603105241.10482-1-mkashani@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529E:EE_|SA0PR12MB7461:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c5b4273-d5db-4245-df68-08dc83bb588e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|82310400017|36860700004|376005; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?z3gaZsWy26n7gJ3t/+ZHSN8/iDeFeEfwRei/S0p/GezOnQbkdKdqyExMCU/r?= =?us-ascii?Q?1Vs6q+2jpbHd9pjpf1y41BKfKbbyr2Ie5XBA27IXudwp7IIrdtoLOeoNKPYE?= =?us-ascii?Q?gExNyR9odxaptUY3JHn3wmVx5phHE6b/4dUDlrZIYdgTB/ei9NnTzQM1zTU3?= =?us-ascii?Q?rr6xqvZfAXjvZgaOhYKjXk1yUvce0pBPIAQsIFctFWRF0eM+Exepl1ohqiy1?= =?us-ascii?Q?84I1+wc1weqOrUoWi+Y9J8razQ5Q7GpkU/al0ErXfW1EX43sgfhSREfCicmD?= =?us-ascii?Q?4s9TdPyXuP7kXtNanr3zPag92dxLlyPZP/tbPdy9SjsTdzLHXvxm+lk3Bdoo?= =?us-ascii?Q?75QxPMO0XfcmaR4otDBSkNle71QnUex/hacXZGdidwWDeh5Wrj5n9+aTmbWd?= =?us-ascii?Q?LiRV7Js3p0TFFC+gWYKXyenez2do2EDsdLIuJtpQ3RUPY8Fn8Qv4q+NBRBO5?= =?us-ascii?Q?bsOu1N0zXBdhZRLoBGs3z09Ov5XZipRU6vu41Oyz9RmUSpk7q3LUMZonb7+b?= =?us-ascii?Q?CJWnkPdtL719WIfQn4M6sWJFMrTjvYk1VCErA0Bmxgoqi0dcaD7s7ADxy/by?= =?us-ascii?Q?/tqfGRl/t+qJ8fpGRU2SzheP//UODSidt3GLJai7PF0Oz4wQifwF4151CZjp?= =?us-ascii?Q?KnC+EC49kfYtP5VtzKXJ8kTR39ha4Kecj1w7iTlKCJyeAjTaoLQ1jYvTPp7P?= =?us-ascii?Q?Cuoyct4mCyWgGWFVCQxByqwFfA0vAvbjvvwBfH9G/qMeBl3jMRdJMiKk2rcZ?= =?us-ascii?Q?Z6YgBJiqEt+E0cghdCmZURgqhs00anKNiJucN0dScCX/B1JdkxCKwr/oMxQy?= =?us-ascii?Q?gfTHOXslnn4gbMNAHETeqqMJZywTT+BcnKnNKj96N20rupFpmJiQRDCkFH3X?= =?us-ascii?Q?bcQh7NM+CBGrqt36vlLn8OkWqFwwfi683cJKusp/6WMkv58bnO4xUDtgTogL?= =?us-ascii?Q?fNm9k7jiq6nV09+p7ME2GBfarNYj02pHkHwDbwAproVJJY5r4P+i6DM163Xu?= =?us-ascii?Q?94RO685TOq4n9aNHT2O+mmjaZNUXWNNwzczfr89XKb2lqB6FAimQnemnwkSj?= =?us-ascii?Q?xzAZXblbHJLbaU03dhjsptn9orrZK/aDJQkIfWSyZ4b5Q1tr+0i3Fy5MEqHn?= =?us-ascii?Q?i/k1BWtjF4CnbXGExMhteFc0DGL6aJhoXaNSmjwfsdX3bfLnWafgnpgESlDY?= =?us-ascii?Q?GhR0fAWN2ru02/L3hN9qXnKSuzZcnkvxaUd68UohUWZfv03xCd1WNKZOB84V?= =?us-ascii?Q?LeXUFXg2pfK2B7syvwCFY70ISviklpPsxWbq8r0GSkzbGEkeAK/fyEXsl5Kj?= =?us-ascii?Q?AtWhwGeJc6PqlQqyhg9yi+kZssvk2o5F7xFilz7U0KKh07bv3vW6gHvBhBA9?= =?us-ascii?Q?KZoZcEYeA3zulSorGBlpB29T2Ip9?= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230031)(1800799015)(82310400017)(36860700004)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2024 10:53:04.6399 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c5b4273-d5db-4245-df68-08dc83bb588e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7461 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Gregory Etelson Non-template PMD implementation allocates ASO flow actions resources on-demand. Current PMD implementation iterated over actions array in search for actions that required ASO resources allocations. The patch replaced the iteration with actions flags bitmap queries. Signed-off-by: Gregory Etelson --- drivers/net/mlx5/mlx5_flow_hw.c | 102 ++++++++++++++------------------ 1 file changed, 45 insertions(+), 57 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 9f43fbfb35..f2ed2d8e46 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -12671,79 +12671,67 @@ static int flow_hw_register_matcher(struct rte_eth_dev *dev, NULL, "fail to register matcher"); } -static int flow_hw_ensure_action_pools_allocated(struct rte_eth_dev *dev, - const struct rte_flow_action actions[], - struct rte_flow_error *error) +static int +flow_hw_allocate_actions(struct rte_eth_dev *dev, + uint64_t action_flags, + struct rte_flow_error *error) { - bool actions_end = false; struct mlx5_priv *priv = dev->data->dev_private; int ret; uint obj_num; - for (; !actions_end; actions++) { - switch ((int)actions->type) { - case RTE_FLOW_ACTION_TYPE_AGE: - /* If no age objects were previously allocated. */ - if (!priv->hws_age_req) { - /* If no counters were previously allocated. */ - if (!priv->hws_cpool) { - obj_num = MLX5_CNT_NT_MAX(priv); - ret = mlx5_hws_cnt_pool_create(dev, obj_num, - priv->nb_queue, NULL); - if (ret) - goto err; - } - if (priv->hws_cpool) { - /* Allocate same number of counters. */ - ret = mlx5_hws_age_pool_init(dev, - priv->hws_cpool->cfg.request_num, - priv->nb_queue, false); - if (ret) - goto err; - } - } - break; - case RTE_FLOW_ACTION_TYPE_COUNT: + if (action_flags & MLX5_FLOW_ACTION_AGE) { + /* If no age objects were previously allocated. */ + if (!priv->hws_age_req) { /* If no counters were previously allocated. */ if (!priv->hws_cpool) { obj_num = MLX5_CNT_NT_MAX(priv); ret = mlx5_hws_cnt_pool_create(dev, obj_num, - priv->nb_queue, NULL); - if (ret) - goto err; - } - break; - case RTE_FLOW_ACTION_TYPE_CONNTRACK: - /* If no CT were previously allocated. */ - if (!priv->hws_ctpool) { - obj_num = MLX5_CT_NT_MAX(priv); - ret = mlx5_flow_ct_init(dev, obj_num, priv->nb_queue); - if (ret) - goto err; - } - break; - case RTE_FLOW_ACTION_TYPE_METER_MARK: - /* If no meters were previously allocated. */ - if (!priv->hws_mpool) { - obj_num = MLX5_MTR_NT_MAX(priv); - ret = mlx5_flow_meter_init(dev, obj_num, 0, 0, - priv->nb_queue); + priv->nb_queue, NULL); if (ret) goto err; } - break; - case RTE_FLOW_ACTION_TYPE_END: - actions_end = true; - break; - default: - break; + /* Allocate same number of counters. */ + ret = mlx5_hws_age_pool_init(dev, priv->hws_cpool->cfg.request_num, + priv->nb_queue, false); + if (ret) + goto err; + } + } + if (action_flags & MLX5_FLOW_ACTION_COUNT) { + /* If no counters were previously allocated. */ + if (!priv->hws_cpool) { + obj_num = MLX5_CNT_NT_MAX(priv); + ret = mlx5_hws_cnt_pool_create(dev, obj_num, + priv->nb_queue, NULL); + if (ret) + goto err; + } + } + if (action_flags & MLX5_FLOW_ACTION_CT) { + /* If no CT were previously allocated. */ + if (!priv->hws_ctpool) { + obj_num = MLX5_CT_NT_MAX(priv); + ret = mlx5_flow_ct_init(dev, obj_num, priv->nb_queue); + if (ret) + goto err; + } + } + if (action_flags & MLX5_FLOW_ACTION_METER) { + /* If no meters were previously allocated. */ + if (!priv->hws_mpool) { + obj_num = MLX5_MTR_NT_MAX(priv); + ret = mlx5_flow_meter_init(dev, obj_num, 0, 0, + priv->nb_queue); + if (ret) + goto err; } } return 0; err: return rte_flow_error_set(error, ret, - RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, "fail to allocate actions"); + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, "fail to allocate actions"); } /* TODO: remove dev if not used */ @@ -12861,7 +12849,7 @@ flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type, * The output actions bit mask instead of * looping on the actions array twice. */ - ret = flow_hw_ensure_action_pools_allocated(dev, actions, error); + ret = flow_hw_allocate_actions(dev, action_flags, error); if (ret) goto error; -- 2.25.1