[PATCH v3 03/17] net/ntnic: add interfaces for platform functionality

[Serhii Iliushyk <sil-plv@napatech.com>]

Add ntnic structures and prototypes for platform interfaces.

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
 .../nthw/core/include/nthw_clock_profiles.h   |  20 ++
 .../net/ntnic/nthw/core/include/nthw_core.h   |  32 +++
 .../net/ntnic/nthw/core/include/nthw_fpga.h   |  54 +++++
 .../ntnic/nthw/core/include/nthw_fpga_rst.h   |  18 ++
 .../net/ntnic/nthw/core/include/nthw_hif.h    | 152 +++++++++++++
 .../net/ntnic/nthw/core/include/nthw_igam.h   |  36 +++
 .../net/ntnic/nthw/core/include/nthw_iic.h    | 101 +++++++++
 .../nthw/core/include/nthw_mac_pcs_xxv.h      | 208 ++++++++++++++++++
 .../ntnic/nthw/core/include/nthw_mac_tfg.h    |  58 +++++
 .../net/ntnic/nthw/core/include/nthw_pcie3.h  |  99 +++++++++
 .../ntnic/nthw/core/include/nthw_phy_tile.h   | 123 +++++++++++
 .../net/ntnic/nthw/core/include/nthw_sdc.h    |  43 ++++
 .../net/ntnic/nthw/core/include/nthw_si5340.h |  33 +++
 .../net/ntnic/nthw/core/include/nthw_spi_v3.h | 105 +++++++++
 .../net/ntnic/nthw/core/include/nthw_spim.h   |  57 +++++
 .../net/ntnic/nthw/core/include/nthw_spis.h   |  62 ++++++
 .../net/ntnic/nthw/core/include/nthw_tsm.h    |  52 +++++
 17 files changed, 1253 insertions(+)
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_clock_profiles.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_core.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_fpga.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_fpga_rst.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_hif.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_igam.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_iic.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_mac_pcs_xxv.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_mac_tfg.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_pcie3.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_sdc.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_si5340.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_spi_v3.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_spim.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_spis.h
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_tsm.h

diff --git a/drivers/net/ntnic/nthw/core/include/nthw_clock_profiles.h b/drivers/net/ntnic/nthw/core/include/nthw_clock_profiles.h
new file mode 100644
index 0000000000..bf8911bca2
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_clock_profiles.h
@@ -0,0 +1,20 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTHW_CLOCK_PROFILES_H_
+#define _NTHW_CLOCK_PROFILES_H_
+
+/* TODO: figure out why static_assert(sizeof(x)...) does not work in plain C */
+#ifndef __cplusplus
+#ifndef __KERNEL__
+#include <assert.h>	/* static_assert */
+#endif	/* __KERNEL__ */
+#endif	/* __cplusplus */
+
+#include "nthw_helper.h"
+
+#include "clock_profiles_structs.h"
+
+#endif	/* _NTHW_CLOCK_PROFILES_H_ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_core.h b/drivers/net/ntnic/nthw/core/include/nthw_core.h
new file mode 100644
index 0000000000..f2d56a41f9
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_core.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_CORE_H__
+#define __NTHW_CORE_H__
+
+#include "nthw_helper.h"
+#include "nthw_utils.h"
+
+#include "nthw_platform_drv.h"
+#include "nthw_fpga_model.h"
+#include "nthw_hif.h"
+#include "nthw_pcie3.h"
+#include "nthw_iic.h"
+
+#include "nthw_mac_pcs_xxv.h"
+#include "nthw_mac_tfg.h"
+#include "nthw_sdc.h"
+
+#include "nthw_spim.h"
+#include "nthw_spis.h"
+
+#include "nthw_tsm.h"
+
+#include "nthw_si5340.h"
+
+#include "nthw_phy_tile.h"
+#include "nthw_igam.h"
+
+#endif	/* __NTHW_CORE_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_fpga.h b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h
new file mode 100644
index 0000000000..ee92b674a2
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h
@@ -0,0 +1,54 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_FPGA_H__
+#define __NTHW_FPGA_H__
+
+#include "nthw_drv.h"
+
+#include "nthw_fpga_model.h"
+
+#include "nthw_rac.h"
+#include "nthw_iic.h"
+
+#include "nthw_fpga_rst.h"
+
+int nthw_fpga_init(struct fpga_info_s *p_fpga_info);
+int nthw_fpga_shutdown(struct fpga_info_s *p_fpga_info);
+
+int nthw_fpga_get_param_info(struct fpga_info_s *p_fpga_info, nthw_fpga_t *p_fpga);
+
+int nthw_fpga_avr_probe(nthw_fpga_t *p_fpga, const int n_instance_no);
+
+int nthw_fpga_iic_scan(nthw_fpga_t *p_fpga, const int n_instance_no_begin,
+	const int n_instance_no_end);
+
+int nthw_fpga_silabs_detect(nthw_fpga_t *p_fpga, const int n_instance_no, const int n_dev_addr,
+	const int n_page_reg_addr);
+
+int nthw_fpga_si5340_clock_synth_init_fmt2(nthw_fpga_t *p_fpga, const uint8_t n_iic_addr,
+	const clk_profile_data_fmt2_t *p_clk_profile,
+	const int n_clk_profile_rec_cnt);
+
+struct nt50b0x_ops {
+	int (*nthw_fpga_nt50b0x_init)(struct fpga_info_s *p_fpga_info);
+};
+
+struct nt50b0x_ops *get_nt50b0x_ops(void);
+
+struct nt400dxx_ops {
+	int (*nthw_fpga_nt400dxx_init)(struct fpga_info_s *p_fpga_info);
+};
+
+struct nt400dxx_ops *get_nt400dxx_ops(void);
+
+struct nt200a0x_ops {
+	int (*nthw_fpga_nt200a0x_init)(struct fpga_info_s *p_fpga_info);
+};
+
+void register_nt200a0x_ops(struct nt200a0x_ops *ops);
+struct nt200a0x_ops *get_nt200a0x_ops(void);
+
+#endif	/* __NTHW_FPGA_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_fpga_rst.h b/drivers/net/ntnic/nthw/core/include/nthw_fpga_rst.h
new file mode 100644
index 0000000000..206120fa37
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_fpga_rst.h
@@ -0,0 +1,18 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_FPGA_RST_H__
+#define __NTHW_FPGA_RST_H__
+
+#include "nthw_drv.h"
+
+#include "nthw_fpga_model.h"
+
+#include "nthw_rac.h"
+#include "nthw_iic.h"
+
+#include "ntnic_nthw_fpga_rst_nt200a0x.h"
+
+#endif	/* __NTHW_FPGA_RST_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_hif.h b/drivers/net/ntnic/nthw/core/include/nthw_hif.h
new file mode 100644
index 0000000000..1e18ddfaf0
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_hif.h
@@ -0,0 +1,152 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_HIF_H__
+#define __NTHW_HIF_H__
+
+#define NTHW_TG_CNT_SIZE (4ULL)
+
+struct nthw_hif {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_hif;
+	int mn_instance;
+
+	nthw_register_t *mp_reg_ctrl;
+	nthw_field_t *mp_fld_ctrl_fsr;
+
+	nthw_register_t *mp_reg_prod_id_lsb;
+	nthw_field_t *mp_fld_prod_id_lsb_rev_id;
+	nthw_field_t *mp_fld_prod_id_lsb_ver_id;
+	nthw_field_t *mp_fld_prod_id_lsb_group_id;
+
+	nthw_register_t *mp_reg_prod_id_msb;
+	nthw_field_t *mp_fld_prod_id_msb_type_id;
+	nthw_field_t *mp_fld_prod_id_msb_build_no;
+
+	nthw_register_t *mp_reg_build_time;
+	nthw_field_t *mp_fld_build_time;
+
+	nthw_register_t *mp_reg_build_seed;
+	nthw_field_t *mp_fld_build_seed;
+
+	nthw_register_t *mp_reg_core_speed;
+	nthw_field_t *mp_fld_core_speed;
+	nthw_field_t *mp_fld_ddr3_speed;
+
+	nthw_register_t *mp_reg_int_mask;
+	nthw_field_t *mp_fld_int_mask_timer;
+	nthw_field_t *mp_fld_int_mask_port;
+	nthw_field_t *mp_fld_int_mask_pps;
+
+	nthw_register_t *mp_reg_int_clr;
+	nthw_field_t *mp_fld_int_clr_timer;
+	nthw_field_t *mp_fld_int_clr_port;
+	nthw_field_t *mp_fld_int_clr_pps;
+
+	nthw_register_t *mp_reg_int_force;
+	nthw_field_t *mp_fld_int_force_timer;
+	nthw_field_t *mp_fld_int_force_port;
+	nthw_field_t *mp_fld_int_force_pps;
+
+	nthw_register_t *mp_reg_sample_time;
+	nthw_field_t *mp_fld_sample_time;
+
+	nthw_register_t *mp_reg_status;
+	nthw_field_t *mp_fld_status_tags_in_use;
+	nthw_field_t *mp_fld_status_wr_err;
+	nthw_field_t *mp_fld_status_rd_err;
+
+	nthw_register_t *mp_reg_stat_ctrl;
+	nthw_field_t *mp_fld_stat_ctrl_ena;
+	nthw_field_t *mp_fld_stat_ctrl_req;
+
+	nthw_register_t *mp_reg_stat_rx;
+	nthw_field_t *mp_fld_stat_rx_counter;
+
+	nthw_register_t *mp_reg_stat_tx;
+	nthw_field_t *mp_fld_stat_tx_counter;
+
+	nthw_register_t *mp_reg_stat_ref_clk;
+	nthw_field_t *mp_fld_stat_ref_clk_ref_clk;
+
+	nthw_register_t *mp_reg_pci_test0;
+	nthw_field_t *mp_fld_pci_test0;
+
+	nthw_register_t *mp_reg_pci_test1;
+	nthw_field_t *mp_fld_pci_test1;
+
+	nthw_register_t *mp_reg_pci_test2;
+	nthw_field_t *mp_fld_pci_test2;
+
+	nthw_register_t *mp_reg_pci_test3;
+	nthw_field_t *mp_fld_pci_test3;
+
+	nthw_register_t *mp_reg_config;
+	nthw_field_t *mp_fld_max_tlp;
+	nthw_field_t *mp_fld_max_read;
+	nthw_field_t *mp_fld_ext_tag;
+
+	int mn_fpga_id_item;
+	int mn_fpga_id_prod;
+	int mn_fpga_id_ver;
+	int mn_fpga_id_rev;
+	int mn_fpga_id_build_no;
+
+	int mn_fpga_param_hif_per_ps;
+	uint32_t mn_fpga_hif_ref_clk_freq;
+};
+
+typedef struct nthw_hif nthw_hif_t;
+typedef struct nthw_hif nthw_hif;
+
+struct nthw_hif_end_point_err_counters {
+	uint32_t n_err_correctable, n_err_non_fatal, n_err_fatal;
+};
+
+struct nthw_hif_end_point_counters {
+	int n_numa_node;
+
+	int n_tg_direction;
+	int n_tg_pkt_size;
+	int n_tg_num_pkts;
+	int n_tg_delay;
+
+	uint64_t cur_rx, cur_tx;
+	uint64_t cur_pci_nt_util, cur_pci_xil_util;
+	uint64_t n_ref_clk_cnt;
+
+	uint64_t n_tags_in_use;
+	uint64_t n_rd_err;
+	uint64_t n_wr_err;
+
+	struct nthw_hif_end_point_err_counters s_rc_ep_pre, s_rc_ep_post, s_rc_ep_delta;
+	struct nthw_hif_end_point_err_counters s_ep_rc_pre, s_ep_rc_post, s_ep_rc_delta;
+
+	int bo_error;
+};
+
+struct nthw_hif_end_points {
+	struct nthw_hif_end_point_counters pri, sla;
+};
+
+nthw_hif_t *nthw_hif_new(void);
+void nthw_hif_delete(nthw_hif_t *p);
+int nthw_hif_init(nthw_hif_t *p, nthw_fpga_t *p_fpga, int n_instance);
+
+int nthw_hif_trigger_sample_time(nthw_hif_t *p);
+
+int nthw_hif_stat_req_enable(nthw_hif_t *p);
+int nthw_hif_stat_req_disable(nthw_hif_t *p);
+
+int nthw_hif_get_stat(nthw_hif_t *p, uint32_t *p_rx_cnt, uint32_t *p_tx_cnt,
+	uint32_t *p_ref_clk_cnt, uint32_t *p_tg_unit_size, uint32_t *p_tg_ref_freq,
+	uint64_t *p_tags_in_use, uint64_t *p_rd_err, uint64_t *p_wr_err);
+int nthw_hif_get_stat_rate(nthw_hif_t *p, uint64_t *p_pci_rx_rate, uint64_t *p_pci_tx_rate,
+	uint64_t *p_ref_clk_cnt, uint64_t *p_tags_in_use,
+	uint64_t *p_rd_err_cnt, uint64_t *p_wr_err_cnt);
+
+int nthw_hif_end_point_counters_sample(nthw_hif_t *p, struct nthw_hif_end_point_counters *epc);
+
+#endif	/* __NTHW_HIF_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_igam.h b/drivers/net/ntnic/nthw/core/include/nthw_igam.h
new file mode 100644
index 0000000000..05c09cc89a
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_igam.h
@@ -0,0 +1,36 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_IGAM_H__
+#define __NTHW_IGAM_H__
+
+#include "nthw_fpga_model.h"
+
+struct nt_igam {
+	nthw_fpga_t *mp_fpga;
+
+	nthw_module_t *mp_mod_igam;
+
+	int mn_igam_instance;
+
+	nthw_register_t *mp_reg_base;
+	nthw_field_t *mp_fld_base_ptr;
+	nthw_field_t *mp_fld_base_busy;
+	nthw_field_t *mp_fld_base_cmd;
+
+	nthw_register_t *mp_reg_data;
+	nthw_field_t *mp_fld_data_data;
+};
+
+typedef struct nt_igam nthw_igam_t;
+typedef struct nt_igam nthw_igam;
+
+nthw_igam_t *nthw_igam_new(void);
+void nthw_igam_delete(nthw_igam_t *p);
+int nthw_igam_init(nthw_igam_t *p, nthw_fpga_t *p_fpga, int mn_igam_instance);
+uint32_t nthw_igam_read(nthw_igam_t *p, uint32_t address);
+void nthw_igam_write(nthw_igam_t *p, uint32_t address, uint32_t data);
+
+#endif	/*  __NTHW_IGAM_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_iic.h b/drivers/net/ntnic/nthw/core/include/nthw_iic.h
new file mode 100644
index 0000000000..5193696455
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_iic.h
@@ -0,0 +1,101 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_IIC_H__
+#define __NTHW_IIC_H__
+
+#include "nthw_fpga_model.h"
+
+struct nthw_iic {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_iic;
+	int mn_iic_instance;
+
+	uint32_t mn_iic_cycle_time;
+	int mn_poll_delay;
+	int mn_bus_ready_retry;
+	int mn_data_ready_retry;
+	int mn_read_data_retry;
+	int mn_write_data_retry;
+
+	nthw_register_t *mp_reg_tsusta;
+	nthw_field_t *mp_fld_tsusta;
+
+	nthw_register_t *mp_reg_tsusto;
+	nthw_field_t *mp_fld_tsusto;
+
+	nthw_register_t *mp_reg_thdsta;
+	nthw_field_t *mp_fld_thdsta;
+
+	nthw_register_t *mp_reg_tsudat;
+	nthw_field_t *mp_fld_tsudat;
+
+	nthw_register_t *mp_reg_tbuf;
+	nthw_field_t *mp_fld_tbuf;
+
+	nthw_register_t *mp_reg_thigh;
+	nthw_field_t *mp_fld_thigh;
+
+	nthw_register_t *mp_reg_tlow;
+	nthw_field_t *mp_fld_tlow;
+
+	nthw_register_t *mp_reg_thddat;
+	nthw_field_t *mp_fld_thddat;
+
+	nthw_register_t *mp_reg_cr;
+	nthw_field_t *mp_fld_cr_en;
+	nthw_field_t *mp_fld_cr_msms;
+	nthw_field_t *mp_fld_cr_txfifo_reset;
+	nthw_field_t *mp_fld_cr_txak;
+
+	nthw_register_t *mp_reg_sr;
+	nthw_field_t *mp_fld_sr_bb;
+	nthw_field_t *mp_fld_sr_rxfifo_full;
+	nthw_field_t *mp_fld_sr_rxfifo_empty;
+	nthw_field_t *mp_fld_sr_txfifo_full;
+	nthw_field_t *mp_fld_sr_txfifo_empty;
+
+	nthw_register_t *mp_reg_tx_fifo;
+	nthw_field_t *mp_fld_tx_fifo_txdata;
+	nthw_field_t *mp_fld_tx_fifo_start;
+	nthw_field_t *mp_fld_tx_fifo_stop;
+
+	nthw_register_t *mp_reg_rx_fifo_pirq;
+	nthw_field_t *mp_fld_rx_fifo_pirq_cmp_val;
+
+	nthw_register_t *mp_reg_rx_fifo;
+	nthw_field_t *mp_fld_rx_fifo_rxdata;
+
+	nthw_register_t *mp_reg_softr;
+	nthw_field_t *mp_fld_softr_rkey;
+};
+
+typedef struct nthw_iic nthw_iic_t;
+typedef struct nthw_iic nthw_iic;
+
+nthw_iic_t *nthw_iic_new(void);
+int nthw_iic_init(nthw_iic_t *p, nthw_fpga_t *p_fpga, int n_iic_instance,
+	uint32_t n_iic_cycle_time);
+void nthw_iic_delete(nthw_iic_t *p);
+
+int nthw_iic_set_retry_params(nthw_iic_t *p, const int n_poll_delay, const int n_bus_ready_retry,
+	const int n_data_ready_retry, const int n_read_data_retry,
+	const int n_write_data_retry);
+
+int nthw_iic_read_data(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	void *p_void);
+int nthw_iic_readbyte(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	uint8_t *p_byte);
+int nthw_iic_write_data(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	void *p_void);
+int nthw_iic_writebyte(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len,
+	uint8_t *p_byte);
+bool nthw_iic_bus_ready(nthw_iic_t *p);
+bool nthw_iic_data_ready(nthw_iic_t *p);
+
+int nthw_iic_scan(nthw_iic_t *p);
+int nthw_iic_scan_dev_addr(nthw_iic_t *p, int n_dev_addr, int n_reg_addr);
+
+#endif	/* __NTHW_IIC_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_mac_pcs_xxv.h b/drivers/net/ntnic/nthw/core/include/nthw_mac_pcs_xxv.h
new file mode 100644
index 0000000000..4537decf12
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_mac_pcs_xxv.h
@@ -0,0 +1,208 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTHW_MAC_PCS_XXV_H_
+#define NTHW_MAC_PCS_XXV_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nthw_fpga_model.h"
+
+enum nthw_mac_pcs_xxv_led_mode_e {
+	NTHW_MAC_PCS_XXV_LED_AUTO = 0x00,
+	NTHW_MAC_PCS_XXV_LED_ON = 0x01,
+	NTHW_MAC_PCS_XXV_LED_OFF = 0x02,
+	NTHW_MAC_PCS_XXV_LED_PORTID = 0x03,
+};
+
+enum nthw_mac_pcs_xxv_dac_mode_e {
+	NTHW_MAC_PCS_XXV_DAC_OFF = 0x00,
+	NTHW_MAC_PCS_XXV_DAC_CA_25G_N = 0x01,
+	NTHW_MAC_PCS_XXV_DAC_CA_25G_S = 0x02,
+	NTHW_MAC_PCS_XXV_DAC_CA_25G_L = 0x03,
+};
+
+struct nthw_mac_pcs_xxv {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_mac_pcs_xxv;
+	int mn_instance;
+
+	uint8_t m_port_no;
+	bool m_mac_8x10G;
+
+#define NTHW_MAC_PCS_XXV_NUM_ELEMS 4
+	struct nthw_mac_pcs_xxv_registers_fields {
+		/* CORE_CONF */
+		nthw_register_t *mp_reg_core_conf;
+		nthw_field_t *mp_fld_core_conf_rx_enable;
+		nthw_field_t *mp_fld_core_conf_rx_force_resync;
+		nthw_field_t *mp_fld_core_conf_tx_enable;
+		nthw_field_t *mp_fld_core_conf_tx_ins_fcs;
+		nthw_field_t *mp_fld_core_conf_tx_ign_fcs;
+		nthw_field_t *mp_fld_core_conf_tx_send_lfi;
+		nthw_field_t *mp_fld_core_conf_tx_send_rfi;
+		nthw_field_t *mp_fld_core_conf_tx_send_idle;
+		nthw_field_t *mp_fld_core_conf_inline_mode;
+		nthw_field_t *mp_fld_core_conf_line_loopback;
+		nthw_field_t *mp_fld_core_conf_ts_at_eop;
+
+		/* ANEG_CONFIG */
+		nthw_register_t *mp_reg_aneg_config;
+		nthw_field_t *mp_fld_aneg_config_enable;
+		nthw_field_t *mp_fld_aneg_config_bypass;
+		nthw_field_t *mp_fld_aneg_config_restart;
+		nthw_field_t *mp_fld_aneg_config_pseudo;
+		nthw_field_t *mp_fld_aneg_config_nonce_seed;
+		nthw_field_t *mp_fld_aneg_config_remote_fault;
+		nthw_field_t *mp_fld_aneg_config_pause;
+		nthw_field_t *mp_fld_aneg_config_asmdir;
+		nthw_field_t *mp_fld_aneg_config_fec74_request10g;
+		nthw_field_t *mp_fld_aneg_config_hide_fec74;
+		nthw_field_t *mp_fld_aneg_config_fec74_request;
+		nthw_field_t *mp_fld_aneg_config_fec91_request;
+		nthw_field_t *mp_fld_aneg_config_fec91_ability;
+		nthw_field_t *mp_fld_aneg_config_rs_fec_request;
+		nthw_field_t *mp_fld_aneg_config_sw_fec_overwrite;
+		nthw_field_t *mp_fld_aneg_config_sw_speed_overwrite;
+
+		/* ANEG_ABILITY */
+		nthw_register_t *mp_reg_aneg_ability;
+		nthw_field_t *mp_fld_aneg_ability_25g_base_cr;
+		nthw_field_t *mp_fld_aneg_ability_25g_base_crs;
+		nthw_field_t *mp_fld_aneg_ability_25g_base_cr1;
+
+		/* LT_CONF */
+		nthw_register_t *mp_reg_lt_conf;
+		nthw_field_t *mp_fld_lt_conf_enable;
+		nthw_field_t *mp_fld_lt_conf_restart;
+		nthw_field_t *mp_fld_lt_conf_seed;
+
+		/* SUB_RST */
+		nthw_register_t *mp_reg_sub_rst;
+		nthw_field_t *mp_fld_sub_rst_rx_mac_pcs;
+		nthw_field_t *mp_fld_sub_rst_tx_mac_pcs;
+		nthw_field_t *mp_fld_sub_rst_rx_gt_data;
+		nthw_field_t *mp_fld_sub_rst_tx_gt_data;
+		nthw_field_t *mp_fld_sub_rst_rx_buf;
+		nthw_field_t *mp_fld_sub_rst_rx_pma;
+		nthw_field_t *mp_fld_sub_rst_tx_pma;
+		nthw_field_t *mp_fld_sub_rst_rx_pcs;
+		nthw_field_t *mp_fld_sub_rst_tx_pcs;
+		nthw_field_t *mp_fld_sub_rst_an_lt;
+		nthw_field_t *mp_fld_sub_rst_speed_ctrl;
+
+		/* SUB_RST_STATUS */
+		nthw_register_t *mp_reg_sub_rst_status;
+		nthw_field_t *mp_fld_sub_rst_status_user_rx_rst;
+		nthw_field_t *mp_fld_sub_rst_status_user_tx_rst;
+		nthw_field_t *mp_fld_sub_rst_status_qpll_lock;
+
+		/* LINK_SUMMARY */
+		nthw_register_t *mp_reg_link_summary;
+		nthw_field_t *mp_fld_link_summary_nt_phy_link_state;
+		nthw_field_t *mp_fld_link_summary_ll_nt_phy_link_state;
+		nthw_field_t *mp_fld_link_summary_abs;
+		nthw_field_t *mp_fld_link_summary_lh_abs;
+		nthw_field_t *mp_fld_link_summary_link_down_cnt;
+		/* Begin 2 x 10/25 Gbps only fields: */
+		nthw_field_t *mp_fld_link_summary_ll_rx_fec74_lock;
+		nthw_field_t *mp_fld_link_summary_lh_rx_rsfec_hi_ser;
+		nthw_field_t *mp_fld_link_summary_ll_rx_rsfec_lane_alignment;
+		nthw_field_t *mp_fld_link_summary_ll_tx_rsfec_lane_alignment;
+		nthw_field_t *mp_fld_link_summary_lh_rx_pcs_valid_ctrl_code;
+		/* End 2 x 10/25 Gbps only fields. */
+		nthw_field_t *mp_fld_link_summary_ll_rx_block_lock;
+		nthw_field_t *mp_fld_link_summary_lh_rx_high_bit_error_rate;
+		nthw_field_t *mp_fld_link_summary_lh_internal_local_fault;
+		nthw_field_t *mp_fld_link_summary_lh_received_local_fault;
+		nthw_field_t *mp_fld_link_summary_lh_local_fault;
+		nthw_field_t *mp_fld_link_summary_lh_remote_fault;
+		nthw_field_t *mp_fld_link_summary_lh_tx_local_fault;
+		nthw_field_t *mp_fld_link_summary_nim_interr;
+
+		/* GTY_LOOP */
+		nthw_register_t *mp_reg_gty_loop;
+		nthw_field_t *mp_fld_gty_loop_gt_loop;
+
+		/* GTY_CTL_RX */
+		nthw_register_t *mp_reg_gty_ctl_rx;
+		nthw_field_t *mp_fld_gty_ctl_rx_polarity;
+		nthw_field_t *mp_fld_gty_ctl_rx_lpm_en;
+		nthw_field_t *mp_fld_gty_ctl_rx_equa_rst;
+
+		/* GTY_CTL_TX */
+		nthw_register_t *mp_reg_gty_ctl_tx;
+		nthw_field_t *mp_fld_gty_ctl_tx_polarity;
+		nthw_field_t *mp_fld_gty_ctl_tx_inhibit;
+
+		/* LINK_SPEED */
+		nthw_register_t *mp_reg_link_speed;
+		nthw_field_t *mp_fld_link_speed_10g;
+		nthw_field_t *mp_fld_link_speed_toggle;
+
+		/* RS_FEC_CONF */
+		nthw_register_t *mp_reg_rs_fec_conf;
+		nthw_field_t *mp_fld_rs_fec_conf_rs_fec_enable;
+
+		/* DEBOUNCE_CTRL */
+		nthw_register_t *mp_reg_debounce_ctrl;
+		nthw_field_t *mp_field_debounce_ctrl_nt_port_ctrl;
+
+		/* FEC_CCW_CNT */
+		nthw_register_t *mp_reg_rs_fec_ccw;
+		nthw_field_t *mp_field_reg_rs_fec_ccw_reg_rs_fec_ccw_cnt;
+
+		/* FEC_UCW_CNT */
+		nthw_register_t *mp_reg_rs_fec_ucw;
+		nthw_field_t *mp_field_reg_rs_fec_ucw_reg_rs_fec_ucw_cnt;
+
+		/* TIMESTAMP_COMP */
+		nthw_register_t *mp_reg_timestamp_comp;
+		nthw_field_t *mp_field_timestamp_comp_rx_dly;
+		nthw_field_t *mp_field_timestamp_comp_tx_dly;
+
+		/* GTY_PRE_CURSOR */
+		nthw_register_t *mp_reg_gty_pre_cursor;
+		nthw_field_t *mp_field_gty_pre_cursor_tx_pre_csr;
+
+		/* GTY_DIFF_CTL */
+		nthw_register_t *mp_reg_gty_diff_ctl;
+		nthw_field_t *mp_field_gty_gty_diff_ctl_tx_diff_ctl;
+
+		/* GTY_POST_CURSOR */
+		nthw_register_t *mp_reg_gty_post_cursor;
+		nthw_field_t *mp_field_gty_post_cursor_tx_post_csr;
+	} regs[NTHW_MAC_PCS_XXV_NUM_ELEMS];
+};
+
+typedef struct nthw_mac_pcs_xxv nthw_mac_pcs_xxv_t;
+typedef struct nthw_mac_pcs_xxv nthw_mac_pcs_xxv;
+
+nthw_mac_pcs_xxv_t *nthw_mac_pcs_xxv_new(void);
+void nthw_mac_pcs_xxv_delete(nthw_mac_pcs_xxv_t *p);
+int nthw_mac_pcs_xxv_init(nthw_mac_pcs_xxv_t *p,
+	nthw_fpga_t *p_fpga,
+	int n_instance,
+	int n_channels,
+	bool mac_8x10G);
+
+void nthw_mac_pcs_xxv_get_link_summary(nthw_mac_pcs_xxv_t *p,
+	uint32_t *p_abs,
+	uint32_t *p_nt_phy_link_state,
+	uint32_t *p_lh_abs,
+	uint32_t *p_ll_nt_phy_link_state,
+	uint32_t *p_link_down_cnt,
+	uint32_t *p_nim_interr,
+	uint32_t *p_lh_local_fault,
+	uint32_t *p_lh_remote_fault,
+	uint32_t *p_lh_internal_local_fault,
+	uint32_t *p_lh_received_local_fault,
+	uint8_t index);
+
+void nthw_mac_pcs_xxv_reset_rx_gt_data(nthw_mac_pcs_xxv_t *p, bool enable, uint8_t index);
+
+void nthw_mac_pcs_xxv_set_rx_mac_pcs_rst(nthw_mac_pcs_xxv_t *p, bool enable, uint8_t index);
+
+#endif	/* NTHW_MAC_PCS_XXV_H_ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_mac_tfg.h b/drivers/net/ntnic/nthw/core/include/nthw_mac_tfg.h
new file mode 100644
index 0000000000..6caf47b378
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_mac_tfg.h
@@ -0,0 +1,58 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTHW_MAC_TFG_H_
+#define NTHW_MAC_TFG_H_
+
+struct nthw_mac_tfg {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_mac_tfg;
+	int mn_instance;
+
+	/* Params */
+	int mn_ifg_speed_mul;
+	int mn_ifg_speed_div;
+
+	/* TFG */
+	nthw_register_t *mp_reg_tfg_data;
+	nthw_register_t *mp_reg_tfg_addr;
+	nthw_register_t *mp_reg_tfg_ctrl;
+	nthw_register_t *mp_reg_tfg_repetition;
+
+	/* TFG ADDR */
+	nthw_field_t *mp_fld_tfg_addr_write_ram_adr;
+	nthw_field_t *mp_fld_tfg_addr_read_enable;
+	nthw_field_t *mp_fld_tfg_addr_read_done;
+
+	/* TFG DATA */
+	nthw_field_t *mp_fld_tfg_data_length;
+	nthw_field_t *mp_fld_tfg_data_gap;
+	nthw_field_t *mp_fld_tfg_data_id;
+
+	/* TFG CTRL */
+	nthw_field_t *mp_fld_tfg_wrap;
+	nthw_field_t *mp_fld_tfg_restart;
+	nthw_field_t *mp_fld_tfg_enable;
+	nthw_field_t *mp_fld_tfg_time_mode;
+	nthw_field_t *mp_fld_tfg_id_pos;
+	nthw_field_t *mp_fld_tfg_id_ena;
+	nthw_field_t *mp_fld_tfg_tx_active;
+
+	/* TFG REPETITION */
+	nthw_field_t *mp_fld_tfg_repetition_count;
+};
+
+typedef struct nthw_mac_tfg nthw_mac_tfg_t;
+typedef struct nthw_mac_tfg nthw_mac_tfg;
+
+nthw_mac_tfg_t *nthw_mac_tfg_new(void);
+void nthw_mac_tfg_delete(nthw_mac_tfg_t *p);
+int nthw_mac_tfg_init(nthw_mac_tfg_t *p, nthw_fpga_t *p_fpga, int n_instance);
+
+void nthw_mac_tfg_tfg_tx_start(nthw_mac_tfg_t *p, uint32_t repetition, uint32_t size,
+	uint32_t pkt_gap);
+void nthw_mac_tfg_tfg_tx_stop(nthw_mac_tfg_t *p);
+
+#endif	/* NTHW_MAC_TFG_H_ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_pcie3.h b/drivers/net/ntnic/nthw/core/include/nthw_pcie3.h
new file mode 100644
index 0000000000..32a18793bc
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_pcie3.h
@@ -0,0 +1,99 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_PCIE3_H__
+#define __NTHW_PCIE3_H__
+
+struct nthw_pcie3 {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_pcie3;
+	int mn_instance;
+
+	nthw_register_t *mp_reg_stat_ctrl;
+	nthw_field_t *mp_fld_stat_ctrl_req;
+	nthw_field_t *mp_fld_stat_ctrl_ena;
+
+	nthw_register_t *mp_reg_stat_rx;
+	nthw_field_t *mp_fld_stat_rx_counter;
+
+	nthw_register_t *mp_reg_stat_tx;
+	nthw_field_t *mp_fld_stat_tx_counter;
+
+	nthw_register_t *mp_reg_stat_rq_rdy;
+	nthw_field_t *mp_fld_stat_rq_rdy_counter;
+
+	nthw_register_t *mp_reg_stat_rq_vld;
+	nthw_field_t *mp_fld_stat_rq_vld_counter;
+
+	nthw_register_t *mp_reg_status0;
+	nthw_field_t *mp_fld_status0_tags_in_use;
+
+	nthw_register_t *mp_reg_stat_ref_clk;
+	nthw_field_t *mp_fld_stat_ref_clk_ref_clk;
+
+	nthw_register_t *mp_reg_rp_to_ep_err;
+	nthw_field_t *mp_fld_rp_to_ep_err_cor;
+	nthw_field_t *mp_fld_rp_to_ep_err_non_fatal;
+	nthw_field_t *mp_fld_rp_to_ep_err_fatal;
+
+	nthw_register_t *mp_reg_ep_to_rp_err;
+	nthw_field_t *mp_fld_ep_to_rp_err_cor;
+	nthw_field_t *mp_fld_ep_to_rp_err_non_fatal;
+	nthw_field_t *mp_fld_ep_to_rp_err_fatal;
+
+	nthw_register_t *mp_reg_sample_time;
+	nthw_field_t *mp_fld_sample_time;
+
+	nthw_register_t *mp_reg_pci_end_point;
+	nthw_field_t *mp_fld_pci_end_point_if_id;
+	nthw_field_t *mp_fld_pci_end_point_send_msg;
+	nthw_field_t *mp_fld_pci_end_point_get_msg;
+	nthw_field_t *mp_fld_pci_end_point_dmaep0_allow_mask;
+	nthw_field_t *mp_fld_pci_end_point_dmaep1_allow_mask;
+
+	nthw_register_t *mp_reg_pci_e3_mark_adr_lsb;
+	nthw_field_t *mp_fld_pci_e3_mark_adr_lsb_adr;
+
+	nthw_register_t *mp_reg_pci_e3_mark_adr_msb;
+	nthw_field_t *mp_fld_pci_e3_mark_adr_msb_adr;
+
+	nthw_register_t *mp_reg_pci_test0;
+	nthw_field_t *mp_fld_pci_test0;
+
+	nthw_register_t *mp_reg_pci_test1;
+	nthw_field_t *mp_fld_pci_test1;
+
+	nthw_register_t *mp_reg_pci_test2;
+	nthw_field_t *mp_fld_pci_test2;
+
+	nthw_register_t *mp_reg_pci_test3;
+	nthw_field_t *mp_fld_pci_test3;
+};
+
+typedef struct nthw_pcie3 nthw_pcie3_t;
+typedef struct nthw_pcie3 nthw_pcie3;
+
+nthw_pcie3_t *nthw_pcie3_new(void);
+void nthw_pcie3_delete(nthw_pcie3_t *p);
+int nthw_pcie3_init(nthw_pcie3_t *p, nthw_fpga_t *p_fpga, int n_instance);
+
+int nthw_pcie3_trigger_sample_time(nthw_pcie3_t *p);
+
+int nthw_pcie3_stat_req_enable(nthw_pcie3_t *p);
+int nthw_pcie3_stat_req_disable(nthw_pcie3_t *p);
+
+int nthw_pcie3_get_stat(nthw_pcie3_t *p, uint32_t *p_rx_cnt, uint32_t *p_tx_cnt,
+	uint32_t *p_ref_clk_cnt, uint32_t *p_tg_unit_size, uint32_t *p_tg_ref_freq,
+	uint32_t *p_tag_use_cnt, uint32_t *p_rq_rdy_cnt, uint32_t *p_rq_vld_cnt);
+int nthw_pcie3_get_stat_rate(nthw_pcie3_t *p, uint64_t *p_pci_rx_rate, uint64_t *p_pci_tx_rate,
+	uint64_t *p_ref_clk_cnt, uint64_t *p_tag_use_cnt,
+	uint64_t *p_pci_nt_bus_util, uint64_t *p_pci_xil_bus_util);
+
+int nthw_pcie3_end_point_counters_sample_pre(nthw_pcie3_t *p,
+	struct nthw_hif_end_point_counters *epc);
+int nthw_pcie3_end_point_counters_sample_post(nthw_pcie3_t *p,
+	struct nthw_hif_end_point_counters *epc);
+
+#endif	/* __NTHW_PCIE3_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h b/drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h
new file mode 100644
index 0000000000..86cacda85f
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_phy_tile.h
@@ -0,0 +1,123 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_PHY_TILE_H__
+#define __NTHW_PHY_TILE_H__
+
+#include "nthw_fpga_model.h"
+
+struct nt_phy_tile {
+	nthw_fpga_t *mp_fpga;
+
+	nthw_module_t *m_mod_phy_tile;
+
+	int mn_phy_tile_instance;
+
+	nthw_register_t *mp_reg_port_xcvr_base[2][4];
+	nthw_field_t *mp_fld_port_xcvr_base_ptr[2][4];
+	nthw_field_t *mp_fld_port_xcvr_base_busy[2][4];
+	nthw_field_t *mp_fld_port_xcvr_base_cmd[2][4];
+
+	nthw_register_t *mp_reg_port_xcvr_data[2][4];
+	nthw_field_t *mp_fld_port_xcvr_data_data[2][4];
+
+	nthw_register_t *mp_reg_port_eth_base[2][4];
+	nthw_field_t *mp_fld_port_eth_base_ptr[2][4];
+	nthw_field_t *mp_fld_port_eth_base_busy[2][4];
+	nthw_field_t *mp_fld_port_eth_base_cmd[2][4];
+
+	nthw_register_t *mp_reg_port_eth_data[2][4];
+	nthw_field_t *mp_fld_port_eth_data_data[2][4];
+
+	nthw_register_t *mp_reg_link_summary[2];
+	nthw_field_t *mp_fld_link_summary_nt_phy_link_state[2];
+	nthw_field_t *mp_fld_link_summary_ll_nt_phy_link_state[2];
+	nthw_field_t *mp_fld_link_summary_link_down_cnt[2];
+	nthw_field_t *mp_fld_link_summary_ll_rx_block_lock[2];
+	nthw_field_t *mp_fld_link_summary_ll_rx_am_lock[2];
+	nthw_field_t *mp_fld_link_summary_lh_rx_high_bit_error_rate[2];
+	nthw_field_t *mp_fld_link_summary_lh_received_local_fault[2];
+	nthw_field_t *mp_fld_link_summary_lh_remote_fault[2];
+
+	nthw_register_t *mp_reg_port_status;
+	nthw_field_t *mp_fld_port_status_rx_pcs_fully_aligned[2];
+	nthw_field_t *mp_fld_port_status_rx_hi_ber[2];
+	nthw_field_t *mp_fld_port_status_rx_remote_fault[2];
+	nthw_field_t *mp_fld_port_status_rx_local_fault[2];
+	nthw_field_t *mp_fld_port_status_rx_am_lock[2];
+
+	nthw_register_t *mp_reg_port_config;
+	nthw_field_t *mp_fld_port_config_dyn_reset;
+	nthw_field_t *mp_fld_port_config_reset[2];
+	nthw_field_t *mp_fld_port_config_rx_reset[2];
+	nthw_field_t *mp_fld_port_config_tx_reset[2];
+
+	nthw_register_t *mp_reg_port_comp[2];
+	nthw_field_t *mp_fld_port_comp_rx_compensation[2];
+	nthw_field_t *mp_fld_port_comp_tx_compensation[2];
+
+	nthw_register_t *mp_reg_dyn_reconfig_base;
+	nthw_field_t *mp_fld_dyn_reconfig_base_ptr;
+	nthw_field_t *mp_fld_dyn_reconfig_base_busy;
+	nthw_field_t *mp_fld_dyn_reconfig_base_cmd;
+
+	nthw_register_t *mp_reg_dyn_reconfig_data;
+	nthw_field_t *mp_fld_dyn_reconfig_data_data;
+
+	nthw_register_t *mp_reg_scratch;
+	nthw_field_t *mp_fld_scratch_data;
+
+	nthw_register_t *mp_reg_dr_cfg_status;
+	nthw_field_t *mp_fld_dr_cfg_status_curr_profile_id;
+	nthw_field_t *mp_fld_dr_cfg_status_in_progress;
+	nthw_field_t *mp_fld_dr_cfg_status_error;
+};
+
+typedef struct nt_phy_tile nthw_phy_tile_t;
+typedef struct nt_phy_tile nt_phy_tile;
+
+nthw_phy_tile_t *nthw_phy_tile_new(void);
+void nthw_phy_tile_delete(nthw_phy_tile_t *p);
+int nthw_phy_tile_init(nthw_phy_tile_t *p, nthw_fpga_t *p_fpga, int mn_phy_tile_instance);
+uint32_t nthw_phy_tile_get_tx_pol_inv(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane);
+uint32_t nthw_phy_tile_get_rx_pol_inv(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane);
+void nthw_phy_tile_set_tx_pol_inv(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane, bool invert);
+void nthw_phy_tile_set_rx_pol_inv(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane, bool invert);
+void nthw_phy_tile_set_host_loopback(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane,
+	bool enable);
+uint32_t nthw_phy_tile_get_host_loopback(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane);
+void nthw_phy_tile_set_tx_equalization(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane,
+	uint32_t pre_tap2, uint32_t main_tap, uint32_t pre_tap1,
+	uint32_t post_tap1);
+void nthw_phy_tile_get_tx_equalization(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane);
+void nthw_phy_tile_get_link_summary(nthw_phy_tile_t *p, uint32_t *p_nt_phy_link_state,
+	uint32_t *p_ll_nt_phy_link_state, uint32_t *p_lh_local_fault,
+	uint32_t *p_lh_remote_fault, uint8_t index);
+void nthw_phy_tile_set_tx_reset(nthw_phy_tile_t *p, uint8_t intf_no, bool reset);
+void nthw_phy_tile_set_rx_reset(nthw_phy_tile_t *p, uint8_t intf_no, bool reset);
+bool nthw_phy_tile_read_fec_enabled_by_scratch(nthw_phy_tile_t *p, uint8_t intf_no);
+void nthw_phy_tile_write_fec_enabled_by_scratch(nthw_phy_tile_t *p, uint8_t intf_no,
+	bool fec_enabled);
+void nthw_phy_tile_set_dyn_reset(nthw_phy_tile_t *p, uint8_t reset);
+bool nthw_phy_tile_get_rx_hi_ber(nthw_phy_tile_t *p, uint8_t intf_no);
+bool nthw_phy_tile_get_rx_am_lock(nthw_phy_tile_t *p, uint8_t intf_no);
+void nthw_phy_tile_set_timestamp_comp_rx(nthw_phy_tile_t *p, uint8_t intf_no, uint32_t value);
+uint32_t nthw_phy_tile_get_timestamp_comp_rx(nthw_phy_tile_t *p, uint8_t intf_no);
+void nthw_phy_tile_set_timestamp_comp_tx(nthw_phy_tile_t *p, uint8_t intf_no, uint32_t value);
+void nthw_phy_tile_write_dr_ctrl_mc_cfgcsr_reg(nthw_phy_tile_t *p, uint32_t offset,
+	uint32_t wdata);
+uint32_t nthw_phy_tile_polling_for_bit_dr_ctrl(nthw_phy_tile_t *p, uint32_t channel,
+	uint32_t offset, uint32_t bit_offset);
+uint32_t nthw_phy_tile_read_eth(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane,
+	uint32_t address);
+void nthw_phy_tile_write_eth(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane, uint32_t address,
+	uint32_t data);
+bool nthw_phy_tile_configure_fec(nthw_phy_tile_t *p, uint8_t intf_no, bool enable);
+uint32_t nthw_phy_tile_read_xcvr(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane,
+	uint32_t address);
+void nthw_phy_tile_write_xcvr(nthw_phy_tile_t *p, uint8_t intf_no, uint8_t lane, uint32_t address,
+	uint32_t data);
+
+#endif	/* __NTHW_PHY_TILE_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_sdc.h b/drivers/net/ntnic/nthw/core/include/nthw_sdc.h
new file mode 100644
index 0000000000..53df9c7520
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_sdc.h
@@ -0,0 +1,43 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_SDC_H__
+#define __NTHW_SDC_H__
+
+struct nthw_sdc {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_sdc;
+	int mn_instance;
+
+	nthw_field_t *mp_fld_ctrl_init;
+	nthw_field_t *mp_fld_ctrl_run_test;
+	nthw_field_t *mp_fld_ctrl_stop_client;
+	nthw_field_t *mp_fld_ctrl_test_enable;
+
+	nthw_field_t *mp_fld_stat_calib;
+	nthw_field_t *mp_fld_stat_cell_cnt_stopped;
+	nthw_field_t *mp_fld_stat_err_found;
+	nthw_field_t *mp_fld_stat_init_done;
+	nthw_field_t *mp_fld_stat_mmcm_lock;
+	nthw_field_t *mp_fld_stat_pll_lock;
+	nthw_field_t *mp_fld_stat_resetting;
+
+	nthw_field_t *mp_fld_cell_cnt;
+	nthw_field_t *mp_fld_cell_cnt_period;
+	nthw_field_t *mp_fld_fill_level;
+	nthw_field_t *mp_fld_max_fill_level;
+};
+
+typedef struct nthw_sdc nthw_sdc_t;
+typedef struct nthw_sdc nthw_sdc;
+
+nthw_sdc_t *nthw_sdc_new(void);
+int nthw_sdc_init(nthw_sdc_t *p, nthw_fpga_t *p_fpga, int n_instance);
+void nthw_sdc_delete(nthw_sdc_t *p);
+
+int nthw_sdc_wait_states(nthw_sdc_t *p, const int n_poll_iterations, const int n_poll_interval);
+int nthw_sdc_get_states(nthw_sdc_t *p, uint64_t *pn_result_mask);
+
+#endif	/* __NTHW_SDC_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_si5340.h b/drivers/net/ntnic/nthw/core/include/nthw_si5340.h
new file mode 100644
index 0000000000..62e6c2d443
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_si5340.h
@@ -0,0 +1,33 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_SI5340_H__
+#define __NTHW_SI5340_H__
+
+#include "nthw_clock_profiles.h"
+
+#define SI5340_SUCCESS (0)
+#define SI5340_FAILED (999)
+#define SI5340_TIMEOUT (666)
+
+struct nthw_si5340 {
+	uint8_t mn_iic_addr;
+	nthw_iic_t *mp_nthw_iic;
+	int mn_clk_cfg;
+	uint8_t m_si5340_page;
+};
+
+typedef struct nthw_si5340 nthw_si5340_t;
+
+nthw_si5340_t *nthw_si5340_new(void);
+int nthw_si5340_init(nthw_si5340_t *p, nthw_iic_t *p_nthw_iic, uint8_t n_iic_addr);
+void nthw_si5340_delete(nthw_si5340_t *p);
+
+int nthw_si5340_config(nthw_si5340_t *p, const void *p_data, int data_cnt,
+	clk_profile_data_fmt_t data_format);
+int nthw_si5340_config_fmt2(nthw_si5340_t *p, const clk_profile_data_fmt2_t *p_data,
+	const int data_cnt);
+
+#endif	/* __NTHW_SI5338_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_spi_v3.h b/drivers/net/ntnic/nthw/core/include/nthw_spi_v3.h
new file mode 100644
index 0000000000..b051a0a9fc
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_spi_v3.h
@@ -0,0 +1,105 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NT4GA_SPI_V3__
+#define __NT4GA_SPI_V3__
+
+/* Must include v1.x series. The first v1.0a only had 248 bytes of storage. v2.0x have 255 */
+#define MAX_AVR_CONTAINER_SIZE (248)
+
+enum avr_opcodes {
+	__AVR_OP_NOP = 0,	/* v2 NOP command */
+	/* version handlers */
+	AVR_OP_VERSION = 1,
+	AVR_OP_SPI_VERSION = 2,	/* v2.0+ command Get protocol version */
+	AVR_OP_SYSINFO = 3,
+	/* Ping handlers */
+	AVR_OP_PING = 4,
+	AVR_OP_PING_DELAY = 5,
+	/* i2c handlers */
+	AVR_OP_I2C_READ = 9,
+	AVR_OP_I2C_WRITE = 10,
+	AVR_OP_I2C_RANDOM_READ = 11,
+	/* VPD handlers */
+	AVR_OP_VPD_READ = 19,
+	AVR_OP_VPD_WRITE = 20,
+	/* SENSOR handlers */
+	AVR_OP_SENSOR_FETCH = 28,
+	/* The following command are only relevant to V3 */
+	AVR_OP_SENSOR_MON_CONTROL = 42,
+	AVR_OP_SENSOR_MON_SETUP = 43,
+	/* special version handler */
+	AVR_OP_SYSINFO_2 = 62,
+};
+
+#define GEN2_AVR_IDENT_SIZE (20)
+#define GEN2_AVR_VERSION_SIZE (50)
+
+#define GEN2_PN_SIZE (13)
+#define GEN2_PBA_SIZE (16)
+#define GEN2_SN_SIZE (10)
+#define GEN2_BNAME_SIZE (14)
+#define GEN2_PLATFORM_SIZE (72)
+#define GEN2_VPD_SIZE_TOTAL                                                                       \
+	(1 + GEN2_PN_SIZE + GEN2_PBA_SIZE + GEN2_SN_SIZE + GEN2_BNAME_SIZE + GEN2_PLATFORM_SIZE + \
+	 2)
+
+typedef struct vpd_eeprom_s {
+	uint8_t psu_hw_version;	/* Hw revision - MUST NEVER ne overwritten. */
+	/* Vital Product Data: P/N   (13bytes ascii 0-9) */
+	uint8_t vpd_pn[GEN2_PN_SIZE];
+	/* Vital Product Data: PBA   (16bytes ascii 0-9) */
+	uint8_t vpd_pba[GEN2_PBA_SIZE];
+	/* Vital Product Data: S/N   (10bytes ascii 0-9) */
+	uint8_t vpd_sn[GEN2_SN_SIZE];
+	/* Vital Product Data: Board Name (10bytes ascii) (e.g. "ntmainb1e2" or "ntfront20b1") */
+	uint8_t vpd_board_name[GEN2_BNAME_SIZE];
+	/*
+	 * Vital Product Data: Other (72bytes of MAC addresses or other stuff.. (gives up to 12 mac
+	 * addresses)
+	 */
+	uint8_t vpd_platform_section[GEN2_PLATFORM_SIZE];
+	/* CRC16 checksum of all of above. This field is not included in the checksum */
+	uint16_t crc16;
+} vpd_eeprom_t;
+
+typedef struct {
+	uint8_t psu_hw_revision;
+	char board_type[GEN2_BNAME_SIZE + 1];
+	char product_id[GEN2_PN_SIZE + 1];
+	char pba_id[GEN2_PBA_SIZE + 1];
+	char serial_number[GEN2_SN_SIZE + 1];
+	uint8_t product_family;
+	uint32_t feature_mask;
+	uint32_t invfeature_mask;
+	uint8_t no_of_macs;
+	uint8_t mac_address[6];
+	uint16_t custom_id;
+	uint8_t user_id[8];
+} board_info_t;
+
+struct tx_rx_buf {
+	uint16_t size;
+	void *p_buf;
+};
+
+struct nthw_spi_v3 {
+	int m_time_out;
+	int mn_instance_no;
+	nthw_spim_t *mp_spim_mod;
+	nthw_spis_t *mp_spis_mod;
+};
+
+typedef struct nthw_spi_v3 nthw_spi_v3_t;
+typedef struct nthw_spi_v3 nthw_spi_v3;
+
+nthw_spi_v3_t *nthw_spi_v3_new(void);
+int nthw_spi_v3_init(nthw_spi_v3_t *p, nthw_fpga_t *p_fpga, int n_instance_no);
+
+int nthw_spi_v3_set_timeout(nthw_spi_v3_t *p, int time_out);
+int nthw_spi_v3_transfer(nthw_spi_v3_t *p, uint16_t opcode, struct tx_rx_buf *tx_buf,
+	struct tx_rx_buf *rx_buf);
+
+#endif	/* __NT4GA_SPI_V3__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_spim.h b/drivers/net/ntnic/nthw/core/include/nthw_spim.h
new file mode 100644
index 0000000000..473ceb86d6
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_spim.h
@@ -0,0 +1,57 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_SPIM_H__
+#define __NTHW_SPIM_H__
+
+struct nthw_spim {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_spim;
+	int mn_instance;
+
+	nthw_register_t *mp_reg_srr;
+	nthw_field_t *mp_fld_srr_rst;
+
+	nthw_register_t *mp_reg_cr;
+	nthw_field_t *mp_fld_cr_loop;
+	nthw_field_t *mp_fld_cr_en;
+	nthw_field_t *mp_fld_cr_txrst;
+	nthw_field_t *mp_fld_cr_rxrst;
+
+	nthw_register_t *mp_reg_sr;
+	nthw_field_t *mp_fld_sr_done;
+	nthw_field_t *mp_fld_sr_txempty;
+	nthw_field_t *mp_fld_sr_rxempty;
+	nthw_field_t *mp_fld_sr_txfull;
+	nthw_field_t *mp_fld_sr_rxfull;
+	nthw_field_t *mp_fld_sr_txlvl;
+	nthw_field_t *mp_fld_sr_rxlvl;
+
+	nthw_register_t *mp_reg_dtr;
+	nthw_field_t *mp_fld_dtr_dtr;
+
+	nthw_register_t *mp_reg_drr;
+	nthw_field_t *mp_fld_drr_drr;
+
+	nthw_register_t *mp_reg_cfg;
+	nthw_field_t *mp_fld_cfg_pre;
+
+	nthw_register_t *mp_reg_cfg_clk;
+	nthw_field_t *mp_fld_cfg_clk_mode;
+};
+
+typedef struct nthw_spim nthw_spim_t;
+typedef struct nthw_spim nthw_spim;
+
+nthw_spim_t *nthw_spim_new(void);
+int nthw_spim_init(nthw_spim_t *p, nthw_fpga_t *p_fpga, int n_instance);
+void nthw_spim_delete(nthw_spim_t *p);
+
+uint32_t nthw_spim_reset(nthw_spim_t *p);
+uint32_t nthw_spim_enable(nthw_spim_t *p, bool b_enable);
+uint32_t nthw_spim_get_tx_fifo_empty(nthw_spim_t *p, bool *pb_empty);
+uint32_t nthw_spim_write_tx_fifo(nthw_spim_t *p, uint32_t n_data);
+
+#endif	/* __NTHW_SPIM_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_spis.h b/drivers/net/ntnic/nthw/core/include/nthw_spis.h
new file mode 100644
index 0000000000..b9a7b6b49d
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_spis.h
@@ -0,0 +1,62 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_SPIS_H__
+#define __NTHW_SPIS_H__
+
+struct nthw_spis {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_spis;
+	int mn_instance;
+
+	nthw_register_t *mp_reg_srr;
+	nthw_field_t *mp_fld_srr_rst;
+
+	nthw_register_t *mp_reg_cr;
+	nthw_field_t *mp_fld_cr_loop;
+	nthw_field_t *mp_fld_cr_en;
+	nthw_field_t *mp_fld_cr_txrst;
+	nthw_field_t *mp_fld_cr_rxrst;
+	nthw_field_t *mp_fld_cr_debug;
+
+	nthw_register_t *mp_reg_sr;
+	nthw_field_t *mp_fld_sr_done;
+	nthw_field_t *mp_fld_sr_txempty;
+	nthw_field_t *mp_fld_sr_rxempty;
+	nthw_field_t *mp_fld_sr_txfull;
+	nthw_field_t *mp_fld_sr_rxfull;
+	nthw_field_t *mp_fld_sr_txlvl;
+	nthw_field_t *mp_fld_sr_rxlvl;
+	nthw_field_t *mp_fld_sr_frame_err;
+	nthw_field_t *mp_fld_sr_read_err;
+	nthw_field_t *mp_fld_sr_write_err;
+
+	nthw_register_t *mp_reg_dtr;
+	nthw_field_t *mp_fld_dtr_dtr;
+
+	nthw_register_t *mp_reg_drr;
+	nthw_field_t *mp_fld_drr_drr;
+
+	nthw_register_t *mp_reg_ram_ctrl;
+	nthw_field_t *mp_fld_ram_ctrl_adr;
+	nthw_field_t *mp_fld_ram_ctrl_cnt;
+
+	nthw_register_t *mp_reg_ram_data;
+	nthw_field_t *mp_fld_ram_data_data;
+};
+
+typedef struct nthw_spis nthw_spis_t;
+typedef struct nthw_spis nthw_spis;
+
+nthw_spis_t *nthw_spis_new(void);
+int nthw_spis_init(nthw_spis_t *p, nthw_fpga_t *p_fpga, int n_instance);
+void nthw_spis_delete(nthw_spis_t *p);
+
+uint32_t nthw_spis_reset(nthw_spis_t *p);
+uint32_t nthw_spis_enable(nthw_spis_t *p, bool b_enable);
+uint32_t nthw_spis_get_rx_fifo_empty(nthw_spis_t *p, bool *pb_empty);
+uint32_t nthw_spis_read_rx_fifo(nthw_spis_t *p, uint32_t *p_data);
+
+#endif	/* __NTHW_SPIS_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_tsm.h b/drivers/net/ntnic/nthw/core/include/nthw_tsm.h
new file mode 100644
index 0000000000..3c766370b4
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_tsm.h
@@ -0,0 +1,52 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_TSM_H__
+#define __NTHW_TSM_H__
+
+struct nthw_tsm {
+	nthw_fpga_t *mp_fpga;
+	nthw_module_t *mp_mod_tsm;
+	int mn_instance;
+
+	nthw_field_t *mp_fld_config_ts_format;
+
+	nthw_field_t *mp_fld_timer_ctrl_timer_en_t0;
+	nthw_field_t *mp_fld_timer_ctrl_timer_en_t1;
+
+	nthw_field_t *mp_fld_timer_timer_t0_max_count;
+
+	nthw_field_t *mp_fld_timer_timer_t1_max_count;
+
+	nthw_register_t *mp_reg_ts_lo;
+	nthw_field_t *mp_fld_ts_lo;
+
+	nthw_register_t *mp_reg_ts_hi;
+	nthw_field_t *mp_fld_ts_hi;
+
+	nthw_register_t *mp_reg_time_lo;
+	nthw_field_t *mp_fld_time_lo;
+
+	nthw_register_t *mp_reg_time_hi;
+	nthw_field_t *mp_fld_time_hi;
+};
+
+typedef struct nthw_tsm nthw_tsm_t;
+typedef struct nthw_tsm nthw_tsm;
+
+nthw_tsm_t *nthw_tsm_new(void);
+int nthw_tsm_init(nthw_tsm_t *p, nthw_fpga_t *p_fpga, int n_instance);
+
+int nthw_tsm_get_ts(nthw_tsm_t *p, uint64_t *p_ts);
+int nthw_tsm_get_time(nthw_tsm_t *p, uint64_t *p_time);
+
+int nthw_tsm_set_timer_t0_enable(nthw_tsm_t *p, bool b_enable);
+int nthw_tsm_set_timer_t0_max_count(nthw_tsm_t *p, uint32_t n_timer_val);
+int nthw_tsm_set_timer_t1_enable(nthw_tsm_t *p, bool b_enable);
+int nthw_tsm_set_timer_t1_max_count(nthw_tsm_t *p, uint32_t n_timer_val);
+
+int nthw_tsm_set_config_ts_format(nthw_tsm_t *p, uint32_t n_val);
+
+#endif	/* __NTHW_TSM_H__ */
-- 
2.45.0