From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 647D14415C; Wed, 5 Jun 2024 10:42:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA59340DDD; Wed, 5 Jun 2024 10:41:57 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2055.outbound.protection.outlook.com [40.107.236.55]) by mails.dpdk.org (Postfix) with ESMTP id A6EAA40A89 for ; Wed, 5 Jun 2024 10:41:55 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=oDUd3TzY06sE2CNDVjblKWuW2b/JYWRiqoKqDtJvZDZufCTyzzhZ/qVihbKGAdhzVlndmzKmehnYuhKZAiJAYC1tIKPOClD5h26E/aCXdIZnzRDdvqq1ZrR/VPRHbFzAhyMcqmDdoctJAC6IZRiDZdO6nKTt9qIx5PFxACB1dJc0DeZC80Yw/IporxAihYcrjzIi5U//+WCP382/PUE92tVKokMOHjxqSylCrnMupgxZWH9UN6U3MRo5vwDCt27pSx5s5MaoV0VUijoixV33G2z9YxfozC0H/h8LB2nRZlOBU9OwtEj00vSAKvUdxPPTeopTh5KNmzoY/u5lu7VKyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hy16SpbZq7qf6J8hq2lAs2/pYQDlNOFgus1jvAUjMTk=; b=fD6znS51lc977mPEgI4A2RhH3qgmKHM6/3hheYiBDHI5ZpzIplwFn1Y2EBPVS5FNGCpB7ijNGBTuJSGATOV2bhHk628fq1j18LhF1n3c3vcoE44lmmzbCWBOCtaUFe8yPh/H8XlP0tRNI/x0mhsd1RYIRlDuY/qDxiyPOd6dOZXjBDGfdQ48sDeQUlaZIWPZrwOTBAHWDGZD/nZjnt1dHdsbA32YgIeSx9AiozKGiLd8OCtZBM7iyVkJQg10YhyYSN3oHpjKEN11adXQ+KxwzXLQaFWfnebkHlWrOYyhH0TJtPUcwPG01mp/f08PAbWHxNjmJSjJVt9BIyALB4ds7w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hy16SpbZq7qf6J8hq2lAs2/pYQDlNOFgus1jvAUjMTk=; b=GhlBbX635LVthp+txcGfeQ4y0L9lHhkiQ8RRthYKpLSCCxk5dPCGS+ewXFVP/T3icJhIXTINDptZVPPND6yTIbcxErBk83ykrKWcCbARrYxJnUS3NxvzV4lFPIE2m3+xC/NdXNr/tar9GLpylK2CN2pL45a9eEgqbp9SEJI6uO0s+5HhFF1QCfb+zRdiv53CehIbK9pq9/e1WXFaEnvnpNmDWZEZNZhEDCH6u7Dz+6XPzp8E17tVe2aYwjltLs1uwcMAJHuPDiGAmI8rSVDF88orqcvphUGN6in84NxMCiYMA2Y/GGDZ2F4T+n7rPQHtRFn85L7AweRiOcZMukq4JA== Received: from CH0PR03CA0182.namprd03.prod.outlook.com (2603:10b6:610:e4::7) by MW5PR12MB5681.namprd12.prod.outlook.com (2603:10b6:303:19e::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.27; Wed, 5 Jun 2024 08:41:52 +0000 Received: from CH2PEPF0000009F.namprd02.prod.outlook.com (2603:10b6:610:e4:cafe::ba) by CH0PR03CA0182.outlook.office365.com (2603:10b6:610:e4::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.30 via Frontend Transport; Wed, 5 Jun 2024 08:41:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF0000009F.mail.protection.outlook.com (10.167.244.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.15 via Frontend Transport; Wed, 5 Jun 2024 08:41:52 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 5 Jun 2024 01:41:41 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 5 Jun 2024 01:41:38 -0700 From: Rongwei Liu To: , , , , , CC: Dariusz Sosnowski Subject: [PATCH v5 3/3] net/mlx5: implement VXLAN last reserved modification Date: Wed, 5 Jun 2024 11:41:11 +0300 Message-ID: <20240605084111.87359-4-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20240605084111.87359-1-rongweil@nvidia.com> References: <6114865.NeCsiYhmir@thomas> <20240605084111.87359-1-rongweil@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009F:EE_|MW5PR12MB5681:EE_ X-MS-Office365-Filtering-Correlation-Id: 33b33487-0a68-4e68-98b6-08dc853b5935 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|36860700004|1800799015|376005|82310400017; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?+sA0KaBN0QhjO101Ow3rHt7SYvOBkx85HAw5RHe6YPBswq3Rs4qx/WdZ2tNs?= =?us-ascii?Q?oGLVnaXAo0AoJGXSIowa4H5CGlpOTKAP4P3LYcFJ/E/u36IsL93twYaAyIgo?= =?us-ascii?Q?JLyPGMMTfahw87yW6VyWa1zmvJ4mHTQab+iSt2H7R80Jc9gk29wbJ6PfhYrv?= =?us-ascii?Q?FlKvjX8Faz0tGrTiMW5Dil+Nn9sTCN2zClJPOqU4Yd0cSWKIDKm0lM2Llwm8?= =?us-ascii?Q?mnIzigtysP2n0DCAwAWbghHR+eu5DxtLLjSicz5yS2fO41vxdnFBWFvQzHW5?= =?us-ascii?Q?Zfxi9CxfElez3SegJBdHJlXXDh6aYVCZ+eKCDhjIn8fstVF1TTEfS4Kyi8h5?= =?us-ascii?Q?BTXYc6FhDOFUBVTDuE0acOTTwFyqr1FJ4VjYPPOny8pwjhpDU2KpvNQg4lYL?= =?us-ascii?Q?R59zgsN/OuaGUqA7Q1eqTRmIN5HXg0/LBRCUVq6FxYhz6Oi1yza4t8waCHHU?= =?us-ascii?Q?Zu12/NJTAHYquiVBgdfM+LEf7W+miPz9csFYjUGRjwFsMfwATG4YABI6Uru6?= =?us-ascii?Q?RkIWE/Pkv20tcjVIql8lpDaA6eIcTz6Vcs2cPnsoSovvlItAAqZX6DfTByK8?= =?us-ascii?Q?KTPOariqsBZTEe8etVVaoRbb0Ozu86EBUKq3e5E6O0y9eBVO50zW7GorNYJU?= =?us-ascii?Q?CUP0O/EIWSoG2A1RWySNevT76wBG9ZuaIL48nVnbglW6nR6g/gtJy7FRUQI2?= =?us-ascii?Q?7S71hYxa4+LqCjjQkIP6cHVKHFXiUE9F4wKpfDQrLaGWQ7/FkowFW8Qu8fRG?= =?us-ascii?Q?KSahgVDR17xWuIL9ti3pby5Uxl/c0tVfviyuPuyCkZME60/IeyZyZKNaB0B9?= =?us-ascii?Q?nBVHJBLAhR0MSVC9ulSLFQTzVkzV1zt/IB7tiSg8bVcSoXAywp0Qb0LAScRn?= =?us-ascii?Q?VnmgVWYMOKB6jf6bQmZIB/9Y8vGiCwYIlXvnEamFthdQXAwOIT/qVb1Hc6OO?= =?us-ascii?Q?owFcf2EaW6ZU6BUaHd6FyRsNvWocwj/GWQEPVTPbhf7pie9dAqV/fev1+nma?= =?us-ascii?Q?hoeYbRDrOsHrgX4hIJomzuU5X1lk/QJ8zHIJgfr1lDQuD3xe0aOI+RfvOvBx?= =?us-ascii?Q?Wv/1YNdlXAueltIm2LrHSXI+p7gzO2QLSJLaTzjpVppSGtYMp2LO8QqT4ifD?= =?us-ascii?Q?0QvjfTqfUeXp+61zI25hmB5SMszkWXtkPLtHD4s6VIwZXuF08YXmlBywOhv0?= =?us-ascii?Q?r0L0/f7jVFFop6vJ5Hch3lu82R4tORsBOz9CwkaoNZswa8FWsjHPOjfdreQI?= =?us-ascii?Q?SxfKT+NORMH/0098pAVHJPuyFzt9vSHwZYnXezTVZbXStbZ6tkg8X2eBHqDb?= =?us-ascii?Q?df6Ewi5e7a8xdK1VxPF9ks1OA0fv2ZXOKqgqob+0mEmqJjNIvXyYPehuNZKT?= =?us-ascii?Q?nllw0+rgm0OFMPgvcCidlFEdmLJx?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004)(1800799015)(376005)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2024 08:41:52.4298 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 33b33487-0a68-4e68-98b6-08dc853b5935 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5681 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implementing the VxLAN last reserved byte modification. Following the RFC, the field is only 1 byte and needs to use the field_length as 8 instead of the real dst_field->size. Signed-off-by: Rongwei Liu Acked-by: Dariusz Sosnowski --- doc/guides/nics/mlx5.rst | 5 +++++ drivers/net/mlx5/mlx5_flow_dv.c | 12 ++++++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++ 3 files changed, 22 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index b5928d40b2..8b3aaf5aac 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -637,6 +637,11 @@ Limitations - Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported. - Modification of the 802.1Q tag is not supported. - Modification of VXLAN network or GENEVE network ID is supported only for HW steering. + - Modification of the VXLAN header is supported with below limitations: + + - Only for HW steering (``dv_flow_en=2``). + - Support VNI and the last reserved byte modifications for traffic with default + UDP destination port. 4789 for VXLAN and VXLAN-GBP, 4790 for VXLAN-GPE. - Modification of GENEVE network ID is not supported when configured ``FLEX_PARSER_PROFILE_ENABLE`` supports Geneve TLV options. See :ref:`mlx5_firmware_config` for more flex parser information. diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 06f5427abf..99abb2f2fb 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1439,6 +1439,8 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev, case RTE_FLOW_FIELD_VXLAN_VNI: case RTE_FLOW_FIELD_GENEVE_VNI: return 24; + case RTE_FLOW_FIELD_VXLAN_LAST_RSVD: + return 8; case RTE_FLOW_FIELD_GTP_TEID: case RTE_FLOW_FIELD_MPLS: case RTE_FLOW_FIELD_TAG: @@ -2038,6 +2040,16 @@ mlx5_flow_field_id_to_modify_info else info[idx].offset = off_be; break; + case RTE_FLOW_FIELD_VXLAN_LAST_RSVD: + MLX5_ASSERT(data->offset + width <= 8); + /* Last_rsvd is on bits 7-0 of TUNNEL_HDR_DW_1. */ + off_be = 8 - (data->offset + width); + info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_TUNNEL_HDR_DW_1}; + if (mask) + mask[idx] = flow_modify_info_mask_8(width, off_be); + else + info[idx].offset = off_be; + break; case RTE_FLOW_FIELD_GENEVE_OPT_TYPE: MLX5_ASSERT(data->offset + width <= 8); modi_id = flow_geneve_opt_modi_field_get(priv, data); diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 63194935a3..01362ae121 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -1385,6 +1385,10 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev, value = *(const uint8_t *)item.spec; value = rte_cpu_to_be_32(value << 8); item.spec = &value; + } else if (conf->dst.field == RTE_FLOW_FIELD_VXLAN_LAST_RSVD) { + value = *(const uint8_t *)item.spec << 24; + value = rte_cpu_to_be_32(value); + item.spec = &value; } } else { type = conf->operation == RTE_FLOW_MODIFY_SET ? @@ -5580,6 +5584,7 @@ flow_hw_validate_modify_field_level(const struct rte_flow_field_data *data, case RTE_FLOW_FIELD_ESP_SPI: case RTE_FLOW_FIELD_ESP_SEQ_NUM: case RTE_FLOW_FIELD_VXLAN_VNI: + case RTE_FLOW_FIELD_VXLAN_LAST_RSVD: case RTE_FLOW_FIELD_GENEVE_VNI: case RTE_FLOW_FIELD_GENEVE_OPT_TYPE: case RTE_FLOW_FIELD_GENEVE_OPT_CLASS: -- 2.27.0