From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 449F244173; Thu, 6 Jun 2024 12:12:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3082D42D80; Thu, 6 Jun 2024 12:12:35 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2072.outbound.protection.outlook.com [40.107.244.72]) by mails.dpdk.org (Postfix) with ESMTP id CD4AC427DD for ; Thu, 6 Jun 2024 12:12:32 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HY/4xmoAw8JXU8iYEXKIaBLRSDremmr0iFpKFdWfGgXyI0gYEB8dSf00F1wzVHYA4c6E4zDNfPW52NyTRkamEBXGlStuXvxfsshzpqpHkogLDMdC+1wXBM1jej6jBV1jtrLqhPFdLOKkrbYCAN2DJtpFePBZEx1nyDaIAKw8N9AfwhZYKtwqTZYvVQLOiwBV470Ee3md3BttxBRcLKcoVIGRQQgDZq9e0YXwT16kJtzRg2MpXXQxHNr/wbjo+aNQrBRyiLExu6x8aufqhcj+Y//8qrfsrJNAwYrytPubsYn5ATkxl1jBXEcDyVySlN3tAxbDD6EaMHOGMYOdS8Bk4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xPdZaMTJVXbdXp5Wda9Nsccr8ZL/lwHqQ4D8XwJx0Xw=; b=noS01yz4jYoEVkidRihquzhfOXL4RP+/yDCyYvXD3F2leSfwVYsXii2zdZLLxaZGw8cPRUccmsafUdgMX3BgVYYxhYeY4I4ektzmfDLoJCKNu4w3ddOQXQaBw2Uk6Yp3+ljrOCLw7Agdb+f2bngM7h3ytyqF4YaHGicJ8K7rrWFe3S7Nc8wku0ubl52aLYil9o6lkZ4UuzmVLbtTF9odOGXD8Q38v1h/g6A2yVQKagjKUcV7dxI87xKSYMwMi1Q/0rQxVEyOj9EfKciQNneJsbYd/SYL4vCGLNe7T9rx0kThRxgVIGGihpq7wfj1hksSS9AG3jCcVgLbhVbDrjvIWQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xPdZaMTJVXbdXp5Wda9Nsccr8ZL/lwHqQ4D8XwJx0Xw=; b=f6jVNx3EIEZMr09l8LpMfUf9UDdtGITMZcNevBwK1GRwT/UrXFrrjS4yg55zBWibGRI1W559xNuv+G7RWCvdp2eUfeMX9StAlfOLYqgQRKo87Iij8IuUndHFgORaOsUzkhxNBNgHbtLEOzaP/vpePh0HUUL5MVsq3vQ2MyB5dnxrYBYyBOaeQJlXb8W05OVX1bywn7c7bYh7fTJn+ImbKBqVVrXKW91rv9GIgJgk0RLOqEqC73bvROv3Lc70DNIIi0evovNA9EjbBHm4kINCV/amsXLgjnW7dc9+ltTc9Amq+3tlvsUlas3dHFyvIuxwFj/f1K/hpM7pe5zOmJWbFw== Received: from DM6PR03CA0071.namprd03.prod.outlook.com (2603:10b6:5:100::48) by LV8PR12MB9183.namprd12.prod.outlook.com (2603:10b6:408:193::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.33; Thu, 6 Jun 2024 10:12:30 +0000 Received: from CY4PEPF0000E9D0.namprd03.prod.outlook.com (2603:10b6:5:100:cafe::50) by DM6PR03CA0071.outlook.office365.com (2603:10b6:5:100::48) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7656.21 via Frontend Transport; Thu, 6 Jun 2024 10:12:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CY4PEPF0000E9D0.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.15 via Frontend Transport; Thu, 6 Jun 2024 10:12:29 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 6 Jun 2024 03:12:24 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 6 Jun 2024 03:12:24 -0700 Received: from nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4 via Frontend Transport; Thu, 6 Jun 2024 03:12:22 -0700 From: Maayan Kashani To: CC: , , , Gregory Etelson , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad Subject: [PATCH v4 1/6] net/mlx5: update NTA rule pattern and actions flags Date: Thu, 6 Jun 2024 13:12:09 +0300 Message-ID: <20240606101214.172057-2-mkashani@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20240606101214.172057-1-mkashani@nvidia.com> References: <20240603105241.10482-1-mkashani@nvidia.com> <20240606101214.172057-1-mkashani@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D0:EE_|LV8PR12MB9183:EE_ X-MS-Office365-Filtering-Correlation-Id: b43dff08-8ea2-4456-2ed1-08dc86112c66 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|376005|36860700004|82310400017; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4lV1cP5E2jG0eknLctWqwcPKlmJNtCyUXoTA+THhwODIBpjTVvHq/X7nUZG6?= =?us-ascii?Q?yf/xrDz3ccVQAxCJKtilPMR52BZMlkcC6wXljKZY2YqaSanmotq+LLJQOMmI?= =?us-ascii?Q?Xg4kX+3INbY2CtQEQsh666vkrZpTw1sD17DFNLcIkvfafmUFGzxH8isAdMej?= =?us-ascii?Q?MEXY16Ygf6C45BuJHbILby+UjEtQPbhhnoOiPyl4TtF1j2LbIRjOrBhGWiQG?= =?us-ascii?Q?UEjPBxmt5uOxN+A4dK65fFzUTF4qJ2xD0ix8+3YhuydeCtascBeBXs41ivc4?= =?us-ascii?Q?6Jx43mHzw9kg5Lmy40/dD0EakJ6SyoA5XiVzdpZBpp+0P6150CxmrpV7gcNq?= =?us-ascii?Q?NZ1jff/Ta/7qNbDqvNqSTQByBg7dEBd25SXGHOgHsUSzIO1rmTxM7mqiqikR?= =?us-ascii?Q?J2ppYBzJsFzan09DdkfAWVXCkJVn6oDu4IA+MHTcNiYQtoRe68D4HnkivXj7?= =?us-ascii?Q?w+IXa3x6uQUwX1i9UJoeFFSClVgUgecFy0EpAUCO557TuQl+E2QsNsTA1rRT?= =?us-ascii?Q?4b4CPbBSQcjShy8g/FicUNiJ3z3VN9zUrwYuehzKn7YP+wx4+KSQYUJ3UDUA?= =?us-ascii?Q?j1NsK/UTtDCFoq269xw2pW63ols2yZUbCdOFpgJPbObTU5u3GsSIKnFB+WED?= =?us-ascii?Q?kjkycK48vLCTlnq3kSyiBnW0kRwIrw7WOGzEgKN0U0K/zf+3b+LIimAJRwQ8?= =?us-ascii?Q?TveCYbWluhUerc0ZBDb5gzwXH+Sw/VPdbeOgi49i8x7q97rl6OjZXrH7RIBA?= =?us-ascii?Q?8EmpgnsLUJ6J5jGK8LRI6P8Jh3E4mbWMjWdo1D6vuqVRKgV1eoy7+7jvBQvZ?= =?us-ascii?Q?tg10vvmJzghIEbsMSR6ugkpWBLvw0+59kuxEhOOtebqHwH/xARVKV/bEoekm?= =?us-ascii?Q?SgsH6DosJtsJz4OkXXZeKRK8MBh2XByoumUPn+Tyc2BZM7CcTQ+91ztqDT6p?= =?us-ascii?Q?ie4MnzGjMsw9ufIBsC0OSMjIRK61S99smKpfWr9xeIJG8kXPr1Cq8VIuB+dx?= =?us-ascii?Q?a5OH+2L/TYLFwpCtQsZUYdG37U4qFXk7BHp3JK460C7gJMM0Tk+vTHqXv6H3?= =?us-ascii?Q?Q4VhWGqsYmQPPWYR/vz0V9b8XiXxNg7dfBKt/AkGnS7aBH8nAXU9Rg6rryPr?= =?us-ascii?Q?sn3r2qHbFnFnp8DLGLUvmU290k18KJASvdQz+2vRtwDQ4j8yFl6ZzQM0rrXj?= =?us-ascii?Q?DbP+GctVaGYLhg7u7BxeV2K+H+P/6k525SBqUxEm5hIoKt7w95fyAjHNcZw/?= =?us-ascii?Q?CVXXZJA9QC0vjyLL70bi4zyDjZ1YfBbZHCI4mm+fbdba11ctXfac294WZ1hJ?= =?us-ascii?Q?XVZFj+z/X/FvP+twN6QLAX67s4pmeR0lGOipJ0TgSgwTe9Tn7fwRMP0aSQMO?= =?us-ascii?Q?58QxW1h6y/5tEBjQ9xbBcBdRqGzqXbe0Cox/6wxTU1GMVnFE0g=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230031)(1800799015)(376005)(36860700004)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2024 10:12:29.6134 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b43dff08-8ea2-4456-2ed1-08dc86112c66 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9183 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Gregory Etelson Move pattern flags bitmap to flow_hw_list_create. Create actions flags bitmap in flow_hw_list_create. PMD uses pattern and actions bitmaps for direct queries instead of iterating arrays. Signed-off-by: Gregory Etelson Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow_hw.c | 147 +++++++++++++++++++++++++++----- 1 file changed, 126 insertions(+), 21 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index d938b5976a..696f675f63 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -568,6 +568,111 @@ flow_hw_matching_item_flags_get(const struct rte_flow_item items[]) return item_flags; } +static uint64_t +flow_hw_action_flags_get(const struct rte_flow_action actions[], + struct rte_flow_error *error) +{ + uint64_t action_flags = 0; + const struct rte_flow_action *action; + + for (action = actions; action->type != RTE_FLOW_ACTION_TYPE_END; action++) { + int type = (int)action->type; + switch (type) { + case RTE_FLOW_ACTION_TYPE_INDIRECT: + switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) { + case MLX5_INDIRECT_ACTION_TYPE_RSS: + goto rss; + case MLX5_INDIRECT_ACTION_TYPE_AGE: + goto age; + case MLX5_INDIRECT_ACTION_TYPE_COUNT: + goto count; + case MLX5_INDIRECT_ACTION_TYPE_CT: + goto ct; + case MLX5_INDIRECT_ACTION_TYPE_METER_MARK: + goto meter; + default: + goto error; + } + break; + case RTE_FLOW_ACTION_TYPE_DROP: + action_flags |= MLX5_FLOW_ACTION_DROP; + break; + case RTE_FLOW_ACTION_TYPE_MARK: + action_flags |= MLX5_FLOW_ACTION_MARK; + break; + case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: + action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN; + break; + case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: + action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN; + break; + case RTE_FLOW_ACTION_TYPE_JUMP: + action_flags |= MLX5_FLOW_ACTION_JUMP; + break; + case RTE_FLOW_ACTION_TYPE_QUEUE: + action_flags |= MLX5_FLOW_ACTION_QUEUE; + break; + case RTE_FLOW_ACTION_TYPE_RSS: +rss: + action_flags |= MLX5_FLOW_ACTION_RSS; + break; + case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: + case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: + action_flags |= MLX5_FLOW_ACTION_ENCAP; + break; + case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: + action_flags |= MLX5_FLOW_ACTION_ENCAP; + break; + case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: + case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: + action_flags |= MLX5_FLOW_ACTION_DECAP; + break; + case RTE_FLOW_ACTION_TYPE_RAW_DECAP: + action_flags |= MLX5_FLOW_ACTION_DECAP; + break; + case RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL: + action_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL; + break; + case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: + action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD; + break; + case RTE_FLOW_ACTION_TYPE_PORT_ID: + case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: + action_flags |= MLX5_FLOW_ACTION_PORT_ID; + break; + case RTE_FLOW_ACTION_TYPE_AGE: +age: + action_flags |= MLX5_FLOW_ACTION_AGE; + break; + case RTE_FLOW_ACTION_TYPE_COUNT: +count: + action_flags |= MLX5_FLOW_ACTION_COUNT; + break; + case RTE_FLOW_ACTION_TYPE_CONNTRACK: +ct: + action_flags |= MLX5_FLOW_ACTION_CT; + break; + case RTE_FLOW_ACTION_TYPE_METER_MARK: +meter: + action_flags |= MLX5_FLOW_ACTION_METER; + break; + case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS: + action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS; + break; + case RTE_FLOW_ACTION_TYPE_VOID: + case RTE_FLOW_ACTION_TYPE_END: + break; + default: + goto error; + } + } + return action_flags; +error: + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, + action, "invalid flow action"); + return 0; +} + /** * Register destination table DR jump action. * @@ -12339,21 +12444,20 @@ flow_hw_encap_decap_resource_register static int flow_hw_translate_flow_actions(struct rte_eth_dev *dev, - const struct rte_flow_attr *attr, - const struct rte_flow_action actions[], - struct rte_flow_hw *flow, - struct mlx5_flow_hw_action_params *ap, - struct mlx5_hw_actions *hw_acts, - uint64_t item_flags, - bool external, - struct rte_flow_error *error) + const struct rte_flow_attr *attr, + const struct rte_flow_action actions[], + struct rte_flow_hw *flow, + struct mlx5_flow_hw_action_params *ap, + struct mlx5_hw_actions *hw_acts, + uint64_t item_flags, uint64_t action_flags, + bool external, + struct rte_flow_error *error) { int ret = 0; uint32_t src_group = 0; enum mlx5dr_table_type table_type; struct rte_flow_template_table *table = NULL; struct mlx5_flow_group grp; - uint64_t action_flags = 0; struct rte_flow_actions_template *at = NULL; struct rte_flow_actions_template_attr template_attr = { .egress = attr->egress, @@ -12631,14 +12735,13 @@ static int flow_hw_apply(struct rte_eth_dev *dev __rte_unused, * @return * 0 on success, negative errno value otherwise and rte_errno set. */ -static int flow_hw_create_flow(struct rte_eth_dev *dev, - enum mlx5_flow_type type, - const struct rte_flow_attr *attr, - const struct rte_flow_item items[], - const struct rte_flow_action actions[], - bool external, - struct rte_flow_hw **flow, - struct rte_flow_error *error) +static int +flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type, + const struct rte_flow_attr *attr, + const struct rte_flow_item items[], + const struct rte_flow_action actions[], + uint64_t item_flags, uint64_t action_flags, bool external, + struct rte_flow_hw **flow, struct rte_flow_error *error) { int ret; struct mlx5_hw_actions hw_act; @@ -12668,8 +12771,6 @@ static int flow_hw_create_flow(struct rte_eth_dev *dev, .tbl_type = 0, }; - uint64_t item_flags = 0; - memset(&hw_act, 0, sizeof(hw_act)); if (attr->transfer) tbl_type = MLX5DR_TABLE_TYPE_FDB; @@ -12710,7 +12811,7 @@ static int flow_hw_create_flow(struct rte_eth_dev *dev, /* Note: the actions should be saved in the sub-flow rule itself for reference. */ ret = flow_hw_translate_flow_actions(dev, attr, actions, *flow, &ap, &hw_act, - item_flags, external, error); + item_flags, action_flags, external, error); if (ret) goto error; @@ -12848,11 +12949,15 @@ static uintptr_t flow_hw_list_create(struct rte_eth_dev *dev, { int ret; struct rte_flow_hw *flow = NULL; + uint64_t item_flags = flow_hw_matching_item_flags_get(items); + uint64_t action_flags = flow_hw_action_flags_get(actions, error); /*TODO: Handle split/expand to num_flows. */ /* Create single flow. */ - ret = flow_hw_create_flow(dev, type, attr, items, actions, external, &flow, error); + ret = flow_hw_create_flow(dev, type, attr, items, actions, + item_flags, action_flags, + external, &flow, error); if (ret) goto free; if (flow) -- 2.21.0