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Thu, 6 Jun 2024 03:12:30 -0700 From: Maayan Kashani To: CC: , , , Gregory Etelson , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad Subject: [PATCH v4 3/6] net/mlx5: support indirect actions in non-template setup Date: Thu, 6 Jun 2024 13:12:11 +0300 Message-ID: <20240606101214.172057-4-mkashani@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20240606101214.172057-1-mkashani@nvidia.com> References: <20240603105241.10482-1-mkashani@nvidia.com> <20240606101214.172057-1-mkashani@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|MW4PR12MB7191:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e9ade42-98ca-4df8-574a-08dc86113096 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|36860700004|376005|82310400017; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?xHtviNTL8jxQ/I/WNHRKCselsxCIx3QXax2AfVpVC8OeChRVpL6Ck9vjC6t1?= =?us-ascii?Q?Ai8QJ6hYgAzonJxt7erjE/rVuveVguGpJXw9fjpkeJTlsy8wp5EQP0GJb9dW?= =?us-ascii?Q?24FhqgUP2/lj8jKmEJRQWVYHXvY85I16Q5MiN4SIU9TvvL+WsDya2IXdbZcg?= =?us-ascii?Q?WgZ+i92DxKMO+uRNjrf0bOG75OjG9E4lJFTrlompNvUEe2+zvNO2lbPcXony?= =?us-ascii?Q?P+KQYp1nFrYgjNXmt0H9LyMpXLQmWGMCD+CqrNSulkv7p/aCJiXAGgIhRcaB?= =?us-ascii?Q?aHpRN3fel0+g6QfLLIG5CDUII/Gl+jMvYyvVcNMZHoN0Q5eOwxGmWKfSa/m7?= =?us-ascii?Q?2XG0NV5C1obXatX51opsILrge1tu0mTs5yp1B+SKDq2b7PrIPUjl6aHqGbA7?= =?us-ascii?Q?MmsF0d7VS44uOqcOv8OENXauqRWC5XNizcLg4W0OpCn/wP+Z7EG+z2AwTS9e?= =?us-ascii?Q?0sY6/PA/7VchLJlIKwUnMm/NmfNUeW4+PnS/jFu6BIb+sPhWrS5jooO5kI2n?= =?us-ascii?Q?DviyXPvdlnx0MAH47WS8sCeBjs8mi0CaBbGF9vqAaR9cC28uCsac57OuRlYI?= =?us-ascii?Q?z/w2qy3KgMTpFTE6Py9Ueh5tmzpIfRo/hjiviPtxPaC+VUARNMjMZvuJZJ/Q?= =?us-ascii?Q?bfUAnbvNgn8OkoD65E+5L0Whm2Mt9V3SxXzEnFg1/xR/IGNoahJHItp3pfa6?= =?us-ascii?Q?GiGjBh0Cay0zVV9gfT6ispg0uoZN/9ZFXyXHnh/tMxNWYT6QtfKXKJ/B3Ui+?= =?us-ascii?Q?YSSmpoJTW0aYSPo6rwlB0ZSUokQVlgymhl7JMgXw9luanxyso9/eahNdtzpQ?= =?us-ascii?Q?qaEcjcme23Vt3akpB7nZLLbvsXbany//7wtPhWCpUbBmFv3WY/WQQE9U8LqB?= =?us-ascii?Q?xJee+QnUyMhreQg7DkYdbA7ej4u3Lz/GUT8//yecn11mM/waG4ZAMBj94TlX?= =?us-ascii?Q?TPGom3YDL5aXvHwM+MLZyOZoABl0S/WP08QzQ4aPE8FAg/uBrkvlRQc3Qds8?= =?us-ascii?Q?avHU4hircipYLRM2FanqQgCroakJsdhi4QJgCh5taZI1LWnYqmXh39uwV1aJ?= =?us-ascii?Q?lQDbPcuNTa3ZAAM/9d62aGdyaEl0ZcK8OU/epVaJbu13adKi6ikOSnASbnm1?= =?us-ascii?Q?He2yaKS7fzH5YCaE5P4Wq8xYY4d26hWZgl7gXDjnTtCMEkZu6Oarp7mMelRh?= =?us-ascii?Q?DyxbUVYBLmp80wzqHjuS2x8YRzSVP3/4yQBHz9nf8WGnc3p5qukM2fx8Vh/M?= =?us-ascii?Q?4WOItexfh8znFdPOk/RPXEZ1G8YxfkbHWaL3vbSTSFPuqWarImIch+qUxK/R?= =?us-ascii?Q?K4Sbbsu98H1rZUWTUMNduFphSsqPG9VLKOUx822ZmkLKL55gQKdCOI2+f+Tz?= =?us-ascii?Q?y6XiXZHjxGOZ/FYAGyWq9NHp3A/lOxdRNiA4lOtomAp9pFqOvg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230031)(1800799015)(36860700004)(376005)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2024 10:12:36.6086 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e9ade42-98ca-4df8-574a-08dc86113096 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7191 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Gregory Etelson Add support for the RSS, AGE, COUNT and CONNTRACK indirect flow actions for the non-template flow rules. Signed-off-by: Gregory Etelson Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow_hw.c | 111 +++++++++++++++++++++++++------- 1 file changed, 89 insertions(+), 22 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 7984bf2f73..9f43fbfb35 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -12431,6 +12431,91 @@ flow_hw_encap_decap_resource_register return 0; } +static enum rte_flow_action_type +flow_nta_get_indirect_action_type(const struct rte_flow_action *action) +{ + switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) { + case MLX5_INDIRECT_ACTION_TYPE_RSS: + return RTE_FLOW_ACTION_TYPE_RSS; + case MLX5_INDIRECT_ACTION_TYPE_AGE: + return RTE_FLOW_ACTION_TYPE_AGE; + case MLX5_INDIRECT_ACTION_TYPE_COUNT: + return RTE_FLOW_ACTION_TYPE_COUNT; + case MLX5_INDIRECT_ACTION_TYPE_CT: + return RTE_FLOW_ACTION_TYPE_CONNTRACK; + default: + break; + } + return RTE_FLOW_ACTION_TYPE_END; +} + +static void +flow_nta_set_mh_mask_conf(const struct rte_flow_action_modify_field *action_conf, + struct rte_flow_action_modify_field *mask_conf) +{ + memset(mask_conf, 0xff, sizeof(*mask_conf)); + mask_conf->operation = action_conf->operation; + mask_conf->dst.field = action_conf->dst.field; + mask_conf->src.field = action_conf->src.field; +} + +union actions_conf { + struct rte_flow_action_modify_field modify_field; + struct rte_flow_action_raw_encap raw_encap; + struct rte_flow_action_vxlan_encap vxlan_encap; + struct rte_flow_action_nvgre_encap nvgre_encap; +}; + +static int +flow_nta_build_template_mask(const struct rte_flow_action actions[], + struct rte_flow_action masks[MLX5_HW_MAX_ACTS], + union actions_conf mask_conf[MLX5_HW_MAX_ACTS]) +{ + int i; + + for (i = 0; i == 0 || actions[i - 1].type != RTE_FLOW_ACTION_TYPE_END; i++) { + const struct rte_flow_action *action = &actions[i]; + struct rte_flow_action *mask = &masks[i]; + union actions_conf *conf = &mask_conf[i]; + + mask->type = action->type; + switch (action->type) { + case RTE_FLOW_ACTION_TYPE_INDIRECT: + mask->type = flow_nta_get_indirect_action_type(action); + if (!mask->type) + return -EINVAL; + break; + case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: + flow_nta_set_mh_mask_conf(action->conf, (void *)conf); + mask->conf = conf; + break; + case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: + /* This mask will set this action as shared. */ + memset(conf, 0xff, sizeof(struct rte_flow_action_raw_encap)); + mask->conf = conf; + break; + case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: + /* This mask will set this action as shared. */ + conf->vxlan_encap.definition = + ((const struct rte_flow_action_vxlan_encap *) + action->conf)->definition; + mask->conf = conf; + break; + case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: + /* This mask will set this action as shared. */ + conf->nvgre_encap.definition = + ((const struct rte_flow_action_nvgre_encap *) + action->conf)->definition; + mask->conf = conf; + break; + default: + break; + } + } + return 0; +#undef NTA_CHECK_CONF_BUF_SIZE +} + static int flow_hw_translate_flow_actions(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, @@ -12454,30 +12539,12 @@ flow_hw_translate_flow_actions(struct rte_eth_dev *dev, .transfer = attr->transfer, }; struct rte_flow_action masks[MLX5_HW_MAX_ACTS]; - struct rte_flow_action_raw_encap encap_conf; - struct rte_flow_action_modify_field mh_conf[MLX5_HW_MAX_ACTS]; + union actions_conf mask_conf[MLX5_HW_MAX_ACTS]; - memset(&masks, 0, sizeof(masks)); - int i = -1; - do { - i++; - masks[i].type = actions[i].type; - if (masks[i].type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) { - memset(&encap_conf, 0x00, sizeof(encap_conf)); - encap_conf.size = ((const struct rte_flow_action_raw_encap *) - (actions[i].conf))->size; - masks[i].conf = &encap_conf; - } - if (masks[i].type == RTE_FLOW_ACTION_TYPE_MODIFY_FIELD) { - const struct rte_flow_action_modify_field *conf = actions[i].conf; - memset(&mh_conf, 0xff, sizeof(mh_conf[i])); - mh_conf[i].operation = conf->operation; - mh_conf[i].dst.field = conf->dst.field; - mh_conf[i].src.field = conf->src.field; - masks[i].conf = &mh_conf[i]; - } - } while (masks[i].type != RTE_FLOW_ACTION_TYPE_END); RTE_SET_USED(action_flags); + memset(masks, 0, sizeof(masks)); + memset(mask_conf, 0, sizeof(mask_conf)); + flow_nta_build_template_mask(actions, masks, mask_conf); /* The group in the attribute translation was done in advance. */ ret = __translate_group(dev, attr, external, attr->group, &src_group, error); if (ret) -- 2.21.0