From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A36841F50; Sun, 9 Jun 2024 10:57:42 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 16B9640669; Sun, 9 Jun 2024 10:56:54 +0200 (CEST) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2075.outbound.protection.outlook.com [40.107.243.75]) by mails.dpdk.org (Postfix) with ESMTP id 95C2740B8F for ; Sun, 9 Jun 2024 10:56:52 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LVPip0lVn+8TQRMcKT8oiUm3F7u6NIte9etFwWRXoWjLLDlrPxnsnDMXIfBaCCYz30DnDhNVWWQEINOHvvNQhkUJPy9xwaymOrCLMmEepaFu9wozoiLDoXxL7AN/VRSH10ojG0hs47MTwaOagV0CQQlI0Wdj7qlG/9i1jlFl7nRi0pRhIXCrQYEs/6QVmn4UhO2n+UkqnXfF7fQFL+qZXnIBupOdkjm1f+TiS2XXkJppUEJevf6zD8zeuKbRuhBgk2Pr1/ZP4qYuXgCOjlnTpP7Eh8I9XAitJTCRoLDHagg3I3URE9Id5c9/OfyJ0ple8KJb6q4Wmhc+mPySkNTdyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7CIh1AAva7J3hdK3IrwbqcWZ2LXVfZkGRcgELF32S38=; b=HpJuwI1IhwuoxfDX0WfMllCQr0DAUVCG6u8NnzXuQULP5oVoC+H1kkcfSEJGVYEM3y5HmUpJJb1P8ebGwlnyj+2a54EbuoSkf1zvg0QdAmYxO/JDtLAtbg395sI92ogHQvavLEL4T+0poLftAGRkh+hTYpLSvlyXkRXJbO2klX5DhA27/3nWZQ/QeV/ZXgW9SARJTg5+AAwvZ/3lgvt8roXFxot9CZvX0xo3SbNU2+eZppjr3/uhoRAXjVpnll82SPIDn+0EX4vxYIkQBF1nC8tOCFl/vTLYKIgbaGkHZV+2hq2yYR/s+fzgzzEB5Csfc+4iw4FRH8+ZnYJg+5smXQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7CIh1AAva7J3hdK3IrwbqcWZ2LXVfZkGRcgELF32S38=; b=So3YBNTgdZG26pLyFhdMgrrPSmSwIab1N+rHSKlacHQ0pbtI1+bLwe6P/M0z5qLKihjY2DW+oDm0jnuCIuZtCWxU/8/uYyEHyk2yuo1TCHBluzfyJ/VFGksMvKc1ra7tTe9ppZICtCMuGVH4UhefjO+0vwnL7snbOPd9kE6f9Y1c57bF2V3mBBqE6E02t4GoWTLo7PZhUpSiORErS2uYA487PL+yEIgHDXbhxH9apW1KL4iFR+rDIjwdfSvXBlN1KKRTZXlr0EhEiIu5tXetZrMtwAaeCPJgUsQasujbBOjRJylnKQx1MHnJCuf77jIAKok1J/5tk8+6XzRVbhlzoA== Received: from CH5PR03CA0023.namprd03.prod.outlook.com (2603:10b6:610:1f1::21) by DM4PR12MB7648.namprd12.prod.outlook.com (2603:10b6:8:104::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.36; Sun, 9 Jun 2024 08:56:50 +0000 Received: from CH3PEPF0000000F.namprd04.prod.outlook.com (2603:10b6:610:1f1:cafe::48) by CH5PR03CA0023.outlook.office365.com (2603:10b6:610:1f1::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7656.23 via Frontend Transport; Sun, 9 Jun 2024 08:56:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CH3PEPF0000000F.mail.protection.outlook.com (10.167.244.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.15 via Frontend Transport; Sun, 9 Jun 2024 08:56:50 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sun, 9 Jun 2024 01:56:43 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sun, 9 Jun 2024 01:56:43 -0700 Received: from nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4 via Frontend Transport; Sun, 9 Jun 2024 01:56:40 -0700 From: Maayan Kashani To: CC: , , , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad Subject: [PATCH v6 10/11] net/mlx5: use non const max number for ASO actions Date: Sun, 9 Jun 2024 11:55:59 +0300 Message-ID: <20240609085600.87274-10-mkashani@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20240609085600.87274-1-mkashani@nvidia.com> References: <20240606123256.177947-1-mkashani@nvidia.com> <20240609085600.87274-1-mkashani@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000F:EE_|DM4PR12MB7648:EE_ X-MS-Office365-Filtering-Correlation-Id: abf951b9-7260-41a9-b72b-08dc88621a01 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|376005|36860700004|1800799015|82310400017; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?aLs/br5oXIZtUuuNAh/fh4oA1yz1NA8wZx8DyCRyHTCRiTbF2xpCgAeyagv+?= =?us-ascii?Q?VsnmdCsSxvZ4OTwRYztaOWP+ggTX4Kn0qQbtnZBK7TrwC6GcYUtRlGueea44?= =?us-ascii?Q?56BHVgVzg5QLbUcG9UJdfbVueOu1N+if6jsYWGs3a8uG1WpFHeDTtJ/I/bPz?= =?us-ascii?Q?LHYVZeROEPpLc6akrSjHZpeo99vcwrMB1kFZmifcykQEfEvwxZisdZ4mMCk8?= =?us-ascii?Q?b5QTVJEYqdySwGFnz9WONv8TFSISknfCUZ/XlB0Dd0VO3GtsDD6qIabUycf8?= =?us-ascii?Q?3l4xgp+T0sgO6A4dfKbAFHjo4tjpeQ/N/tKUrUy39yV9FgUd41Ek+YKtV2Wl?= =?us-ascii?Q?w6ArvENT7mkVT4/lvykgeRSLIrUj8uz2h1K8/bTuFI9a7SlVQD2F8e4mdRhk?= =?us-ascii?Q?ryXOKsrA0afNTU4S8eQJFsjlQNOolFlGVkYVm2luFSkbLhOaHNii3+wtxeTx?= =?us-ascii?Q?b+Tyr3zEU27InoXR6VULXMckmNGgHjkFGub+wY6iuc2XaCY/OjLfl9npG+L0?= =?us-ascii?Q?9hstWVxIcRmi5353KiRzfhxLUizKOwV0vn3jPkn3yLUxN9AURaNCzHIuXKjq?= =?us-ascii?Q?sZbN3wEFSlXx0PhLJDlQTXEwGAA/NoJiF6FI7QTmcPY2vlA0EfmX4QQc63KR?= =?us-ascii?Q?Xu1wZNZvNCaPx5lCTc99Nf2QUXCfxxvFwFFn8EQgr0RDYqT/MCcKK5Gddj0H?= =?us-ascii?Q?tYG3YyVIlLCzKR81uwtjieX01aAfDuSOkZXKodyrUtQAjHu4/SlQbTx9pf/h?= =?us-ascii?Q?YxNTLRt0e8zpsCCz+YSgB8FfoE1+pBYpd/db7DGQKt9/ad5rDqYa4crUJJ5k?= =?us-ascii?Q?7ZSKn/lapxLjF7jNHOk4RVSS6s685T/0wnogAlQRWh9OYJNcYvW2CeR/6umW?= =?us-ascii?Q?kXEpuZRjE2fMu8RALsMOfdedlTUGAnP9vpmo9AymTE2BAQjMOViJW2DfWAys?= =?us-ascii?Q?pz1+KrZJw6MVB7PnT+UCMsTXiKWVT1Hu87BfN2poQyr+qDo/tQ15sLu1Z/q6?= =?us-ascii?Q?/bnsUd0X6Sy3zpC1OtmEpzuLWCD3nK83xCnNcFzNvm4HFSFwxz+3ab8nT6P9?= =?us-ascii?Q?0ECMBRSJGg2ZZtKT3DzE/pnpVPFvivlkiEMO5XyCv3GkrLHcqmxHV8uoGSjE?= =?us-ascii?Q?wNw6rS5D7vRS78J6YDp8qDf0uSL8g/N0DgdsDruADHdEIsLfrIqjRrdN7t2+?= =?us-ascii?Q?OdUiRKexYHeNTRHJ6oLdhlGjMhsFFAHyG4PsKE+11bi416dphnj2NAr+tuwZ?= =?us-ascii?Q?vVFVRddriSA99cOGD7Fe/28ck11nlC7qFgN3IWmEnyT8X060M9hV2FaqE1TT?= =?us-ascii?Q?H1S1mNR6rbdngPtrgOrEajkBcioGqcWo5tiind7y/gaeQhx970hWYb9LIBql?= =?us-ascii?Q?CUCuD+uWpHz9L3dJdE6mLC2+B7s66naBGRZ6aOVn9JK0NfL6ag=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230031)(376005)(36860700004)(1800799015)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2024 08:56:50.2697 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abf951b9-7260-41a9-b72b-08dc88621a01 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7648 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For ASO max allocations in non-template mode, Read FW capabilities instead of using consts. Signed-off-by: Maayan Kashani Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5.h | 17 ++++++++++++----- drivers/net/mlx5/mlx5_flow_hw.c | 13 +++++++++---- drivers/net/mlx5/mlx5_flow_meter.c | 25 +++++++++++++++++++++---- 3 files changed, 42 insertions(+), 13 deletions(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 5789cc6ef17..159ea10018e 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -812,12 +812,18 @@ struct mlx5_dev_shared_port { /* Only yellow color valid. */ #define MLX5_MTR_POLICY_MODE_OY 3 +/* Max number of meters. */ +#define MLX5_MTR_MAX(priv) (mlx5_flow_mtr_max_get(priv)) /* Max number of meters allocated in non template mode. */ -#define MLX5_MTR_NT_MAX (1 << 23) -/* Max number of connection tracking allocated in non template mode */ -#define MLX5_CT_NT_MAX (1 << 23) -/* Max number of counters allocated in non template mode */ -#define MLX5_CNT_MAX (1 << 23) +#define MLX5_MTR_NT_MAX(priv) (MLX5_MTR_MAX(priv) >> 1) +/* Max number of connection tracking. */ +#define MLX5_CT_MAX(priv) (1 << (priv)->sh->cdev->config.hca_attr.log_max_conn_track_offload) +/* Max number of connection tracking allocated in non template mode. */ +#define MLX5_CT_NT_MAX(priv) (MLX5_CT_MAX(priv) >> 1) +/* Max number of counters. */ +#define MLX5_CNT_MAX(priv) ((priv)->sh->hws_max_nb_counters) +/* Max number of counters allocated in non template mode. */ +#define MLX5_CNT_NT_MAX(priv) (MLX5_CNT_MAX(priv) >> 1) enum mlx5_meter_domain { MLX5_MTR_DOMAIN_INGRESS, @@ -2457,6 +2463,7 @@ mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev, int mlx5_flow_meter_flush(struct rte_eth_dev *dev, struct rte_mtr_error *error); void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev); +uint32_t mlx5_flow_mtr_max_get(struct mlx5_priv *priv); /* mlx5_os.c */ diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index f326ca0a21c..b4b0de417a8 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -13114,6 +13114,7 @@ static int flow_hw_ensure_action_pools_allocated(struct rte_eth_dev *dev, bool actions_end = false; struct mlx5_priv *priv = dev->data->dev_private; int ret; + uint obj_num; for (; !actions_end; actions++) { switch ((int)actions->type) { @@ -13122,7 +13123,8 @@ static int flow_hw_ensure_action_pools_allocated(struct rte_eth_dev *dev, if (!priv->hws_age_req) { /* If no counters were previously allocated. */ if (!priv->hws_cpool) { - ret = mlx5_hws_cnt_pool_create(dev, MLX5_CNT_MAX, + obj_num = MLX5_CNT_NT_MAX(priv); + ret = mlx5_hws_cnt_pool_create(dev, obj_num, priv->nb_queue, NULL); if (ret) goto err; @@ -13140,7 +13142,8 @@ static int flow_hw_ensure_action_pools_allocated(struct rte_eth_dev *dev, case RTE_FLOW_ACTION_TYPE_COUNT: /* If no counters were previously allocated. */ if (!priv->hws_cpool) { - ret = mlx5_hws_cnt_pool_create(dev, MLX5_CNT_MAX, + obj_num = MLX5_CNT_NT_MAX(priv); + ret = mlx5_hws_cnt_pool_create(dev, obj_num, priv->nb_queue, NULL); if (ret) goto err; @@ -13149,7 +13152,8 @@ static int flow_hw_ensure_action_pools_allocated(struct rte_eth_dev *dev, case RTE_FLOW_ACTION_TYPE_CONNTRACK: /* If no CT were previously allocated. */ if (!priv->hws_ctpool) { - ret = mlx5_flow_ct_init(dev, MLX5_CT_NT_MAX, priv->nb_queue); + obj_num = MLX5_CT_NT_MAX(priv); + ret = mlx5_flow_ct_init(dev, obj_num, priv->nb_queue); if (ret) goto err; } @@ -13157,7 +13161,8 @@ static int flow_hw_ensure_action_pools_allocated(struct rte_eth_dev *dev, case RTE_FLOW_ACTION_TYPE_METER_MARK: /* If no meters were previously allocated. */ if (!priv->hws_mpool) { - ret = mlx5_flow_meter_init(dev, MLX5_MTR_NT_MAX, 0, 0, + obj_num = MLX5_MTR_NT_MAX(priv); + ret = mlx5_flow_meter_init(dev, obj_num, 0, 0, priv->nb_queue); if (ret) goto err; diff --git a/drivers/net/mlx5/mlx5_flow_meter.c b/drivers/net/mlx5/mlx5_flow_meter.c index da3289b2189..19d86070707 100644 --- a/drivers/net/mlx5/mlx5_flow_meter.c +++ b/drivers/net/mlx5/mlx5_flow_meter.c @@ -704,6 +704,26 @@ mlx5_flow_meter_param_fill(struct mlx5_flow_meter_profile *fmp, return 0; } +/** + * Callback to get MTR maximum objects number. + * + * @param[in] priv + * Pointer to Ethernet device. + * + * @return + * Max number of meters. + */ +uint32_t +mlx5_flow_mtr_max_get(struct mlx5_priv *priv) +{ + struct mlx5_hca_qos_attr *qattr = &priv->sh->cdev->config.hca_attr.qos; + + /* Max number of meters. */ + return ((priv->sh->meter_aso_en) ? + 1 << (qattr->log_max_num_meter_aso + 1) : + qattr->log_max_flow_meter); +} + /** * Callback to get MTR capabilities. * @@ -730,14 +750,11 @@ mlx5_flow_mtr_cap_get(struct rte_eth_dev *dev, RTE_MTR_ERROR_TYPE_UNSPECIFIED, NULL, "Meter is not supported"); memset(cap, 0, sizeof(*cap)); + cap->n_max = mlx5_flow_mtr_max_get(priv); if (priv->sh->meter_aso_en) { - /* 2 meters per one ASO cache line. */ - cap->n_max = 1 << (qattr->log_max_num_meter_aso + 1); cap->srtcm_rfc2697_packet_mode_supported = 1; cap->trtcm_rfc2698_packet_mode_supported = 1; cap->trtcm_rfc4115_packet_mode_supported = 1; - } else { - cap->n_max = 1 << qattr->log_max_flow_meter; } cap->srtcm_rfc2697_byte_mode_supported = 1; cap->trtcm_rfc2698_byte_mode_supported = 1; -- 2.21.0