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Mon, 10 Jun 2024 01:51:00 -0700 From: Maayan Kashani To: CC: , , , Gregory Etelson , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad Subject: [PATCH v5 3/6] net/mlx5: support indirect actions in non-template setup Date: Mon, 10 Jun 2024 11:50:36 +0300 Message-ID: <20240610085039.146356-3-mkashani@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20240610085039.146356-1-mkashani@nvidia.com> References: <20240606101214.172057-1-mkashani@nvidia.com> <20240610085039.146356-1-mkashani@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FD:EE_|CY5PR12MB6060:EE_ X-MS-Office365-Filtering-Correlation-Id: bad2beb5-f76f-4941-c732-08dc892a7bab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|36860700004|376005|1800799015|82310400017; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?BqKnbuHY0lxXa9JJ4qSs9ECPvrnwX7Z1gXgix6TbgqODBlLUQNlUe7k/y2Hs?= =?us-ascii?Q?82bLkbmviI191O7u+xggeAtvJBjhjWLTRImI0YgijseptstBvGE7kfw8VDUG?= =?us-ascii?Q?bdEOeaXVJCpBonjMPe9pJBUH9lEPTyZFZBzpkMCP+GKQTd+2agOHb07aEXp/?= =?us-ascii?Q?sZsZ7qg1eQ9aoaNbhTjttJRZ1p1+7FFUHt2GXvFhfBXLsOkYCCDtPo+WxwD6?= =?us-ascii?Q?4g0Ybinp+BsOIdLSMz3CZ8ETP8ByEBtw6VbmMtYhUHL01XCuH16LtIlL30Um?= =?us-ascii?Q?Z8ittbYvPmmjuZtjBwZUB8kDcVJHLmBv9tw4/0Iid/NRCwSGhu/jBSAfmrVe?= =?us-ascii?Q?sKzuLvt/M8lIS53nG5ehpKpiq6ugQ3jCeHb1UJk6GJdCrdqy4z35hU4n1Bv/?= =?us-ascii?Q?cpN91PL7Xu9QBRh6RgEwRTtuOshzFw2Er+M5I5URXJDr7tvR4uBR3hehg04O?= =?us-ascii?Q?P9IYnClaoXxBYPMf5HdEK2JPtwKxXpXMY0jzBtG/up6qjwNPLhrwOcOfQnYp?= =?us-ascii?Q?HqYh+vTwp4WaVJ8igVExOAu4x9BXJv+TIVeZAnWiPhvaDOlGvZsA+vaHCHHv?= =?us-ascii?Q?IT1tx56Yyxr4cMe7Q/Zc5tuBu9VsawkWiDrAR6rY1czXQYvArCs32g3unTN4?= =?us-ascii?Q?Egz/E6reYjUDScJXHTAN+KfwtLYo3SIU2rcFE4xvIRnbnerSFWKqBx4iTMH9?= =?us-ascii?Q?bpizkjsRdlshuN3tKfI27piH0frbCja9L3nYnuhbS2eHohgYUzJmMnQ0Jj84?= =?us-ascii?Q?HxWxNt+JyK0TfMXadE6vcbAyJ/jKCW2ubDNcrnNRXRcTWIF1Yi8iERRlwjtn?= =?us-ascii?Q?gaN5K/BIIWDLFEGxu7+M0K/6db/QXB13Tj0TNekE7FBSN2XcH42jeJBVaB21?= =?us-ascii?Q?OTcfBZW2Co74MlPbTc6vljcw0KNHOWjnEmZHdBNAC6iUmJRHno3ZIimMxPoC?= =?us-ascii?Q?tUaL9b7B3t2RrbmHBu4fPbHiGVLqMpu77TrsPw/3odvSEO+xvEELStXK8Qws?= =?us-ascii?Q?LWayvnBwxHu0lFgjeKE9LW7E2L3vgB2ewMbZdCto6cUp5/yL6CLIQcnLzJxM?= =?us-ascii?Q?+y934vNhwi5dof9iw7gerWyBUQQxIoL7CHoX3qJO3XRwlRwWRiD95yEBDi0s?= =?us-ascii?Q?yvuhIKCFtUZRNA+sYEfTcCvP0AfMDoKOCrFbLnjgVhsaq+lOB+jT1Xll8l7V?= =?us-ascii?Q?Lq2pbJ65R/WYnDM0qdbifcFoAedFsWhwRnRiAJ6MwqfbO1+kK0iIpYxHwjPv?= =?us-ascii?Q?Om0GuUuZ1rcFFIKukxhQR3cYTelvPU2k2obSsPhWC7uS9jIPJ2HQ2kpf1zld?= =?us-ascii?Q?5pl5fLy354nzNtN8PqaB/9BKGOrID+aVM16oEjtDS/s5xsirql992Rke5AI4?= =?us-ascii?Q?NYE7mKxh9Ckjy8BGhYD/6s141lPf1wlarbLLR9gZC5PL51uDyw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004)(376005)(1800799015)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jun 2024 08:51:13.5629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bad2beb5-f76f-4941-c732-08dc892a7bab X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6060 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Gregory Etelson Add support for the RSS, AGE, COUNT and CONNTRACK indirect flow actions for the non-template flow rules. Signed-off-by: Gregory Etelson Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow_hw.c | 111 +++++++++++++++++++++++++------- 1 file changed, 89 insertions(+), 22 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 19c7f810285..a98e078b498 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -13096,6 +13096,91 @@ flow_hw_encap_decap_resource_register return 0; } +static enum rte_flow_action_type +flow_nta_get_indirect_action_type(const struct rte_flow_action *action) +{ + switch (MLX5_INDIRECT_ACTION_TYPE_GET(action->conf)) { + case MLX5_INDIRECT_ACTION_TYPE_RSS: + return RTE_FLOW_ACTION_TYPE_RSS; + case MLX5_INDIRECT_ACTION_TYPE_AGE: + return RTE_FLOW_ACTION_TYPE_AGE; + case MLX5_INDIRECT_ACTION_TYPE_COUNT: + return RTE_FLOW_ACTION_TYPE_COUNT; + case MLX5_INDIRECT_ACTION_TYPE_CT: + return RTE_FLOW_ACTION_TYPE_CONNTRACK; + default: + break; + } + return RTE_FLOW_ACTION_TYPE_END; +} + +static void +flow_nta_set_mh_mask_conf(const struct rte_flow_action_modify_field *action_conf, + struct rte_flow_action_modify_field *mask_conf) +{ + memset(mask_conf, 0xff, sizeof(*mask_conf)); + mask_conf->operation = action_conf->operation; + mask_conf->dst.field = action_conf->dst.field; + mask_conf->src.field = action_conf->src.field; +} + +union actions_conf { + struct rte_flow_action_modify_field modify_field; + struct rte_flow_action_raw_encap raw_encap; + struct rte_flow_action_vxlan_encap vxlan_encap; + struct rte_flow_action_nvgre_encap nvgre_encap; +}; + +static int +flow_nta_build_template_mask(const struct rte_flow_action actions[], + struct rte_flow_action masks[MLX5_HW_MAX_ACTS], + union actions_conf mask_conf[MLX5_HW_MAX_ACTS]) +{ + int i; + + for (i = 0; i == 0 || actions[i - 1].type != RTE_FLOW_ACTION_TYPE_END; i++) { + const struct rte_flow_action *action = &actions[i]; + struct rte_flow_action *mask = &masks[i]; + union actions_conf *conf = &mask_conf[i]; + + mask->type = action->type; + switch (action->type) { + case RTE_FLOW_ACTION_TYPE_INDIRECT: + mask->type = flow_nta_get_indirect_action_type(action); + if (!mask->type) + return -EINVAL; + break; + case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: + flow_nta_set_mh_mask_conf(action->conf, (void *)conf); + mask->conf = conf; + break; + case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: + /* This mask will set this action as shared. */ + memset(conf, 0xff, sizeof(struct rte_flow_action_raw_encap)); + mask->conf = conf; + break; + case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: + /* This mask will set this action as shared. */ + conf->vxlan_encap.definition = + ((const struct rte_flow_action_vxlan_encap *) + action->conf)->definition; + mask->conf = conf; + break; + case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: + /* This mask will set this action as shared. */ + conf->nvgre_encap.definition = + ((const struct rte_flow_action_nvgre_encap *) + action->conf)->definition; + mask->conf = conf; + break; + default: + break; + } + } + return 0; +#undef NTA_CHECK_CONF_BUF_SIZE +} + static int flow_hw_translate_flow_actions(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, @@ -13119,30 +13204,12 @@ flow_hw_translate_flow_actions(struct rte_eth_dev *dev, .transfer = attr->transfer, }; struct rte_flow_action masks[MLX5_HW_MAX_ACTS]; - struct rte_flow_action_raw_encap encap_conf; - struct rte_flow_action_modify_field mh_conf[MLX5_HW_MAX_ACTS]; + union actions_conf mask_conf[MLX5_HW_MAX_ACTS]; - memset(&masks, 0, sizeof(masks)); - int i = -1; - do { - i++; - masks[i].type = actions[i].type; - if (masks[i].type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) { - memset(&encap_conf, 0x00, sizeof(encap_conf)); - encap_conf.size = ((const struct rte_flow_action_raw_encap *) - (actions[i].conf))->size; - masks[i].conf = &encap_conf; - } - if (masks[i].type == RTE_FLOW_ACTION_TYPE_MODIFY_FIELD) { - const struct rte_flow_action_modify_field *conf = actions[i].conf; - memset(&mh_conf, 0xff, sizeof(mh_conf[i])); - mh_conf[i].operation = conf->operation; - mh_conf[i].dst.field = conf->dst.field; - mh_conf[i].src.field = conf->src.field; - masks[i].conf = &mh_conf[i]; - } - } while (masks[i].type != RTE_FLOW_ACTION_TYPE_END); RTE_SET_USED(action_flags); + memset(masks, 0, sizeof(masks)); + memset(mask_conf, 0, sizeof(mask_conf)); + flow_nta_build_template_mask(actions, masks, mask_conf); /* The group in the attribute translation was done in advance. */ ret = __translate_group(dev, attr, external, attr->group, &src_group, error); if (ret) -- 2.21.0