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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1PEPF000075ED.mail.protection.outlook.com (10.167.249.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.15 via Frontend Transport; Mon, 24 Jun 2024 05:11:32 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sun, 23 Jun 2024 22:11:17 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sun, 23 Jun 2024 22:11:14 -0700 From: Gregory Etelson To: CC: , , , Dariusz Sosnowski , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad Subject: [PATCH] net/mlx5: fix HWS GRE OPTION item validation Date: Mon, 24 Jun 2024 08:11:00 +0300 Message-ID: <20240624051100.42212-1-getelson@nvidia.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075ED:EE_|CH3PR12MB7738:EE_ X-MS-Office365-Filtering-Correlation-Id: 5eb08c07-a7f1-4fe4-c15d-08dc940c1cee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230037)(376011)(1800799021)(36860700010)(82310400023); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 05:11:32.4132 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5eb08c07-a7f1-4fe4-c15d-08dc940c1cee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075ED.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7738 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 1. GRE_OPTION flow item validation required both item spec and mask. HWS pattern template provides item mask only. The patch removes spec requirement in HWS GRE_OPTION item validation. 2. In non-HWS setup, GRE_OPTION flow item validation for the checksum and sequence item parameters require group value. HWS pattern template does not have a group. The patch removes group validations for GRE_OPTION item. Fixes: 113feae56db6 ("net/mlx5: validate HWS template items") Signed-off-by: Gregory Etelson Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 7bcbbc74b5..5e4e45eb3e 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -3388,7 +3388,7 @@ mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, "GRE option following a wrong item"); - if (!spec || !mask) + if ((!spec && !mlx5_hws_active(dev)) || !mask) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, item, "At least one field gre_option(checksum/key/sequence) must be specified"); @@ -3414,18 +3414,21 @@ mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, RTE_FLOW_ERROR_TYPE_ITEM, item, "Sequence bit must be on"); - if (mask->checksum_rsvd.checksum || mask->sequence.sequence) { - if (priv->sh->steering_format_version == - MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || - ((attr->group || (attr->transfer && priv->fdb_def_rule)) && - !priv->sh->misc5_cap) || - (!(priv->sh->tunnel_header_0_1 && - priv->sh->tunnel_header_2_3) && - !attr->group && (!attr->transfer || !priv->fdb_def_rule))) - return rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ITEM, - item, - "Checksum/Sequence not supported"); + if (!mlx5_hws_active(dev)) { + if (mask->checksum_rsvd.checksum || mask->sequence.sequence) { + if (priv->sh->steering_format_version == + MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || + ((attr->group || + (attr->transfer && priv->fdb_def_rule)) && + !priv->sh->misc5_cap) || + (!(priv->sh->tunnel_header_0_1 && + priv->sh->tunnel_header_2_3) && + !attr->group && + (!attr->transfer || !priv->fdb_def_rule))) + return rte_flow_error_set + (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, + item, "Checksum/Sequence not supported"); + } } ret = mlx5_flow_item_acceptable (dev, item, (const uint8_t *)mask, -- 2.43.0