[PATCH v5 11/23] net/ntnic: add FPGA initialization functionality

[Serhii Iliushyk <sil-plv@napatech.com>]

Enable FPGA initialization

Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
v5
* Fix Typo/Spelling
---
 drivers/net/ntnic/adapter/nt4ga_adapter.c     |  52 +++-
 drivers/net/ntnic/meson.build                 |   7 +
 .../net/ntnic/nthw/core/include/nthw_core.h   |   4 +
 .../net/ntnic/nthw/core/include/nthw_fpga.h   |  22 ++
 drivers/net/ntnic/nthw/core/nthw_fpga.c       | 222 ++++++++++++++++++
 drivers/net/ntnic/nthw/nthw_drv.h             |   1 +
 drivers/net/ntnic/nthw/nthw_register.h        |   1 +
 drivers/net/ntnic/ntnic_ethdev.c              |  39 ++-
 drivers/net/ntnic/ntnic_mod_reg.h             |   1 +
 9 files changed, 345 insertions(+), 4 deletions(-)
 create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_fpga.h
 create mode 100644 drivers/net/ntnic/nthw/core/nthw_fpga.c

diff --git a/drivers/net/ntnic/adapter/nt4ga_adapter.c b/drivers/net/ntnic/adapter/nt4ga_adapter.c
index 7cc3841ecf..99083dd2dd 100644
--- a/drivers/net/ntnic/adapter/nt4ga_adapter.c
+++ b/drivers/net/ntnic/adapter/nt4ga_adapter.c
@@ -6,7 +6,7 @@
 #include <rte_thread.h>
 
 #include "ntlog.h"
-#include "nt_util.h"
+#include "nthw_fpga.h"
 #include "ntnic_mod_reg.h"
 
 static int nt4ga_adapter_show_info(struct adapter_info_s *p_adapter_info, FILE *pfh)
@@ -15,6 +15,7 @@ static int nt4ga_adapter_show_info(struct adapter_info_s *p_adapter_info, FILE *
 	const char *const p_adapter_id_str = p_adapter_info->mp_adapter_id_str;
 	fpga_info_t *p_fpga_info = &p_adapter_info->fpga_info;
 	hw_info_t *p_hw_info = &p_adapter_info->hw_info;
+	mcu_info_t *mcu_info = &p_adapter_info->fpga_info.mcu_info;
 	char a_pci_ident_str[32];
 
 	snprintf(a_pci_ident_str, sizeof(a_pci_ident_str), PCIIDENT_PRINT_STR,
@@ -37,7 +38,8 @@ static int nt4ga_adapter_show_info(struct adapter_info_s *p_adapter_info, FILE *
 	fprintf(pfh, "%s: Hw=0x%02X_rev%d: %s\n", p_adapter_id_str, p_hw_info->hw_platform_id,
 		p_fpga_info->nthw_hw_info.hw_id, p_fpga_info->nthw_hw_info.hw_plat_id_str);
 	fprintf(pfh, "%s: MCU Details:\n", p_adapter_id_str);
-
+	fprintf(pfh, "%s: HasMcu=%d McuType=%d McuDramSize=%d\n", p_adapter_id_str,
+		mcu_info->mb_has_mcu, mcu_info->mn_mcu_type, mcu_info->mn_mcu_dram_size);
 
 	return 0;
 }
@@ -49,6 +51,13 @@ static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info)
 	fpga_info_t *fpga_info = &p_adapter_info->fpga_info;
 	hw_info_t *p_hw_info = &p_adapter_info->hw_info;
 
+	/*
+	 * IMPORTANT: Most variables cannot be determined before nthw fpga model is instantiated
+	 * (nthw_fpga_init())
+	 */
+	int n_phy_ports = -1;
+	int res = -1;
+	nthw_fpga_t *p_fpga = NULL;
 
 	p_hw_info->n_nthw_adapter_id = nthw_platform_get_nthw_adapter_id(p_hw_info->pci_device_id);
 
@@ -102,6 +111,39 @@ static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info)
 		}
 	}
 
+	res = nthw_fpga_init(&p_adapter_info->fpga_info);
+
+	if (res) {
+		NT_LOG_DBGX(ERR, NTNIC, "%s: %s: FPGA=%04d res=x%08X\n", p_adapter_id_str,
+			p_dev_name, fpga_info->n_fpga_prod_id, res);
+		return res;
+	}
+
+	assert(fpga_info);
+	p_fpga = fpga_info->mp_fpga;
+	assert(p_fpga);
+	n_phy_ports = fpga_info->n_phy_ports;
+	assert(n_phy_ports >= 1);
+
+	{
+		assert(fpga_info->n_fpga_prod_id > 0);
+
+		switch (fpga_info->n_fpga_prod_id) {
+		default:
+			NT_LOG(ERR, NTNIC, "Unsupported FPGA product: %04d\n",
+				fpga_info->n_fpga_prod_id);
+			res = -1;
+			break;
+		}
+
+		if (res) {
+			NT_LOG_DBGX(ERR, NTNIC, "%s: %s: FPGA=%04d res=x%08X\n",
+				p_adapter_id_str, p_dev_name,
+				fpga_info->n_fpga_prod_id, res);
+			return res;
+		}
+	}
+
 	return 0;
 }
 
@@ -109,8 +151,12 @@ static int nt4ga_adapter_deinit(struct adapter_info_s *p_adapter_info)
 {
 	fpga_info_t *fpga_info = &p_adapter_info->fpga_info;
 	int i;
-	int res = -1;
+	int res;
+
+	nthw_fpga_shutdown(&p_adapter_info->fpga_info);
 
+	/* Rac rab reset flip flop */
+	res = nthw_rac_rab_reset(fpga_info->mp_nthw_rac);
 
 	/* Free adapter port ident strings */
 	for (i = 0; i < fpga_info->n_phy_ports; i++) {
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index aa839f4de3..fced38e41a 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -21,6 +21,7 @@ includes = [
     include_directories('nthw/core/include'),
     include_directories('nthw'),
     include_directories('nthw/supported'),
+    include_directories('nthw/model'),
 ]
 
 # all sources
@@ -29,7 +30,13 @@ sources = files(
     'nthw/supported/nthw_fpga_9563_055_039_0000.c',
     'nthw/supported/nthw_fpga_instances.c',
     'nthw/supported/nthw_fpga_mod_str_map.c',
+    'nthw/core/nthw_fpga.c',
+    'nthw/core/nthw_hif.c',
+    'nthw/core/nthw_iic.c',
+    'nthw/core/nthw_pcie3.c',
+    'nthw/model/nthw_fpga_model.c',
     'nthw/nthw_platform.c',
+    'nthw/nthw_rac.c',
     'ntlog/ntlog.c',
     'ntutil/nt_util.c',
     'ntnic_mod_reg.c',
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_core.h b/drivers/net/ntnic/nthw/core/include/nthw_core.h
index c2602e396f..69af113816 100644
--- a/drivers/net/ntnic/nthw/core/include/nthw_core.h
+++ b/drivers/net/ntnic/nthw/core/include/nthw_core.h
@@ -11,6 +11,10 @@
 #include <stdint.h>
 
 #include "nthw_platform_drv.h"
+#include "nthw_fpga_model.h"
+#include "nthw_hif.h"
+#include "nthw_pcie3.h"
+#include "nthw_iic.h"
 
 
 #endif	/* __NTHW_CORE_H__ */
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_fpga.h b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h
new file mode 100644
index 0000000000..1943f6e225
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h
@@ -0,0 +1,22 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __NTHW_FPGA_H__
+#define __NTHW_FPGA_H__
+
+#include "nthw_drv.h"
+
+#include "nthw_fpga_model.h"
+
+#include "nthw_rac.h"
+#include "nthw_iic.h"
+
+int nthw_fpga_init(struct fpga_info_s *p_fpga_info);
+int nthw_fpga_shutdown(struct fpga_info_s *p_fpga_info);
+
+int nthw_fpga_get_param_info(struct fpga_info_s *p_fpga_info, nthw_fpga_t *p_fpga);
+
+
+#endif	/* __NTHW_FPGA_H__ */
diff --git a/drivers/net/ntnic/nthw/core/nthw_fpga.c b/drivers/net/ntnic/nthw/core/nthw_fpga.c
new file mode 100644
index 0000000000..df238ec4ef
--- /dev/null
+++ b/drivers/net/ntnic/nthw/core/nthw_fpga.c
@@ -0,0 +1,222 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "nthw_fpga.h"
+
+#include "nthw_fpga_instances.h"
+#include "nthw_fpga_mod_str_map.h"
+
+#include <arpa/inet.h>
+
+int nthw_fpga_get_param_info(struct fpga_info_s *p_fpga_info, nthw_fpga_t *p_fpga)
+{
+	mcu_info_t *p_mcu_info = &p_fpga_info->mcu_info;
+
+	const int n_phy_ports = nthw_fpga_get_product_param(p_fpga, NT_PHY_PORTS, -1);
+	const int n_phy_quads = nthw_fpga_get_product_param(p_fpga, NT_PHY_QUADS, -1);
+	const int n_rx_ports = nthw_fpga_get_product_param(p_fpga, NT_RX_PORTS, -1);
+	const int n_tx_ports = nthw_fpga_get_product_param(p_fpga, NT_TX_PORTS, -1);
+	const int n_vf_offset = nthw_fpga_get_product_param(p_fpga, NT_HIF_VF_OFFSET, 4);
+
+	p_fpga_info->n_phy_ports = n_phy_ports;
+	p_fpga_info->n_phy_quads = n_phy_quads;
+	p_fpga_info->n_rx_ports = n_rx_ports;
+	p_fpga_info->n_tx_ports = n_tx_ports;
+	p_fpga_info->n_vf_offset = n_vf_offset;
+	p_fpga_info->profile = FPGA_INFO_PROFILE_UNKNOWN;
+
+	/* Check for MCU */
+	if (nthw_fpga_get_product_param(p_fpga, NT_MCU_PRESENT, 0) != 0) {
+		p_mcu_info->mb_has_mcu = true;
+		/* Check MCU Type */
+		p_mcu_info->mn_mcu_type = nthw_fpga_get_product_param(p_fpga, NT_MCU_TYPE, -1);
+		/* MCU DRAM size */
+		p_mcu_info->mn_mcu_dram_size =
+			nthw_fpga_get_product_param(p_fpga, NT_MCU_DRAM_SIZE, -1);
+
+	} else {
+		p_mcu_info->mb_has_mcu = false;
+		p_mcu_info->mn_mcu_type = -1;
+		p_mcu_info->mn_mcu_dram_size = -1;
+	}
+
+	/* Check for VSWITCH FPGA */
+	if (nthw_fpga_get_product_param(p_fpga, NT_NFV_OVS_PRODUCT, 0) != 0) {
+		p_fpga_info->profile = FPGA_INFO_PROFILE_VSWITCH;
+
+	} else if (nthw_fpga_get_product_param(p_fpga, NT_IOA_PRESENT, 0) != 0) {
+		/* Check for VSWITCH FPGA - legacy */
+		p_fpga_info->profile = FPGA_INFO_PROFILE_VSWITCH;
+
+	} else if (nthw_fpga_get_product_param(p_fpga, NT_QM_PRESENT, 0) != 0) {
+		p_fpga_info->profile = FPGA_INFO_PROFILE_CAPTURE;
+
+	} else {
+		p_fpga_info->profile = FPGA_INFO_PROFILE_INLINE;
+	}
+
+	return 0;
+}
+
+int nthw_fpga_init(struct fpga_info_s *p_fpga_info)
+{
+	const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str;
+
+	nthw_hif_t *p_nthw_hif = NULL;
+	nthw_pcie3_t *p_nthw_pcie3 = NULL;
+	nthw_rac_t *p_nthw_rac = NULL;
+
+	mcu_info_t *p_mcu_info = &p_fpga_info->mcu_info;
+	uint64_t n_fpga_ident = 0;
+	nthw_fpga_mgr_t *p_fpga_mgr = NULL;
+	nthw_fpga_t *p_fpga = NULL;
+
+	char s_fpga_prod_ver_rev_str[32] = { 0 };
+
+	int res = 0;
+
+	assert(p_fpga_info);
+
+	{
+		const uint64_t n_fpga_ident = nthw_fpga_read_ident(p_fpga_info);
+		const uint32_t n_fpga_build_time = nthw_fpga_read_buildtime(p_fpga_info);
+		const int n_fpga_type_id = nthw_fpga_extract_type_id(n_fpga_ident);
+		const int n_fpga_prod_id = nthw_fpga_extract_prod_id(n_fpga_ident);
+		const int n_fpga_ver_id = nthw_fpga_extract_ver_id(n_fpga_ident);
+		const int n_fpga_rev_id = nthw_fpga_extract_rev_id(n_fpga_ident);
+
+		p_fpga_info->n_fpga_ident = n_fpga_ident;
+		p_fpga_info->n_fpga_type_id = n_fpga_type_id;
+		p_fpga_info->n_fpga_prod_id = n_fpga_prod_id;
+		p_fpga_info->n_fpga_ver_id = n_fpga_ver_id;
+		p_fpga_info->n_fpga_rev_id = n_fpga_rev_id;
+		p_fpga_info->n_fpga_build_time = n_fpga_build_time;
+
+		snprintf(s_fpga_prod_ver_rev_str, sizeof(s_fpga_prod_ver_rev_str),
+			"%04d-%04d-%02d-%02d", n_fpga_type_id, n_fpga_prod_id, n_fpga_ver_id,
+			n_fpga_rev_id);
+
+		NT_LOG(INF, NTHW, "%s: FPGA %s (%" PRIX64 ") [%08X]\n", p_adapter_id_str,
+			s_fpga_prod_ver_rev_str, n_fpga_ident, n_fpga_build_time);
+	}
+
+	n_fpga_ident = p_fpga_info->n_fpga_ident;
+
+	p_fpga_mgr = nthw_fpga_mgr_new();
+	nthw_fpga_mgr_init(p_fpga_mgr, nthw_fpga_instances,
+		(const void *)sa_nthw_fpga_mod_str_map);
+	nthw_fpga_mgr_log_dump(p_fpga_mgr);
+	p_fpga = nthw_fpga_mgr_query_fpga(p_fpga_mgr, n_fpga_ident, p_fpga_info);
+	p_fpga_info->mp_fpga = p_fpga;
+
+	if (p_fpga == NULL) {
+		NT_LOG(ERR, NTHW, "%s: Unsupported FPGA: %s (%08X)\n", p_adapter_id_str,
+			s_fpga_prod_ver_rev_str, p_fpga_info->n_fpga_build_time);
+		return -1;
+	}
+
+	if (p_fpga_mgr) {
+		nthw_fpga_mgr_delete(p_fpga_mgr);
+		p_fpga_mgr = NULL;
+	}
+
+	/* Read Fpga param info */
+	nthw_fpga_get_param_info(p_fpga_info, p_fpga);
+
+	/* debug: report params */
+	NT_LOG(DBG, NTHW, "%s: NT_PHY_PORTS=%d\n", p_adapter_id_str, p_fpga_info->n_phy_ports);
+	NT_LOG(DBG, NTHW, "%s: NT_PHY_QUADS=%d\n", p_adapter_id_str, p_fpga_info->n_phy_quads);
+	NT_LOG(DBG, NTHW, "%s: NT_RX_PORTS=%d\n", p_adapter_id_str, p_fpga_info->n_rx_ports);
+	NT_LOG(DBG, NTHW, "%s: NT_TX_PORTS=%d\n", p_adapter_id_str, p_fpga_info->n_tx_ports);
+	NT_LOG(DBG, NTHW, "%s: nProfile=%d\n", p_adapter_id_str, (int)p_fpga_info->profile);
+	NT_LOG(DBG, NTHW, "%s: bHasMcu=%d\n", p_adapter_id_str, p_mcu_info->mb_has_mcu);
+	NT_LOG(DBG, NTHW, "%s: McuType=%d\n", p_adapter_id_str, p_mcu_info->mn_mcu_type);
+	NT_LOG(DBG, NTHW, "%s: McuDramSize=%d\n", p_adapter_id_str, p_mcu_info->mn_mcu_dram_size);
+
+	p_nthw_rac = nthw_rac_new();
+
+	if (p_nthw_rac == NULL) {
+		NT_LOG(ERR, NTHW, "%s: Unsupported FPGA: RAC is not found: %s (%08X)\n",
+			p_adapter_id_str, s_fpga_prod_ver_rev_str, p_fpga_info->n_fpga_build_time);
+		return -1;
+	}
+
+	nthw_rac_init(p_nthw_rac, p_fpga, p_fpga_info);
+	nthw_rac_rab_flush(p_nthw_rac);
+	p_fpga_info->mp_nthw_rac = p_nthw_rac;
+
+	switch (p_fpga_info->n_nthw_adapter_id) {
+	default:
+		NT_LOG(ERR, NTHW, "%s: Unsupported HW product id: %d\n", p_adapter_id_str,
+			p_fpga_info->n_nthw_adapter_id);
+		res = -1;
+		break;
+	}
+
+	if (res) {
+		NT_LOG(ERR, NTHW, "%s: status: 0x%08X\n", p_adapter_id_str, res);
+		return res;
+	}
+
+	res = nthw_pcie3_init(NULL, p_fpga, 0);	/* Probe for module */
+
+	if (res == 0) {
+		p_nthw_pcie3 = nthw_pcie3_new();
+
+		if (p_nthw_pcie3) {
+			res = nthw_pcie3_init(p_nthw_pcie3, p_fpga, 0);
+
+			if (res == 0) {
+				NT_LOG(DBG, NTHW, "%s: Pcie3 module found\n", p_adapter_id_str);
+				nthw_pcie3_trigger_sample_time(p_nthw_pcie3);
+
+			} else {
+				nthw_pcie3_delete(p_nthw_pcie3);
+				p_nthw_pcie3 = NULL;
+			}
+		}
+
+		p_fpga_info->mp_nthw_pcie3 = p_nthw_pcie3;
+	}
+
+	if (p_nthw_pcie3 == NULL) {
+		p_nthw_hif = nthw_hif_new();
+
+		if (p_nthw_hif) {
+			res = nthw_hif_init(p_nthw_hif, p_fpga, 0);
+
+			if (res == 0) {
+				NT_LOG(DBG, NTHW, "%s: Hif module found\n", p_adapter_id_str);
+				nthw_hif_trigger_sample_time(p_nthw_hif);
+
+			} else {
+				nthw_hif_delete(p_nthw_hif);
+				p_nthw_hif = NULL;
+			}
+		}
+	}
+
+	p_fpga_info->mp_nthw_hif = p_nthw_hif;
+
+
+	return res;
+}
+
+int nthw_fpga_shutdown(struct fpga_info_s *p_fpga_info)
+{
+	int res = -1;
+
+	if (p_fpga_info) {
+		if (p_fpga_info && p_fpga_info->mp_nthw_rac)
+			res = nthw_rac_rab_reset(p_fpga_info->mp_nthw_rac);
+	}
+
+	return res;
+}
diff --git a/drivers/net/ntnic/nthw/nthw_drv.h b/drivers/net/ntnic/nthw/nthw_drv.h
index d7cd64bb1d..071618eb6e 100644
--- a/drivers/net/ntnic/nthw/nthw_drv.h
+++ b/drivers/net/ntnic/nthw/nthw_drv.h
@@ -22,6 +22,7 @@ enum fpga_info_profile {
 };
 
 typedef struct mcu_info_s {
+	bool mb_has_mcu;
 	int mn_mcu_type;
 	int mn_mcu_dram_size;
 } mcu_info_t;
diff --git a/drivers/net/ntnic/nthw/nthw_register.h b/drivers/net/ntnic/nthw/nthw_register.h
index db006fcf72..ecc661a656 100644
--- a/drivers/net/ntnic/nthw/nthw_register.h
+++ b/drivers/net/ntnic/nthw/nthw_register.h
@@ -11,6 +11,7 @@
 #include <stdbool.h>
 #include <inttypes.h>
 
+#include "nthw_fpga_model.h"
 
 #include "fpga_model.h"
 
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index 7acffaebdd..c1961055d5 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -197,12 +197,33 @@ eth_dev_close(struct rte_eth_dev *eth_dev)
 	return 0;
 }
 
+static int
+eth_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, size_t fw_size)
+{
+	struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+
+	fpga_info_t *fpga_info = &internals->p_drv->ntdrv.adapter_info.fpga_info;
+	const int length = snprintf(fw_version, fw_size, "%03d-%04d-%02d-%02d",
+			fpga_info->n_fpga_type_id, fpga_info->n_fpga_prod_id,
+			fpga_info->n_fpga_ver_id, fpga_info->n_fpga_rev_id);
+
+	if ((size_t)length < fw_size) {
+		/* We have space for the version string */
+		return 0;
+
+	} else {
+		/* We do not have space for the version string -return the needed space */
+		return length + 1;
+	}
+}
+
 static struct eth_dev_ops nthw_eth_dev_ops = {
 	.dev_configure = eth_dev_configure,
 	.dev_start = eth_dev_start,
 	.dev_stop = eth_dev_stop,
 	.dev_close = eth_dev_close,
 	.dev_infos_get = eth_dev_infos_get,
+	.fw_version_get = eth_fw_version_get,
 };
 
 static int
@@ -219,6 +240,7 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev)
 
 	struct drv_s *p_drv;
 	ntdrv_4ga_t *p_nt_drv;
+	fpga_info_t *fpga_info;
 	hw_info_t *p_hw_info;
 	(void)p_hw_info;
 	uint32_t n_port_mask = -1;	/* All ports enabled by default */
@@ -252,6 +274,7 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev)
 
 	/* context */
 	p_nt_drv = &p_drv->ntdrv;
+	fpga_info = &p_nt_drv->adapter_info.fpga_info;
 	p_hw_info = &p_nt_drv->adapter_info.hw_info;
 
 	p_drv->p_dev = pci_dev;
@@ -262,6 +285,11 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev)
 	p_nt_drv->adapter_info.n_rx_host_buffers = nb_rx_queues;
 	p_nt_drv->adapter_info.n_tx_host_buffers = nb_tx_queues;
 
+	fpga_info->bar0_addr = (void *)pci_dev->mem_resource[0].addr;
+	fpga_info->bar0_size = pci_dev->mem_resource[0].len;
+	fpga_info->numa_node = pci_dev->device.numa_node;
+	fpga_info->pciident = p_nt_drv->pciident;
+	fpga_info->adapter_no = p_drv->adapter_no;
 
 	p_nt_drv->adapter_info.hw_info.pci_class_id = pci_dev->id.class_id;
 	p_nt_drv->adapter_info.hw_info.pci_vendor_id = pci_dev->id.vendor_id;
@@ -298,6 +326,15 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev)
 		/* mp_adapter_id_str is initialized after nt4ga_adapter_init(p_nt_drv) */
 		const char *const p_adapter_id_str = p_nt_drv->adapter_info.mp_adapter_id_str;
 		(void)p_adapter_id_str;
+		NT_LOG(DBG, NTNIC,
+			"%s: %s: AdapterPCI=" PCIIDENT_PRINT_STR " Hw=0x%02X_rev%d PhyPorts=%d\n",
+			(pci_dev->name[0] ? pci_dev->name : "NA"), p_adapter_id_str,
+			PCIIDENT_TO_DOMAIN(p_nt_drv->adapter_info.fpga_info.pciident),
+			PCIIDENT_TO_BUSNR(p_nt_drv->adapter_info.fpga_info.pciident),
+			PCIIDENT_TO_DEVNR(p_nt_drv->adapter_info.fpga_info.pciident),
+			PCIIDENT_TO_FUNCNR(p_nt_drv->adapter_info.fpga_info.pciident),
+			p_hw_info->hw_platform_id, fpga_info->nthw_hw_info.hw_id,
+			fpga_info->n_phy_ports);
 
 	} else {
 		NT_LOG_DBGX(ERR, NTNIC, "%s: error=%d\n",
@@ -305,7 +342,7 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev)
 		return -1;
 	}
 
-	n_phy_ports = 0;
+	n_phy_ports = fpga_info->n_phy_ports;
 
 	for (int n_intf_no = 0; n_intf_no < n_phy_ports; n_intf_no++) {
 		const char *const p_port_id_str = p_nt_drv->adapter_info.mp_port_id_str[n_intf_no];
diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h
index 48a9f8f7b9..96fc829399 100644
--- a/drivers/net/ntnic/ntnic_mod_reg.h
+++ b/drivers/net/ntnic/ntnic_mod_reg.h
@@ -7,6 +7,7 @@
 #define __NTNIC_MOD_REG_H__
 
 #include <stdint.h>
+#include "nthw_fpga_model.h"
 #include "nthw_platform_drv.h"
 #include "nthw_drv.h"
 #include "nt4ga_adapter.h"
-- 
2.45.0