From: Serhii Iliushyk <sil-plv@napatech.com>
To: dev@dpdk.org
Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com,
andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com
Subject: [PATCH v5 09/23] net/ntnic: add registers and FPGA model for NapaTech NIC
Date: Thu, 27 Jun 2024 09:38:50 +0200 [thread overview]
Message-ID: <20240627073918.2039719-9-sil-plv@napatech.com> (raw)
In-Reply-To: <20240627073918.2039719-1-sil-plv@napatech.com>
The NTNIC PMD does not rely on a kernel space Napatech driver,
thus all defines related to the register layout is part of the PMD
code, which will be added in later commits.
Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
drivers/net/ntnic/include/fpga_model.h | 104 ++
drivers/net/ntnic/meson.build | 4 +
.../net/ntnic/nthw/model/nthw_fpga_model.c | 1194 ++++++++++++++++
.../net/ntnic/nthw/model/nthw_fpga_model.h | 245 ++++
drivers/net/ntnic/nthw/nthw_register.h | 21 +
.../supported/nthw_fpga_9563_055_039_0000.c | 1233 +++++++++++++++++
.../nthw/supported/nthw_fpga_instances.c | 6 +
.../nthw/supported/nthw_fpga_instances.h | 7 +
.../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 36 +
.../nthw/supported/nthw_fpga_mod_str_map.c | 21 +
.../nthw/supported/nthw_fpga_mod_str_map.h | 11 +
.../nthw/supported/nthw_fpga_param_defs.h | 232 ++++
.../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 35 +
.../nthw/supported/nthw_fpga_reg_defs_gfg.h | 126 ++
.../nthw/supported/nthw_fpga_reg_defs_gmf.h | 68 +
.../supported/nthw_fpga_reg_defs_gpio_phy.h | 48 +
.../nthw/supported/nthw_fpga_reg_defs_hif.h | 79 ++
.../nthw/supported/nthw_fpga_reg_defs_i2cm.h | 38 +
.../nthw/supported/nthw_fpga_reg_defs_iic.h | 96 ++
.../supported/nthw_fpga_reg_defs_mac_pcs.h | 298 ++++
.../supported/nthw_fpga_reg_defs_pci_rd_tg.h | 37 +
.../supported/nthw_fpga_reg_defs_pci_wr_tg.h | 40 +
.../nthw/supported/nthw_fpga_reg_defs_pcie3.h | 281 ++++
.../nthw/supported/nthw_fpga_reg_defs_rac.h | 72 +
.../supported/nthw_fpga_reg_defs_rst9563.h | 59 +
.../nthw/supported/nthw_fpga_reg_defs_sdc.h | 44 +
drivers/net/ntnic/ntnic_ethdev.c | 1 +
27 files changed, 4436 insertions(+)
create mode 100644 drivers/net/ntnic/include/fpga_model.h
create mode 100644 drivers/net/ntnic/nthw/model/nthw_fpga_model.c
create mode 100644 drivers/net/ntnic/nthw/model/nthw_fpga_model.h
create mode 100644 drivers/net/ntnic/nthw/nthw_register.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h
create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h
diff --git a/drivers/net/ntnic/include/fpga_model.h b/drivers/net/ntnic/include/fpga_model.h
new file mode 100644
index 0000000000..5eb0170b23
--- /dev/null
+++ b/drivers/net/ntnic/include/fpga_model.h
@@ -0,0 +1,104 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _FPGA_MODEL_H_
+#define _FPGA_MODEL_H_
+
+#include <unistd.h>
+#include <stdint.h>
+#include <inttypes.h>
+
+typedef uint32_t nthw_id_t;
+
+enum nthw_fpga_bus_type {
+ NTHW_FPGA_BUS_TYPE_UNKNOWN =
+ 0, /* Unknown/uninitialized - keep this as the first enum element */
+ NTHW_FPGA_BUS_TYPE_BAR,
+ NTHW_FPGA_BUS_TYPE_PCI,
+ NTHW_FPGA_BUS_TYPE_CCIP,
+ NTHW_FPGA_BUS_TYPE_RAB0,
+ NTHW_FPGA_BUS_TYPE_RAB1,
+ NTHW_FPGA_BUS_TYPE_RAB2,
+ NTHW_FPGA_BUS_TYPE_NMB,
+ NTHW_FPGA_BUS_TYPE_NDM,
+ NTHW_FPGA_BUS_TYPE_SPI0,
+ NTHW_FPGA_BUS_TYPE_SPI = NTHW_FPGA_BUS_TYPE_SPI0,
+};
+
+typedef enum nthw_fpga_bus_type nthw_fpga_bus_type_e;
+
+enum nthw_fpga_register_type {
+ NTHW_FPGA_REG_TYPE_UNKNOWN =
+ 0, /* Unknown/uninitialized - keep this as the first enum element */
+ NTHW_FPGA_REG_TYPE_RW,
+ NTHW_FPGA_REG_TYPE_RO,
+ NTHW_FPGA_REG_TYPE_WO,
+ NTHW_FPGA_REG_TYPE_RC1,
+ NTHW_FPGA_REG_TYPE_MIXED,
+};
+
+typedef enum nthw_fpga_register_type nthw_fpga_register_type_e;
+
+struct nthw_fpga_field_init {
+ nthw_id_t id;
+ uint16_t bw;
+ uint16_t low;
+ uint64_t reset_val;
+};
+
+typedef struct nthw_fpga_field_init nthw_fpga_field_init_s;
+
+struct nthw_fpga_register_init {
+ nthw_id_t id;
+ uint32_t addr_rel;
+ uint16_t bw;
+ nthw_fpga_register_type_e type;
+ uint64_t reset_val;
+ int nb_fields;
+ struct nthw_fpga_field_init *fields;
+};
+
+typedef struct nthw_fpga_register_init nthw_fpga_register_init_s;
+
+struct nthw_fpga_module_init {
+ nthw_id_t id;
+ int instance;
+ nthw_id_t def_id;
+ int major_version;
+ int minor_version;
+ nthw_fpga_bus_type_e bus_id;
+ uint32_t addr_base;
+ int nb_registers;
+ struct nthw_fpga_register_init *registers;
+};
+
+typedef struct nthw_fpga_module_init nthw_fpga_module_init_s;
+
+struct nthw_fpga_prod_param {
+ const nthw_id_t id;
+ const int value;
+};
+
+typedef struct nthw_fpga_prod_param nthw_fpga_prod_param_s;
+
+struct nthw_fpga_prod_init {
+ int fpga_item_id;
+ int fpga_product_id;
+ int fpga_version;
+ int fpga_revision;
+ int fpga_patch_no;
+ int fpga_build_no;
+ uint32_t fpga_build_time;
+ int nb_prod_params;
+ struct nthw_fpga_prod_param *product_params;
+ int nb_modules;
+ struct nthw_fpga_module_init *modules;
+};
+
+typedef struct nthw_fpga_prod_init nthw_fpga_prod_init_s;
+
+#endif /* _FPGA_MODEL_H_ */
+
+/* EOF */
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 316a0e4b20..490a10c442 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -19,11 +19,15 @@ includes = [
include_directories('ntlog/include'),
include_directories('ntutil/include'),
include_directories('nthw'),
+ include_directories('nthw/supported'),
]
# all sources
sources = files(
'adapter/nt4ga_adapter.c',
+ 'nthw/supported/nthw_fpga_9563_055_039_0000.c',
+ 'nthw/supported/nthw_fpga_instances.c',
+ 'nthw/supported/nthw_fpga_mod_str_map.c',
'nthw/nthw_platform.c',
'ntlog/ntlog.c',
'ntutil/nt_util.c',
diff --git a/drivers/net/ntnic/nthw/model/nthw_fpga_model.c b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c
new file mode 100644
index 0000000000..4f4a162574
--- /dev/null
+++ b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c
@@ -0,0 +1,1194 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <time.h> /* ctime */
+
+#include "nthw_drv.h" /* fpga_info_s */
+#include "nthw_register.h"
+#include "nthw_fpga_model.h"
+#include "nthw_rac.h"
+#include "ntlog.h"
+
+/*
+ * NOTE: this needs to be (manually) synced with enum nthw_fpga_bus_type
+ */
+static const char *const sa_nthw_fpga_bus_type_str[] = {
+ "ERR", /* NTHW_FPGA_BUS_TYPE_UNKNOWN, */
+ "BAR", /* NTHW_FPGA_BUS_TYPE_BAR, */
+ "PCI", /* NTHW_FPGA_BUS_TYPE_PCI, */
+ "CCIP", /* NTHW_FPGA_BUS_TYPE_CCIP, */
+ "RAB0", /* NTHW_FPGA_BUS_TYPE_RAB0, */
+ "RAB1", /* NTHW_FPGA_BUS_TYPE_RAB1, */
+ "RAB2", /* NTHW_FPGA_BUS_TYPE_RAB2, */
+ "NMB", /* NTHW_FPGA_BUS_TYPE_NMB, */
+ "NDM", /* NTHW_FPGA_BUS_TYPE_NDM, */
+};
+
+static const char *get_bus_name(int n_bus_type_id)
+{
+ if (n_bus_type_id >= 1 && n_bus_type_id <= (int)ARRAY_SIZE(sa_nthw_fpga_bus_type_str))
+ return sa_nthw_fpga_bus_type_str[n_bus_type_id];
+
+ else
+ return "ERR";
+}
+
+/*
+ * module name lookup by id from array
+ * Uses naive linear search as performance is not an issue here...
+ */
+
+static const struct {
+ const nthw_id_t a;
+ const char *b;
+} *sa_nthw_fpga_mod_str_map;
+
+static const char *nthw_fpga_mod_id_to_str(nthw_id_t n_fpga_mod_id)
+{
+ int i;
+
+ if (sa_nthw_fpga_mod_str_map) {
+ for (i = 0; sa_nthw_fpga_mod_str_map[i].a && sa_nthw_fpga_mod_str_map[i].b; i++)
+ if ((nthw_id_t)sa_nthw_fpga_mod_str_map[i].a == n_fpga_mod_id)
+ return sa_nthw_fpga_mod_str_map[i].b;
+ }
+
+ return "unknown";
+}
+
+static int nthw_read_data(struct fpga_info_s *p_fpga_info, bool trc, int n_bus_type_id,
+ uint32_t addr, uint32_t len, uint32_t *p_data)
+{
+ int rc = -1;
+
+ assert(p_fpga_info);
+ assert(p_data);
+ assert(len >= 1);
+
+ switch (n_bus_type_id) {
+ case NTHW_FPGA_BUS_TYPE_BAR:
+ case NTHW_FPGA_BUS_TYPE_PCI:
+ nthw_rac_bar0_read32(p_fpga_info, addr, len, p_data);
+ rc = 0;
+ break;
+
+ case NTHW_FPGA_BUS_TYPE_RAB0:
+ assert(p_fpga_info->mp_nthw_rac);
+ rc = nthw_rac_rab_read32(p_fpga_info->mp_nthw_rac, trc, 0, addr, len, p_data);
+ break;
+
+ case NTHW_FPGA_BUS_TYPE_RAB1:
+ assert(p_fpga_info->mp_nthw_rac);
+ rc = nthw_rac_rab_read32(p_fpga_info->mp_nthw_rac, trc, 1, addr, len, p_data);
+ break;
+
+ case NTHW_FPGA_BUS_TYPE_RAB2:
+ assert(p_fpga_info->mp_nthw_rac);
+ rc = nthw_rac_rab_read32(p_fpga_info->mp_nthw_rac, trc, 2, addr, len, p_data);
+ break;
+
+ default:
+ assert(false);
+ return -1;
+ }
+
+ return rc;
+}
+
+static int nthw_write_data(struct fpga_info_s *p_fpga_info, bool trc, int n_bus_type_id,
+ uint32_t addr, uint32_t len, const uint32_t *p_data)
+{
+ int rc = -1;
+
+ assert(p_fpga_info);
+ assert(p_data);
+ assert(len >= 1);
+
+ switch (n_bus_type_id) {
+ case NTHW_FPGA_BUS_TYPE_BAR:
+ case NTHW_FPGA_BUS_TYPE_PCI:
+ nthw_rac_bar0_write32(p_fpga_info, addr, len, p_data);
+ rc = 0;
+ break;
+
+ case NTHW_FPGA_BUS_TYPE_RAB0:
+ assert(p_fpga_info->mp_nthw_rac);
+ rc = nthw_rac_rab_write32(p_fpga_info->mp_nthw_rac, trc, 0, addr, len, p_data);
+ break;
+
+ case NTHW_FPGA_BUS_TYPE_RAB1:
+ assert(p_fpga_info->mp_nthw_rac);
+ rc = nthw_rac_rab_write32(p_fpga_info->mp_nthw_rac, trc, 1, addr, len, p_data);
+ break;
+
+ case NTHW_FPGA_BUS_TYPE_RAB2:
+ assert(p_fpga_info->mp_nthw_rac);
+ rc = nthw_rac_rab_write32(p_fpga_info->mp_nthw_rac, trc, 2, addr, len, p_data);
+ break;
+
+ default:
+ assert(false);
+ return -1;
+ }
+
+ return rc;
+}
+
+uint64_t nthw_fpga_read_ident(struct fpga_info_s *p_fpga_info)
+{
+ uint64_t n_fpga_ident;
+ uint32_t n_fpga_ident_lo, n_fpga_ident_hi;
+ nthw_rac_bar0_read32(p_fpga_info, 0x0, 1, &n_fpga_ident_lo);
+ nthw_rac_bar0_read32(p_fpga_info, 0x8, 1, &n_fpga_ident_hi);
+ n_fpga_ident = (((uint64_t)n_fpga_ident_hi << 32) | n_fpga_ident_lo);
+ return n_fpga_ident;
+}
+
+uint32_t nthw_fpga_read_buildtime(struct fpga_info_s *p_fpga_info)
+{
+ uint32_t n_fpga_build_time;
+ nthw_rac_bar0_read32(p_fpga_info, 0x10, 1, &n_fpga_build_time);
+ return n_fpga_build_time;
+}
+
+int nthw_fpga_extract_type_id(const uint64_t n_fpga_ident)
+{
+ return (uint16_t)(n_fpga_ident >> 32) & 0xFF;
+}
+
+int nthw_fpga_extract_prod_id(const uint64_t n_fpga_ident)
+{
+ return (uint16_t)(n_fpga_ident >> 16) & 0xFFFF;
+}
+
+int nthw_fpga_extract_ver_id(const uint64_t n_fpga_ident)
+{
+ return (uint16_t)((n_fpga_ident >> 8) & 0xFF);
+}
+
+int nthw_fpga_extract_rev_id(const uint64_t n_fpga_ident)
+{
+ return (uint16_t)(n_fpga_ident & 0xFF);
+}
+
+/*
+ * FpgaMgr
+ */
+nthw_fpga_mgr_t *nthw_fpga_mgr_new(void)
+{
+ nthw_fpga_mgr_t *p = malloc(sizeof(nthw_fpga_mgr_t));
+ return p;
+}
+
+void nthw_fpga_mgr_delete(nthw_fpga_mgr_t *p)
+{
+ memset(p, 0, sizeof(nthw_fpga_mgr_t));
+ free(p);
+}
+
+void nthw_fpga_mgr_init(nthw_fpga_mgr_t *p, struct nthw_fpga_prod_init **pa_nthw_fpga_instances,
+ const void *pa_mod_str_map)
+{
+ size_t i = 0;
+
+ p->mpa_fpga_prod_init = pa_nthw_fpga_instances;
+ sa_nthw_fpga_mod_str_map = pa_mod_str_map;
+
+ /* Count fpga instance in array */
+ if (pa_nthw_fpga_instances) {
+ for (i = 0;; i++)
+ if (p->mpa_fpga_prod_init[i] == NULL)
+ break;
+ }
+
+ p->mn_fpgas = (int)i;
+}
+
+static nthw_fpga_t *nthw_fpga_mgr_lookup_fpga(nthw_fpga_mgr_t *p, uint64_t n_fpga_id,
+ struct fpga_info_s *p_fpga_info)
+{
+ const int n_fpga_prod_id = nthw_fpga_extract_prod_id(n_fpga_id);
+ const int n_fpga_ver = nthw_fpga_extract_ver_id(n_fpga_id);
+ const int n_fpga_rev = nthw_fpga_extract_rev_id(n_fpga_id);
+ int i;
+
+ for (i = 0; i < p->mn_fpgas; i++) {
+ nthw_fpga_prod_init_s *p_init = p->mpa_fpga_prod_init[i];
+
+ if (p_init->fpga_product_id == n_fpga_prod_id &&
+ p_init->fpga_version == n_fpga_ver && p_init->fpga_revision == n_fpga_rev) {
+ nthw_fpga_t *p_fpga = nthw_fpga_model_new();
+ nthw_fpga_model_init(p_fpga, p_init, p_fpga_info);
+ return p_fpga;
+ }
+ }
+
+ return NULL;
+}
+
+nthw_fpga_t *nthw_fpga_mgr_query_fpga(nthw_fpga_mgr_t *p_fpga_mgr, uint64_t n_fpga_id,
+ struct fpga_info_s *p_fpga_info)
+{
+ const int n_fpga_prod_id = nthw_fpga_extract_prod_id(n_fpga_id);
+ const int n_fpga_ver = nthw_fpga_extract_ver_id(n_fpga_id);
+ const int n_fpga_rev = nthw_fpga_extract_rev_id(n_fpga_id);
+
+ nthw_fpga_t *p_fpga = nthw_fpga_mgr_lookup_fpga(p_fpga_mgr, n_fpga_id, p_fpga_info);
+
+ if (p_fpga) {
+ } else {
+ NT_LOG(ERR, NTHW, "FPGA Id 0x%" PRIX64 ": %04d: %d.%d: no match found\n",
+ n_fpga_id, n_fpga_prod_id, n_fpga_ver, n_fpga_rev);
+ }
+
+ return p_fpga;
+}
+
+
+void nthw_fpga_mgr_log_dump(nthw_fpga_mgr_t *p)
+{
+ int i;
+
+ NT_LOG_DBGX(DEBUG, NTHW, "fpgas=%d\n", p->mn_fpgas);
+
+ for (i = 0; i < p->mn_fpgas; i++) {
+ nthw_fpga_prod_init_s *p_init = p->mpa_fpga_prod_init[i];
+ (void)p_init;
+ NT_LOG_DBGX(DEBUG, NTHW, "fpga=%d/%d: %04d-%02d-%02d\n", i, p->mn_fpgas,
+ p_init->fpga_product_id, p_init->fpga_version, p_init->fpga_revision);
+ }
+}
+
+/*
+ * Fpga
+ */
+nthw_fpga_t *nthw_fpga_model_new(void)
+{
+ nthw_fpga_t *p = malloc(sizeof(nthw_fpga_t));
+
+ if (p)
+ memset(p, 0, sizeof(nthw_fpga_t));
+
+ return p;
+}
+
+void nthw_fpga_model_init(nthw_fpga_t *p, nthw_fpga_prod_init_s *p_init,
+ struct fpga_info_s *p_fpga_info)
+{
+ int i;
+
+ p->p_fpga_info = p_fpga_info;
+ p->mp_init = p_init;
+
+ p->mn_item_id = p_init->fpga_item_id;
+ p->mn_product_id = p_init->fpga_product_id;
+ p->mn_fpga_version = p_init->fpga_version;
+ p->mn_fpga_revision = p_init->fpga_revision;
+ p->mn_fpga_patch_no = p_init->fpga_patch_no;
+ p->mn_fpga_build_no = p_init->fpga_build_no;
+ p->mn_fpga_build_time = p_init->fpga_build_time;
+
+ p->mn_params = p_init->nb_prod_params;
+
+ if (p->mn_params) {
+ p->mpa_params = malloc(p->mn_params * sizeof(nthw_param_t *));
+
+ if (p->mpa_params) {
+ memset(p->mpa_params, 0, (p->mn_params * sizeof(nthw_param_t *)));
+
+ for (i = 0; i < p->mn_params; i++) {
+ nthw_param_t *p_param = nthw_param_new();
+
+ nthw_param_init(p_param, p, &p_init->product_params[i]);
+ p->mpa_params[i] = p_param;
+ }
+ }
+ }
+
+ p->mn_modules = p_init->nb_modules;
+
+ if (p->mn_modules) {
+ p->mpa_modules = malloc(p_init->nb_modules * sizeof(nthw_module_t *));
+
+ if (p->mpa_modules) {
+ memset(p->mpa_modules, 0, (p->mn_modules * sizeof(nthw_module_t *)));
+
+ for (i = 0; i < p->mn_modules; i++) {
+ nthw_module_t *p_mod = nthw_module_new();
+
+ nthw_module_init(p_mod, p, &p_init->modules[i]);
+ p->mpa_modules[i] = p_mod;
+ }
+ }
+ }
+}
+
+void nthw_fpga_set_debug_mode(nthw_fpga_t *p, int debug_mode)
+{
+ int i;
+
+ p->m_debug_mode = debug_mode;
+
+ for (i = 0; i < p->mn_modules; i++) {
+ nthw_module_t *p_mod = p->mpa_modules[i];
+
+ if (p_mod)
+ nthw_module_set_debug_mode(p_mod, debug_mode);
+ }
+}
+
+static nthw_module_t *nthw_fpga_lookup_module(const nthw_fpga_t *p, nthw_id_t id, int instance)
+{
+ int i;
+
+ for (i = 0; i < p->mn_modules; i++) {
+ nthw_module_t *p_mod = p->mpa_modules[i];
+
+ if (p_mod->mn_mod_id == id && p_mod->mn_instance == instance)
+ return p_mod;
+ }
+
+ return NULL;
+}
+
+nthw_module_t *nthw_fpga_query_module(const nthw_fpga_t *p, nthw_id_t id, int instance)
+{
+ return nthw_fpga_lookup_module(p, id, instance);
+}
+
+int nthw_fpga_get_product_param(const nthw_fpga_t *p, const nthw_id_t n_param_id,
+ const int n_default_value)
+{
+ int i;
+
+ for (i = 0; i < p->mn_params; i++) {
+ nthw_param_t *p_param = p->mpa_params[i];
+
+ if (p_param->mn_param_id == n_param_id)
+ return p_param->mn_param_value;
+ }
+
+ return n_default_value;
+}
+
+int nthw_fpga_get_product_id(const nthw_fpga_t *p)
+{
+ return p->mn_product_id;
+}
+
+/*
+ * Param
+ */
+nthw_param_t *nthw_param_new(void)
+{
+ nthw_param_t *p = malloc(sizeof(nthw_param_t));
+
+ return p;
+}
+
+void nthw_param_init(nthw_param_t *p, nthw_fpga_t *p_fpga, nthw_fpga_prod_param_s *p_init)
+{
+ p->mp_owner = p_fpga;
+ p->mp_init = p_init;
+
+ p->mn_param_id = p_init->id;
+ p->mn_param_value = p_init->value;
+}
+
+/*
+ * Module
+ */
+nthw_module_t *nthw_module_new(void)
+{
+ nthw_module_t *p = malloc(sizeof(nthw_module_t));
+
+ return p;
+}
+
+void nthw_module_init(nthw_module_t *p, nthw_fpga_t *p_fpga, nthw_fpga_module_init_s *p_init)
+{
+ int i;
+
+ p->mp_owner = p_fpga;
+ p->mp_init = p_init;
+
+ p->mn_mod_id = p_init->id;
+ p->mn_instance = p_init->instance;
+
+ /* Copy debug mode from owner */
+ if (p->mp_owner)
+ p->mn_debug_mode = p->mp_owner->m_debug_mode;
+
+ else
+ p->mn_debug_mode = 0;
+
+ p->mn_mod_def_id = p_init->def_id;
+ p->mn_major_version = p_init->major_version;
+ p->mn_minor_version = p_init->minor_version;
+ p->mn_bus = p_init->bus_id;
+ p->mn_addr_base = p_init->addr_base;
+
+ p->mn_registers = p_init->nb_registers;
+
+ if (p->mn_registers) {
+ p->mpa_registers = malloc(p->mn_registers * sizeof(nthw_register_t *));
+
+ if (p->mpa_registers) {
+ memset(p->mpa_registers, 0, (p->mn_registers * sizeof(nthw_register_t *)));
+
+ for (i = 0; i < p->mn_registers; i++) {
+ nthw_register_t *p_reg = nthw_register_new();
+
+ nthw_register_init(p_reg, p, &p_init->registers[i]);
+ p->mpa_registers[i] = p_reg;
+ }
+ }
+ }
+}
+
+int nthw_module_get_major_version(const nthw_module_t *p)
+{
+ return p->mn_major_version;
+}
+
+int nthw_module_get_minor_version(const nthw_module_t *p)
+{
+ return p->mn_minor_version;
+}
+
+uint64_t nthw_module_get_version_packed64(const nthw_module_t *p)
+{
+ return (((uint64_t)p->mn_major_version & 0xFFFFFFFF) << 32) |
+ (p->mn_minor_version & 0xFFFFFFFF);
+}
+
+bool nthw_module_is_version_newer(const nthw_module_t *p, int major_version, int minor_version)
+{
+ if (major_version == p->mn_major_version)
+ return p->mn_minor_version >= minor_version;
+
+ return p->mn_major_version >= major_version;
+}
+
+static nthw_register_t *nthw_module_lookup_register(nthw_module_t *p, nthw_id_t id)
+{
+ int i;
+ nthw_register_t *p_register = NULL;
+
+ for (i = 0; i < p->mn_registers; i++) {
+ if (p->mpa_registers[i]->mn_id == id) {
+ p_register = p->mpa_registers[i];
+ break;
+ }
+ }
+
+ return p_register;
+}
+
+nthw_register_t *nthw_module_query_register(nthw_module_t *p, nthw_id_t id)
+{
+ return nthw_module_lookup_register(p, id);
+}
+
+nthw_register_t *nthw_module_get_register(nthw_module_t *p, nthw_id_t id)
+{
+ nthw_register_t *p_register;
+
+ if (p == NULL) {
+ NT_LOG(ERR, NTHW, "Illegal module context for register %u\n", id);
+ return NULL;
+ }
+
+ p_register = nthw_module_lookup_register(p, id);
+
+ if (!p_register) {
+ NT_LOG(ERR, NTHW, "Register %u not found in module: %s (%u)\n", id,
+ nthw_fpga_mod_id_to_str(p->mn_mod_id), p->mn_mod_id);
+ }
+
+ return p_register;
+}
+
+int nthw_module_get_debug_mode(const nthw_module_t *p)
+{
+ return p->mn_debug_mode;
+}
+
+void nthw_module_set_debug_mode(nthw_module_t *p, unsigned int debug_mode)
+{
+ int i;
+
+ p->mn_debug_mode = debug_mode;
+
+ for (i = 0; i < p->mn_registers; i++) {
+ nthw_register_t *p_register = p->mpa_registers[i];
+
+ if (p_register)
+ nthw_register_set_debug_mode(p_register, debug_mode);
+ }
+}
+
+int nthw_module_get_bus(const nthw_module_t *p)
+{
+ return p->mn_bus;
+}
+
+/*
+ * Register
+ */
+nthw_register_t *nthw_register_new(void)
+{
+ nthw_register_t *p = malloc(sizeof(nthw_register_t));
+
+ return p;
+}
+
+void nthw_register_init(nthw_register_t *p, nthw_module_t *p_module,
+ nthw_fpga_register_init_s *p_init)
+{
+ int i;
+
+ p->mp_owner = p_module;
+
+ p->mn_id = p_init->id;
+ p->mn_bit_width = p_init->bw;
+ p->mn_addr_rel = p_init->addr_rel;
+ p->mn_addr = p_module->mn_addr_base + p_init->addr_rel;
+ p->mn_type = p_init->type;
+ /* Old P200 registers have no bw at register level - default to BW=-1 */
+ p->mn_len = ((p_init->bw != (uint16_t)-1) ? ((p_init->bw + 31) >> 5) : 1);
+ p->mn_debug_mode = p_module->mn_debug_mode;
+
+ p->mn_fields = p_init->nb_fields;
+
+ if (p->mn_fields) {
+ p->mpa_fields = malloc(p->mn_fields * sizeof(nthw_field_t *));
+
+ if (p->mpa_fields) {
+ memset(p->mpa_fields, 0, (p->mn_fields * sizeof(nthw_field_t *)));
+
+ for (i = 0; i < p->mn_fields; i++) {
+ nthw_field_t *p_field = nthw_field_new();
+
+ nthw_field_init(p_field, p, &p_init->fields[i]);
+ p->mpa_fields[i] = p_field;
+ }
+
+ p->mp_shadow = malloc(p->mn_len * sizeof(uint32_t));
+
+ if (p->mp_shadow)
+ memset(p->mp_shadow, 0x00, (p->mn_len * sizeof(uint32_t)));
+
+ p->mp_dirty = malloc(p->mn_len * sizeof(bool));
+
+ if (p->mp_dirty)
+ memset(p->mp_dirty, 0x00, (p->mn_len * sizeof(bool)));
+ }
+ }
+}
+
+uint32_t nthw_register_get_address(const nthw_register_t *p)
+{
+ return p->mn_addr;
+}
+
+void nthw_register_reset(const nthw_register_t *p)
+{
+ int i;
+ nthw_field_t *p_field = NULL;
+
+ for (i = 0; i < p->mn_fields; i++) {
+ p_field = p->mpa_fields[i];
+
+ if (p_field)
+ nthw_field_reset(p_field);
+ }
+}
+
+static nthw_field_t *nthw_register_lookup_field(const nthw_register_t *p, nthw_id_t id)
+{
+ int i;
+ nthw_field_t *p_field = NULL;
+
+ if (!p)
+ return NULL;
+
+ for (i = 0; i < p->mn_fields; i++) {
+ if (p->mpa_fields[i]->mn_id == id) {
+ p_field = p->mpa_fields[i];
+ break;
+ }
+ }
+
+ return p_field;
+}
+
+nthw_field_t *nthw_register_query_field(const nthw_register_t *p, nthw_id_t id)
+{
+ return nthw_register_lookup_field(p, id);
+}
+
+nthw_field_t *nthw_register_get_field(const nthw_register_t *p, nthw_id_t id)
+{
+ nthw_field_t *p_field;
+
+ if (p == NULL) {
+ NT_LOG(ERR, NTHW, "Illegal register context for field %u\n", id);
+ return NULL;
+ }
+
+ p_field = nthw_register_lookup_field(p, id);
+
+ if (!p_field) {
+ NT_LOG(ERR, NTHW, "Field %u not found in module: %s (%u)\n", id,
+ nthw_fpga_mod_id_to_str(p->mp_owner->mn_mod_id), p->mp_owner->mn_mod_id);
+ }
+
+ return p_field;
+}
+
+int nthw_register_get_bit_width(const nthw_register_t *p)
+{
+ return p->mn_bit_width;
+}
+
+int nthw_register_get_debug_mode(const nthw_register_t *p)
+{
+ return p->mn_debug_mode;
+}
+
+/*
+ * NOTE: do not set debug on fields - as register operation dumps typically are enough
+ */
+void nthw_register_set_debug_mode(nthw_register_t *p, unsigned int debug_mode)
+{
+ int i;
+
+ p->mn_debug_mode = debug_mode;
+
+ for (i = 0; i < p->mn_fields; i++) {
+ nthw_field_t *p_field = p->mpa_fields[i];
+
+ if (p_field)
+ nthw_field_set_debug_mode(p_field, debug_mode);
+ }
+}
+
+static int nthw_register_read_data(const nthw_register_t *p)
+{
+ int rc = -1;
+
+ const int n_bus_type_id = nthw_module_get_bus(p->mp_owner);
+ const uint32_t addr = p->mn_addr;
+ const uint32_t len = p->mn_len;
+ uint32_t *const p_data = p->mp_shadow;
+ const bool trc = (p->mn_debug_mode & NTHW_REG_TRACE_ON_READ);
+
+ struct fpga_info_s *p_fpga_info = NULL;
+
+ if (p && p->mp_owner && p->mp_owner->mp_owner)
+ p_fpga_info = p->mp_owner->mp_owner->p_fpga_info;
+
+ assert(p_fpga_info);
+ assert(p_data);
+
+ rc = nthw_read_data(p_fpga_info, trc, n_bus_type_id, addr, len, p_data);
+ return rc;
+}
+
+static int nthw_register_write_data(const nthw_register_t *p, uint32_t cnt)
+{
+ int rc = -1;
+
+ const int n_bus_type_id = nthw_module_get_bus(p->mp_owner);
+ const uint32_t addr = p->mn_addr;
+ const uint32_t len = p->mn_len;
+ uint32_t *const p_data = p->mp_shadow;
+ const bool trc = (p->mn_debug_mode & NTHW_REG_TRACE_ON_WRITE);
+
+ struct fpga_info_s *p_fpga_info = NULL;
+
+ if (p && p->mp_owner && p->mp_owner->mp_owner)
+ p_fpga_info = p->mp_owner->mp_owner->p_fpga_info;
+
+ assert(p_fpga_info);
+ assert(p_data);
+
+ rc = nthw_write_data(p_fpga_info, trc, n_bus_type_id, addr, (len * cnt), p_data);
+
+ return rc;
+}
+
+void nthw_register_get_val(const nthw_register_t *p, uint32_t *p_data, uint32_t len)
+{
+ uint32_t i;
+
+ if (len == (uint32_t)-1 || len > p->mn_len)
+ len = p->mn_len;
+
+ assert(len <= p->mn_len);
+ assert(p_data);
+
+ for (i = 0; i < len; i++)
+ p_data[i] = p->mp_shadow[i];
+}
+
+uint32_t nthw_register_get_val32(const nthw_register_t *p)
+{
+ uint32_t val = 0;
+
+ nthw_register_get_val(p, &val, 1);
+ return val;
+}
+
+void nthw_register_update(const nthw_register_t *p)
+{
+ if (p && p->mn_type != NTHW_FPGA_REG_TYPE_WO) {
+ const char *const p_dev_name = "NA";
+ (void)p_dev_name;
+ const int n_bus_type_id = nthw_module_get_bus(p->mp_owner);
+ const char *const p_bus_name = get_bus_name(n_bus_type_id);
+ (void)p_bus_name;
+ const uint32_t addr = p->mn_addr;
+ (void)addr;
+ const uint32_t len = p->mn_len;
+ uint32_t *const p_data = p->mp_shadow;
+
+ nthw_register_read_data(p);
+
+ if (p->mn_debug_mode & NTHW_REG_DEBUG_ON_READ) {
+ uint32_t i = len;
+ uint32_t *ptr = p_data;
+ (void)ptr;
+ char *tmp_string = ntlog_helper_str_alloc("Register::read");
+ ntlog_helper_str_add(tmp_string,
+ "(Dev: %s, Bus: %s, Addr: 0x%08X, Cnt: %d, Data:",
+ p_dev_name, p_bus_name, addr, len);
+
+ while (i--)
+ ntlog_helper_str_add(tmp_string, " 0x%08X", *ptr++);
+
+ ntlog_helper_str_add(tmp_string, ")");
+ NT_LOG(DBG, NTHW, "%s", tmp_string);
+ ntlog_helper_str_free(tmp_string);
+ }
+ }
+}
+
+uint32_t nthw_register_get_val_updated32(const nthw_register_t *p)
+{
+ uint32_t val = 0;
+
+ nthw_register_update(p);
+ nthw_register_get_val(p, &val, 1);
+ return val;
+}
+
+void nthw_register_make_dirty(nthw_register_t *p)
+{
+ uint32_t i;
+
+ for (i = 0; i < p->mn_len; i++)
+ p->mp_dirty[i] = true;
+}
+
+void nthw_register_set_val(nthw_register_t *p, const uint32_t *p_data, uint32_t len)
+{
+ assert(len <= p->mn_len);
+ assert(p_data);
+
+ if (len == (uint32_t)-1 || len > p->mn_len)
+ len = p->mn_len;
+
+ if (p->mp_shadow != p_data)
+ memcpy(p->mp_shadow, p_data, (len * sizeof(uint32_t)));
+}
+
+void nthw_register_flush(const nthw_register_t *p, uint32_t cnt)
+{
+ int rc;
+
+ if (p->mn_type != NTHW_FPGA_REG_TYPE_RO) {
+ const char *const p_dev_name = "NA";
+ const int n_bus_type_id = nthw_module_get_bus(p->mp_owner);
+ const char *p_bus_name = get_bus_name(n_bus_type_id);
+ const uint32_t addr = p->mn_addr;
+ const uint32_t len = p->mn_len;
+ uint32_t *const p_data = p->mp_shadow;
+ uint32_t i;
+
+ assert(len * cnt <= 256);
+
+ if (p->mn_debug_mode & NTHW_REG_DEBUG_ON_WRITE) {
+ uint32_t i = len * cnt;
+ uint32_t *ptr = p_data;
+ char *tmp_string = ntlog_helper_str_alloc("Register::write");
+
+ ntlog_helper_str_add(tmp_string,
+ "(Dev: %s, Bus: %s, Addr: 0x%08X, Cnt: %d, Data:",
+ p_dev_name, p_bus_name, addr, i);
+
+ while (i--)
+ ntlog_helper_str_add(tmp_string, " 0x%08X", *ptr++);
+
+ ntlog_helper_str_add(tmp_string, ")");
+ NT_LOG(DBG, NTHW, "%s", tmp_string);
+ ntlog_helper_str_free(tmp_string);
+ }
+
+ rc = nthw_register_write_data(p, cnt);
+
+ if (rc)
+ NT_LOG(ERR, NTHW, "Register write error %d\n", rc);
+
+ for (i = 0; i < cnt; i++)
+ p->mp_dirty[i] = false;
+ }
+}
+
+void nthw_register_clr(nthw_register_t *p)
+{
+ memset(p->mp_shadow, 0, p->mn_len * sizeof(uint32_t));
+ nthw_register_make_dirty(p);
+}
+
+/*
+ * Field
+ */
+nthw_field_t *nthw_field_new(void)
+{
+ nthw_field_t *p = malloc(sizeof(nthw_field_t));
+
+ return p;
+}
+
+void nthw_field_init(nthw_field_t *p, nthw_register_t *p_reg, const nthw_fpga_field_init_s *p_init)
+{
+ p->mp_owner = p_reg;
+
+ p->mn_debug_mode = p_reg->mn_debug_mode;
+
+ p->mn_id = p_init->id;
+ p->mn_bit_width = p_init->bw;
+ p->mn_bit_pos_low = p_init->low;
+ p->mn_reset_val = (uint32_t)p_init->reset_val;
+ p->mn_first_word = p_init->low / 32;
+ p->mn_first_bit = p_init->low % 32;
+ p->mn_front_mask = 0;
+ p->mn_body_length = 0;
+ p->mn_words = (p_init->bw + 0x1f) / 0x20;
+ p->mn_tail_mask = 0;
+
+ {
+ int bits_remaining = p_init->bw;
+ int front_mask_length = 32 - p->mn_first_bit;
+
+ if (front_mask_length > bits_remaining)
+ front_mask_length = bits_remaining;
+
+ bits_remaining -= front_mask_length;
+
+ p->mn_front_mask =
+ (uint32_t)(((1ULL << front_mask_length) - 1) << p->mn_first_bit);
+
+ p->mn_body_length = bits_remaining / 32;
+ bits_remaining -= p->mn_body_length * 32;
+ p->mn_tail_mask = (1 << bits_remaining) - 1;
+
+ if (p->mn_debug_mode >= 0x100) {
+ NT_LOG_DBGX(DEBUG, NTHW,
+ "fldid=%08d: [%08d:%08d] %08d/%08d: (%08d,%08d) (0x%08X,%08d,0x%08X)\n",
+ p_init->id, p_init->low, (p_init->low + p_init->bw),
+ p_init->bw, ((p_init->bw + 31) / 32), p->mn_first_word,
+ p->mn_first_bit, p->mn_front_mask, p->mn_body_length,
+ p->mn_tail_mask);
+ }
+ }
+}
+
+int nthw_field_get_debug_mode(const nthw_field_t *p)
+{
+ return p->mn_debug_mode;
+}
+
+void nthw_field_set_debug_mode(nthw_field_t *p, unsigned int debug_mode)
+{
+ p->mn_debug_mode = debug_mode;
+}
+
+int nthw_field_get_bit_width(const nthw_field_t *p)
+{
+ return p->mn_bit_width;
+}
+
+int nthw_field_get_bit_pos_low(const nthw_field_t *p)
+{
+ return p->mn_bit_pos_low;
+}
+
+int nthw_field_get_bit_pos_high(const nthw_field_t *p)
+{
+ return p->mn_bit_pos_low + p->mn_bit_width - 1;
+}
+
+uint32_t nthw_field_get_mask(const nthw_field_t *p)
+{
+ return p->mn_front_mask;
+}
+
+void nthw_field_reset(const nthw_field_t *p)
+{
+ nthw_field_set_val32(p, (uint32_t)p->mn_reset_val);
+}
+
+void nthw_field_get_val(const nthw_field_t *p, uint32_t *p_data, uint32_t len)
+{
+ uint32_t i;
+ uint32_t data_index = 0;
+ uint32_t shadow_index = p->mn_first_word;
+
+ union {
+ uint32_t w32[2];
+ uint64_t w64;
+ } buf;
+
+ (void)len;
+ assert(len <= p->mn_words);
+
+ /* handle front */
+ buf.w32[0] = p->mp_owner->mp_shadow[shadow_index++] & p->mn_front_mask;
+
+ /* handle body */
+ for (i = 0; i < p->mn_body_length; i++) {
+ buf.w32[1] = p->mp_owner->mp_shadow[shadow_index++];
+ buf.w64 = buf.w64 >> (p->mn_first_bit);
+ assert(data_index < len);
+ p_data[data_index++] = buf.w32[0];
+ buf.w64 = buf.w64 >> (32 - p->mn_first_bit);
+ }
+
+ /* handle tail */
+ if (p->mn_tail_mask)
+ buf.w32[1] = p->mp_owner->mp_shadow[shadow_index++] & p->mn_tail_mask;
+
+ else
+ buf.w32[1] = 0;
+
+ buf.w64 = buf.w64 >> (p->mn_first_bit);
+ p_data[data_index++] = buf.w32[0];
+
+ if (data_index < p->mn_words)
+ p_data[data_index++] = buf.w32[1];
+}
+
+void nthw_field_set_val(const nthw_field_t *p, const uint32_t *p_data, uint32_t len)
+{
+ uint32_t i;
+ uint32_t data_index = 0;
+ uint32_t shadow_index = p->mn_first_word;
+
+ union {
+ uint32_t w32[2];
+ uint64_t w64;
+ } buf;
+
+ (void)len;
+ assert(len == p->mn_words);
+
+ /* handle front */
+ buf.w32[0] = 0;
+ buf.w32[1] = p_data[data_index++];
+ buf.w64 = buf.w64 >> (32 - p->mn_first_bit);
+ p->mp_owner->mp_shadow[shadow_index] =
+ (p->mp_owner->mp_shadow[shadow_index] & ~p->mn_front_mask) |
+ (buf.w32[0] & p->mn_front_mask);
+ shadow_index++;
+
+ /* handle body */
+ for (i = 0; i < p->mn_body_length; i++) {
+ buf.w64 = buf.w64 >> (p->mn_first_bit);
+ assert(data_index < len);
+ buf.w32[1] = p_data[data_index++];
+ buf.w64 = buf.w64 >> (32 - p->mn_first_bit);
+ p->mp_owner->mp_shadow[shadow_index++] = buf.w32[0];
+ }
+
+ /* handle tail */
+ if (p->mn_tail_mask) {
+ buf.w64 = buf.w64 >> (p->mn_first_bit);
+
+ if (data_index < len)
+ buf.w32[1] = p_data[data_index];
+
+ buf.w64 = buf.w64 >> (32 - p->mn_first_bit);
+ p->mp_owner->mp_shadow[shadow_index] =
+ (p->mp_owner->mp_shadow[shadow_index] & ~p->mn_tail_mask) |
+ (buf.w32[0] & p->mn_tail_mask);
+ }
+
+ nthw_register_make_dirty(p->mp_owner);
+}
+
+void nthw_field_set_val_flush(const nthw_field_t *p, const uint32_t *p_data, uint32_t len)
+{
+ nthw_field_set_val(p, p_data, len);
+ nthw_field_flush_register(p);
+}
+
+uint32_t nthw_field_get_val32(const nthw_field_t *p)
+{
+ uint32_t val;
+
+ nthw_field_get_val(p, &val, 1);
+ return val;
+}
+
+uint32_t nthw_field_get_updated(const nthw_field_t *p)
+{
+ uint32_t val;
+
+ nthw_register_update(p->mp_owner);
+ nthw_field_get_val(p, &val, 1);
+
+ return val;
+}
+
+void nthw_field_update_register(const nthw_field_t *p)
+{
+ nthw_register_update(p->mp_owner);
+}
+
+void nthw_field_flush_register(const nthw_field_t *p)
+{
+ nthw_register_flush(p->mp_owner, 1);
+}
+
+void nthw_field_set_val32(const nthw_field_t *p, uint32_t val)
+{
+ nthw_field_set_val(p, &val, 1);
+}
+
+void nthw_field_set_val_flush32(const nthw_field_t *p, uint32_t val)
+{
+ nthw_field_set_val(p, &val, 1);
+ nthw_register_flush(p->mp_owner, 1);
+}
+
+void nthw_field_clr_all(const nthw_field_t *p)
+{
+ assert(p->mn_body_length == 0);
+ nthw_field_set_val32(p, 0);
+}
+
+void nthw_field_clr_flush(const nthw_field_t *p)
+{
+ nthw_field_clr_all(p);
+ nthw_register_flush(p->mp_owner, 1);
+}
+
+void nthw_field_set_all(const nthw_field_t *p)
+{
+ assert(p->mn_body_length == 0);
+ nthw_field_set_val32(p, ~0);
+}
+
+void nthw_field_set_flush(const nthw_field_t *p)
+{
+ nthw_field_set_all(p);
+ nthw_register_flush(p->mp_owner, 1);
+}
+
+enum nthw_field_match {
+ NTHW_FIELD_MATCH_CLR_ALL,
+ NTHW_FIELD_MATCH_SET_ALL,
+ NTHW_FIELD_MATCH_CLR_ANY,
+ NTHW_FIELD_MATCH_SET_ANY,
+};
+
+static int nthw_field_wait_cond32(const nthw_field_t *p, enum nthw_field_match e_match,
+ int n_poll_iterations, int n_poll_interval)
+{
+ const uint32_t n_mask = (1 << p->mn_bit_width) - 1;
+
+ if (n_poll_iterations == -1)
+ n_poll_iterations = 10000;
+
+ if (n_poll_interval == -1)
+ n_poll_interval = 100; /* usec */
+
+ if (p->mn_debug_mode) {
+ const char *const p_cond_name =
+ ((e_match == NTHW_FIELD_MATCH_SET_ALL)
+ ? "SetAll"
+ : ((e_match == NTHW_FIELD_MATCH_CLR_ALL)
+ ? "ClrAll"
+ : ((e_match == NTHW_FIELD_MATCH_CLR_ANY) ? "ClrAny"
+ : "SetAny")));
+ (void)p_cond_name;
+ const char *const p_dev_name = "NA";
+ (void)p_dev_name;
+ const char *const p_bus_name =
+ get_bus_name(nthw_module_get_bus(p->mp_owner->mp_owner));
+ (void)p_bus_name;
+ uint32_t n_reg_addr = nthw_register_get_address(p->mp_owner);
+ (void)n_reg_addr;
+ uint32_t n_reg_mask = (((1 << p->mn_bit_width) - 1) << p->mn_bit_pos_low);
+ (void)n_reg_mask;
+
+ NT_LOG(DBG, NTHW,
+ "Register::Field::wait%s32(Dev: %s, Bus: %s, Addr: 0x%08X, Mask: 0x%08X, Iterations: %d, Interval: %d)\n",
+ p_cond_name, p_dev_name, p_bus_name, n_reg_addr, n_reg_mask,
+ n_poll_iterations, n_poll_interval);
+ }
+
+ while (true) {
+ uint32_t val = nthw_field_get_updated(p);
+
+ if (e_match == NTHW_FIELD_MATCH_SET_ANY && val != 0) {
+ return 0;
+
+ } else if (e_match == NTHW_FIELD_MATCH_SET_ALL && val == n_mask) {
+ return 0;
+
+ } else if (e_match == NTHW_FIELD_MATCH_CLR_ALL && val == 0) {
+ return 0;
+
+ } else if (e_match == NTHW_FIELD_MATCH_CLR_ANY) {
+ uint32_t mask = nthw_field_get_mask(p);
+
+ if (val != mask)
+ return 0;
+ }
+
+ n_poll_iterations--;
+
+ if (n_poll_iterations <= 0)
+ return -1;
+
+ nt_os_wait_usec(n_poll_interval);
+ }
+
+ return 0;
+}
+
+int nthw_field_wait_set_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval)
+{
+ return nthw_field_wait_cond32(p, NTHW_FIELD_MATCH_SET_ALL, n_poll_iterations,
+ n_poll_interval);
+}
+
+int nthw_field_wait_clr_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval)
+{
+ return nthw_field_wait_cond32(p, NTHW_FIELD_MATCH_CLR_ALL, n_poll_iterations,
+ n_poll_interval);
+}
+
+int nthw_field_wait_set_any32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval)
+{
+ return nthw_field_wait_cond32(p, NTHW_FIELD_MATCH_SET_ANY, n_poll_iterations,
+ n_poll_interval);
+}
+
+/* EOF */
diff --git a/drivers/net/ntnic/nthw/model/nthw_fpga_model.h b/drivers/net/ntnic/nthw/model/nthw_fpga_model.h
new file mode 100644
index 0000000000..7956f0689e
--- /dev/null
+++ b/drivers/net/ntnic/nthw/model/nthw_fpga_model.h
@@ -0,0 +1,245 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _NTHW_FPGA_MODEL_H_
+#define _NTHW_FPGA_MODEL_H_
+
+#include <stdbool.h>
+#include "fpga_model.h"
+
+#define VERSION_PACKED64(_major_, _minor_) \
+ ((((uint64_t)(_major_) & (0xFFFFFFFF)) << 32) | ((_minor_) & (0xFFFFFFFF)))
+
+enum nthw_reg_debug_mode {
+ NTHW_REG_DEBUG_NONE = 0,
+ NTHW_REG_DEBUG_ON_READ = 1,
+ NTHW_REG_DEBUG_ON_WRITE = 2,
+ NTHW_REG_TRACE_ON_READ = 4,
+ NTHW_REG_TRACE_ON_WRITE = 8,
+};
+
+struct nthw_fpga_s;
+
+struct nthw_param_s;
+
+struct nthw_module_s;
+
+struct nthw_register_s;
+
+struct nthw_field_s;
+
+struct nthw_fpga_mgr_s {
+ int mn_fpgas;
+ struct nthw_fpga_prod_init **mpa_fpga_prod_init;
+};
+
+typedef struct nthw_fpga_mgr_s nthw_fpga_mgr_t;
+
+struct nthw_fpga_s {
+ struct fpga_info_s *p_fpga_info;
+
+ int mn_item_id;
+ int mn_product_id;
+ int mn_fpga_version;
+ int mn_fpga_revision;
+ int mn_fpga_patch_no;
+ int mn_fpga_build_no;
+ uint32_t mn_fpga_build_time;
+
+ int mn_params;
+ struct nthw_param_s **mpa_params;
+
+ int mn_modules;
+ struct nthw_module_s **mpa_modules;
+
+ nthw_fpga_prod_init_s *mp_init;
+
+ int m_debug_mode;
+};
+
+typedef struct nthw_fpga_s nthw_fpga_t;
+
+struct nthw_param_s {
+ nthw_fpga_t *mp_owner;
+
+ nthw_id_t mn_param_id;
+ int mn_param_value;
+
+ nthw_fpga_prod_param_s *mp_init;
+};
+
+typedef struct nthw_param_s nthw_param_t;
+
+struct nthw_module_s {
+ nthw_fpga_t *mp_owner;
+
+ nthw_id_t mn_mod_id;
+
+ int mn_instance;
+
+ int mn_mod_def_id;
+ int mn_major_version;
+ int mn_minor_version;
+
+ int mn_bus;
+ uint32_t mn_addr_base;
+
+ int mn_debug_mode;
+
+ int mn_registers;
+ struct nthw_register_s **mpa_registers;
+
+ nthw_fpga_module_init_s *mp_init;
+};
+
+typedef struct nthw_module_s nthw_module_t;
+
+struct nthw_register_s {
+ nthw_module_t *mp_owner;
+
+ nthw_id_t mn_id;
+
+ uint32_t mn_bit_width;
+ uint32_t mn_addr_rel;
+ uint32_t mn_addr;
+ uint32_t mn_type;
+ uint32_t mn_len;
+
+ int mn_debug_mode;
+
+ int mn_fields;
+ struct nthw_field_s **mpa_fields;
+
+ uint32_t *mp_shadow;
+ bool *mp_dirty;
+
+ nthw_fpga_register_init_s *mp_init;
+};
+
+typedef struct nthw_register_s nthw_register_t;
+
+struct nthw_field_s {
+ nthw_register_t *mp_owner;
+
+ nthw_id_t mn_id;
+
+ uint32_t mn_bit_width;
+ uint32_t mn_bit_pos_low;
+ uint32_t mn_reset_val;
+ uint32_t mn_first_word;
+ uint32_t mn_first_bit;
+ uint32_t mn_front_mask;
+ uint32_t mn_body_length;
+ uint32_t mn_words;
+ uint32_t mn_tail_mask;
+
+ int mn_debug_mode;
+
+ nthw_fpga_field_init_s *mp_init;
+};
+
+typedef struct nthw_field_s nthw_field_t;
+
+int nthw_fpga_extract_type_id(const uint64_t n_fpga_ident);
+int nthw_fpga_extract_prod_id(const uint64_t n_fpga_ident);
+int nthw_fpga_extract_ver_id(const uint64_t n_fpga_ident);
+int nthw_fpga_extract_rev_id(const uint64_t n_fpga_ident);
+
+uint64_t nthw_fpga_read_ident(struct fpga_info_s *p_fpga_info);
+uint32_t nthw_fpga_read_buildtime(struct fpga_info_s *p_fpga_info);
+
+nthw_fpga_mgr_t *nthw_fpga_mgr_new(void);
+void nthw_fpga_mgr_init(nthw_fpga_mgr_t *p, struct nthw_fpga_prod_init **pa_nthw_fpga_instances,
+ const void *pa_mod_str_map);
+void nthw_fpga_mgr_delete(nthw_fpga_mgr_t *p);
+nthw_fpga_t *nthw_fpga_mgr_query_fpga(nthw_fpga_mgr_t *p, uint64_t n_fpga_id,
+ struct fpga_info_s *p_fpga_info);
+void nthw_fpga_mgr_log_dump(nthw_fpga_mgr_t *p);
+
+nthw_fpga_t *nthw_fpga_model_new(void);
+void nthw_fpga_model_init(nthw_fpga_t *p, nthw_fpga_prod_init_s *p_init,
+ struct fpga_info_s *p_fpga_info);
+
+int nthw_fpga_get_product_param(const nthw_fpga_t *p, const nthw_id_t n_param_id,
+ const int default_value);
+int nthw_fpga_get_product_id(const nthw_fpga_t *p);
+
+nthw_module_t *nthw_fpga_query_module(const nthw_fpga_t *p, nthw_id_t id, int instance);
+void nthw_fpga_set_debug_mode(nthw_fpga_t *p, int n_debug_mode);
+
+nthw_param_t *nthw_param_new(void);
+void nthw_param_init(nthw_param_t *p, nthw_fpga_t *p_fpga, nthw_fpga_prod_param_s *p_init);
+
+nthw_module_t *nthw_module_new(void);
+void nthw_module_init(nthw_module_t *p, nthw_fpga_t *p_fpga, nthw_fpga_module_init_s *p_init);
+void nthw_module_init2(nthw_module_t *p, nthw_fpga_t *p_fpga, nthw_id_t mod_id, int instance,
+ int debug_mode);
+
+int nthw_module_get_major_version(const nthw_module_t *p);
+int nthw_module_get_minor_version(const nthw_module_t *p);
+uint64_t nthw_module_get_version_packed64(const nthw_module_t *p);
+bool nthw_module_is_version_newer(const nthw_module_t *p, int major_version, int minor_version);
+
+int nthw_module_get_bus(const nthw_module_t *p);
+nthw_register_t *nthw_module_query_register(nthw_module_t *p, nthw_id_t id);
+nthw_register_t *nthw_module_get_register(nthw_module_t *p, nthw_id_t id);
+int nthw_module_get_debug_mode(const nthw_module_t *p);
+void nthw_module_set_debug_mode(nthw_module_t *p, unsigned int debug_mode);
+
+nthw_register_t *nthw_register_new(void);
+void nthw_register_init(nthw_register_t *p, nthw_module_t *p_module,
+ nthw_fpga_register_init_s *p_init);
+
+nthw_field_t *nthw_register_query_field(const nthw_register_t *p, nthw_id_t id);
+nthw_field_t *nthw_register_get_field(const nthw_register_t *p, nthw_id_t id);
+
+uint32_t nthw_register_get_address(const nthw_register_t *p);
+int nthw_register_get_bit_width(const nthw_register_t *p);
+int nthw_register_get_debug_mode(const nthw_register_t *p);
+void nthw_register_set_debug_mode(nthw_register_t *p, unsigned int debug_mode);
+
+void nthw_register_get_val(const nthw_register_t *p, uint32_t *p_data, uint32_t len);
+uint32_t nthw_register_get_val32(const nthw_register_t *p);
+uint32_t nthw_register_get_val_updated32(const nthw_register_t *p);
+
+void nthw_register_set_val(nthw_register_t *p, const uint32_t *p_data, uint32_t len);
+
+void nthw_register_make_dirty(nthw_register_t *p);
+void nthw_register_update(const nthw_register_t *p);
+void nthw_register_reset(const nthw_register_t *p);
+void nthw_register_flush(const nthw_register_t *p, uint32_t cnt);
+void nthw_register_clr(nthw_register_t *p);
+
+nthw_field_t *nthw_field_new(void);
+void nthw_field_init(nthw_field_t *p, nthw_register_t *p_reg,
+ const nthw_fpga_field_init_s *p_init);
+
+int nthw_field_get_debug_mode(const nthw_field_t *p);
+void nthw_field_set_debug_mode(nthw_field_t *p, unsigned int n_debug_mode);
+int nthw_field_get_bit_width(const nthw_field_t *p);
+int nthw_field_get_bit_pos_low(const nthw_field_t *p);
+int nthw_field_get_bit_pos_high(const nthw_field_t *p);
+uint32_t nthw_field_get_mask(const nthw_field_t *p);
+void nthw_field_reset(const nthw_field_t *p);
+void nthw_field_get_val(const nthw_field_t *p, uint32_t *p_data, uint32_t len);
+void nthw_field_set_val(const nthw_field_t *p, const uint32_t *p_data, uint32_t len);
+void nthw_field_set_val_flush(const nthw_field_t *p, const uint32_t *p_data, uint32_t len);
+uint32_t nthw_field_get_val32(const nthw_field_t *p);
+uint32_t nthw_field_get_updated(const nthw_field_t *p);
+void nthw_field_update_register(const nthw_field_t *p);
+void nthw_field_flush_register(const nthw_field_t *p);
+void nthw_field_set_val32(const nthw_field_t *p, uint32_t val);
+void nthw_field_set_val_flush32(const nthw_field_t *p, uint32_t val);
+void nthw_field_clr_all(const nthw_field_t *p);
+void nthw_field_clr_flush(const nthw_field_t *p);
+void nthw_field_set_all(const nthw_field_t *p);
+void nthw_field_set_flush(const nthw_field_t *p);
+
+int nthw_field_wait_clr_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval);
+int nthw_field_wait_set_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval);
+
+int nthw_field_wait_set_any32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval);
+
+#endif /* _NTHW_FPGA_MODEL_H_ */
diff --git a/drivers/net/ntnic/nthw/nthw_register.h b/drivers/net/ntnic/nthw/nthw_register.h
new file mode 100644
index 0000000000..db006fcf72
--- /dev/null
+++ b/drivers/net/ntnic/nthw/nthw_register.h
@@ -0,0 +1,21 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NTHW_REGISTER_H_
+#define NTHW_REGISTER_H_
+
+#include <unistd.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <inttypes.h>
+
+
+#include "fpga_model.h"
+
+#include "nthw_fpga_mod_defs.h"
+#include "nthw_fpga_param_defs.h"
+#include "nthw_fpga_reg_defs.h"
+
+#endif /* NTHW_REGISTER_H_ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
new file mode 100644
index 0000000000..f5bd833ff1
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c
@@ -0,0 +1,1233 @@
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+#include "nthw_register.h"
+
+static nthw_fpga_field_init_s gfg_burstsize0_fields[] = {
+ { GFG_BURSTSIZE0_VAL, 24, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_burstsize1_fields[] = {
+ { GFG_BURSTSIZE1_VAL, 24, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_ctrl0_fields[] = {
+ { GFG_CTRL0_ENABLE, 1, 0, 0 },
+ { GFG_CTRL0_MODE, 3, 1, 0 },
+ { GFG_CTRL0_PRBS_EN, 1, 4, 0 },
+ { GFG_CTRL0_SIZE, 14, 16, 64 },
+};
+
+static nthw_fpga_field_init_s gfg_ctrl1_fields[] = {
+ { GFG_CTRL1_ENABLE, 1, 0, 0 },
+ { GFG_CTRL1_MODE, 3, 1, 0 },
+ { GFG_CTRL1_PRBS_EN, 1, 4, 0 },
+ { GFG_CTRL1_SIZE, 14, 16, 64 },
+};
+
+static nthw_fpga_field_init_s gfg_run0_fields[] = {
+ { GFG_RUN0_RUN, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_run1_fields[] = {
+ { GFG_RUN1_RUN, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_sizemask0_fields[] = {
+ { GFG_SIZEMASK0_VAL, 14, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_sizemask1_fields[] = {
+ { GFG_SIZEMASK1_VAL, 14, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_streamid0_fields[] = {
+ { GFG_STREAMID0_VAL, 8, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gfg_streamid1_fields[] = {
+ { GFG_STREAMID1_VAL, 8, 0, 1 },
+};
+
+static nthw_fpga_register_init_s gfg_registers[] = {
+ { GFG_BURSTSIZE0, 3, 24, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_burstsize0_fields },
+ { GFG_BURSTSIZE1, 8, 24, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_burstsize1_fields },
+ { GFG_CTRL0, 0, 30, NTHW_FPGA_REG_TYPE_WO, 4194304, 4, gfg_ctrl0_fields },
+ { GFG_CTRL1, 5, 30, NTHW_FPGA_REG_TYPE_WO, 4194304, 4, gfg_ctrl1_fields },
+ { GFG_RUN0, 1, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_run0_fields },
+ { GFG_RUN1, 6, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_run1_fields },
+ { GFG_SIZEMASK0, 4, 14, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_sizemask0_fields },
+ { GFG_SIZEMASK1, 9, 14, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_sizemask1_fields },
+ { GFG_STREAMID0, 2, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_streamid0_fields },
+ { GFG_STREAMID1, 7, 8, NTHW_FPGA_REG_TYPE_WO, 1, 1, gfg_streamid1_fields },
+};
+
+static nthw_fpga_field_init_s gmf_ctrl_fields[] = {
+ { GMF_CTRL_ENABLE, 1, 0, 0 },
+ { GMF_CTRL_FCS_ALWAYS, 1, 1, 0 },
+ { GMF_CTRL_IFG_AUTO_ADJUST_ENABLE, 1, 7, 0 },
+ { GMF_CTRL_IFG_ENABLE, 1, 2, 0 },
+ { GMF_CTRL_IFG_TX_NOW_ALWAYS, 1, 3, 0 },
+ { GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE, 1, 5, 0 },
+ { GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK, 1, 6, 0 },
+ { GMF_CTRL_IFG_TX_ON_TS_ALWAYS, 1, 4, 0 },
+ { GMF_CTRL_TS_INJECT_ALWAYS, 1, 8, 0 },
+ { GMF_CTRL_TS_INJECT_DUAL_STEP, 1, 9, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_debug_lane_marker_fields[] = {
+ { GMF_DEBUG_LANE_MARKER_COMPENSATION, 16, 0, 16384 },
+};
+
+static nthw_fpga_field_init_s gmf_ifg_max_adjust_slack_fields[] = {
+ { GMF_IFG_MAX_ADJUST_SLACK_SLACK, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_ifg_set_clock_delta_fields[] = {
+ { GMF_IFG_SET_CLOCK_DELTA_DELTA, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_ifg_set_clock_delta_adjust_fields[] = {
+ { GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_ifg_tx_now_on_ts_fields[] = {
+ { GMF_IFG_TX_NOW_ON_TS_TS, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_speed_fields[] = {
+ { GMF_SPEED_IFG_SPEED, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_stat_data_buffer_fields[] = {
+ { GMF_STAT_DATA_BUFFER_USED, 15, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s gmf_stat_max_delayed_pkt_fields[] = {
+ { GMF_STAT_MAX_DELAYED_PKT_NS, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_stat_next_pkt_fields[] = {
+ { GMF_STAT_NEXT_PKT_NS, 64, 0, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_stat_sticky_fields[] = {
+ { GMF_STAT_STICKY_DATA_UNDERFLOWED, 1, 0, 0 },
+ { GMF_STAT_STICKY_IFG_ADJUSTED, 1, 1, 0 },
+};
+
+static nthw_fpga_field_init_s gmf_ts_inject_fields[] = {
+ { GMF_TS_INJECT_OFFSET, 14, 0, 0 },
+ { GMF_TS_INJECT_POS, 2, 14, 0 },
+};
+
+static nthw_fpga_register_init_s gmf_registers[] = {
+ { GMF_CTRL, 0, 10, NTHW_FPGA_REG_TYPE_WO, 0, 10, gmf_ctrl_fields },
+ {
+ GMF_DEBUG_LANE_MARKER, 7, 16, NTHW_FPGA_REG_TYPE_WO, 16384, 1,
+ gmf_debug_lane_marker_fields
+ },
+ {
+ GMF_IFG_MAX_ADJUST_SLACK, 4, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+ gmf_ifg_max_adjust_slack_fields
+ },
+ {
+ GMF_IFG_SET_CLOCK_DELTA, 2, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+ gmf_ifg_set_clock_delta_fields
+ },
+ {
+ GMF_IFG_SET_CLOCK_DELTA_ADJUST, 3, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1,
+ gmf_ifg_set_clock_delta_adjust_fields
+ },
+ { GMF_IFG_TX_NOW_ON_TS, 5, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1, gmf_ifg_tx_now_on_ts_fields },
+ { GMF_SPEED, 1, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1, gmf_speed_fields },
+ { GMF_STAT_DATA_BUFFER, 9, 15, NTHW_FPGA_REG_TYPE_RO, 0, 1, gmf_stat_data_buffer_fields },
+ {
+ GMF_STAT_MAX_DELAYED_PKT, 11, 64, NTHW_FPGA_REG_TYPE_RC1, 0, 1,
+ gmf_stat_max_delayed_pkt_fields
+ },
+ { GMF_STAT_NEXT_PKT, 10, 64, NTHW_FPGA_REG_TYPE_RO, 0, 1, gmf_stat_next_pkt_fields },
+ { GMF_STAT_STICKY, 8, 2, NTHW_FPGA_REG_TYPE_RC1, 0, 2, gmf_stat_sticky_fields },
+ { GMF_TS_INJECT, 6, 16, NTHW_FPGA_REG_TYPE_WO, 0, 2, gmf_ts_inject_fields },
+};
+
+static nthw_fpga_field_init_s gpio_phy_cfg_fields[] = {
+ { GPIO_PHY_CFG_E_PORT0_RXLOS, 1, 8, 0 }, { GPIO_PHY_CFG_E_PORT1_RXLOS, 1, 9, 0 },
+ { GPIO_PHY_CFG_PORT0_INT_B, 1, 1, 1 }, { GPIO_PHY_CFG_PORT0_LPMODE, 1, 0, 0 },
+ { GPIO_PHY_CFG_PORT0_MODPRS_B, 1, 3, 1 }, { GPIO_PHY_CFG_PORT0_RESET_B, 1, 2, 0 },
+ { GPIO_PHY_CFG_PORT1_INT_B, 1, 5, 1 }, { GPIO_PHY_CFG_PORT1_LPMODE, 1, 4, 0 },
+ { GPIO_PHY_CFG_PORT1_MODPRS_B, 1, 7, 1 }, { GPIO_PHY_CFG_PORT1_RESET_B, 1, 6, 0 },
+};
+
+static nthw_fpga_field_init_s gpio_phy_gpio_fields[] = {
+ { GPIO_PHY_GPIO_E_PORT0_RXLOS, 1, 8, 0 }, { GPIO_PHY_GPIO_E_PORT1_RXLOS, 1, 9, 0 },
+ { GPIO_PHY_GPIO_PORT0_INT_B, 1, 1, 0x0000 }, { GPIO_PHY_GPIO_PORT0_LPMODE, 1, 0, 1 },
+ { GPIO_PHY_GPIO_PORT0_MODPRS_B, 1, 3, 0x0000 }, { GPIO_PHY_GPIO_PORT0_RESET_B, 1, 2, 0 },
+ { GPIO_PHY_GPIO_PORT1_INT_B, 1, 5, 0x0000 }, { GPIO_PHY_GPIO_PORT1_LPMODE, 1, 4, 1 },
+ { GPIO_PHY_GPIO_PORT1_MODPRS_B, 1, 7, 0x0000 }, { GPIO_PHY_GPIO_PORT1_RESET_B, 1, 6, 0 },
+};
+
+static nthw_fpga_register_init_s gpio_phy_registers[] = {
+ { GPIO_PHY_CFG, 0, 10, NTHW_FPGA_REG_TYPE_RW, 170, 10, gpio_phy_cfg_fields },
+ { GPIO_PHY_GPIO, 1, 10, NTHW_FPGA_REG_TYPE_RW, 17, 10, gpio_phy_gpio_fields },
+};
+
+static nthw_fpga_field_init_s hif_build_time_fields[] = {
+ { HIF_BUILD_TIME_TIME, 32, 0, 1713859545 },
+};
+
+static nthw_fpga_field_init_s hif_config_fields[] = {
+ { HIF_CONFIG_EXT_TAG, 1, 6, 0x0000 },
+ { HIF_CONFIG_MAX_READ, 3, 3, 0x0000 },
+ { HIF_CONFIG_MAX_TLP, 3, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s hif_control_fields[] = {
+ { HIF_CONTROL_BLESSED, 8, 4, 0 },
+ { HIF_CONTROL_FSR, 1, 12, 1 },
+ { HIF_CONTROL_WRAW, 4, 0, 1 },
+};
+
+static nthw_fpga_field_init_s hif_prod_id_ex_fields[] = {
+ { HIF_PROD_ID_EX_LAYOUT, 1, 31, 0 },
+ { HIF_PROD_ID_EX_LAYOUT_VERSION, 8, 0, 1 },
+ { HIF_PROD_ID_EX_RESERVED, 23, 8, 0 },
+};
+
+static nthw_fpga_field_init_s hif_prod_id_lsb_fields[] = {
+ { HIF_PROD_ID_LSB_GROUP_ID, 16, 16, 9563 },
+ { HIF_PROD_ID_LSB_REV_ID, 8, 0, 39 },
+ { HIF_PROD_ID_LSB_VER_ID, 8, 8, 55 },
+};
+
+static nthw_fpga_field_init_s hif_prod_id_msb_fields[] = {
+ { HIF_PROD_ID_MSB_BUILD_NO, 10, 12, 0 },
+ { HIF_PROD_ID_MSB_TYPE_ID, 12, 0, 200 },
+};
+
+static nthw_fpga_field_init_s hif_sample_time_fields[] = {
+ { HIF_SAMPLE_TIME_SAMPLE_TIME, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s hif_status_fields[] = {
+ { HIF_STATUS_RD_ERR, 1, 9, 0 },
+ { HIF_STATUS_TAGS_IN_USE, 8, 0, 0 },
+ { HIF_STATUS_WR_ERR, 1, 8, 0 },
+};
+
+static nthw_fpga_field_init_s hif_stat_ctrl_fields[] = {
+ { HIF_STAT_CTRL_STAT_ENA, 1, 1, 0 },
+ { HIF_STAT_CTRL_STAT_REQ, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s hif_stat_refclk_fields[] = {
+ { HIF_STAT_REFCLK_REFCLK250, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s hif_stat_rx_fields[] = {
+ { HIF_STAT_RX_COUNTER, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s hif_stat_tx_fields[] = {
+ { HIF_STAT_TX_COUNTER, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s hif_test0_fields[] = {
+ { HIF_TEST0_DATA, 32, 0, 287454020 },
+};
+
+static nthw_fpga_field_init_s hif_test1_fields[] = {
+ { HIF_TEST1_DATA, 32, 0, 2864434397 },
+};
+
+static nthw_fpga_field_init_s hif_uuid0_fields[] = {
+ { HIF_UUID0_UUID0, 32, 0, 1237800326 },
+};
+
+static nthw_fpga_field_init_s hif_uuid1_fields[] = {
+ { HIF_UUID1_UUID1, 32, 0, 3057550372 },
+};
+
+static nthw_fpga_field_init_s hif_uuid2_fields[] = {
+ { HIF_UUID2_UUID2, 32, 0, 2445752330 },
+};
+
+static nthw_fpga_field_init_s hif_uuid3_fields[] = {
+ { HIF_UUID3_UUID3, 32, 0, 1864147557 },
+};
+
+static nthw_fpga_register_init_s hif_registers[] = {
+ { HIF_BUILD_TIME, 16, 32, NTHW_FPGA_REG_TYPE_RO, 1713859545, 1, hif_build_time_fields },
+ { HIF_CONFIG, 24, 7, NTHW_FPGA_REG_TYPE_RW, 0, 3, hif_config_fields },
+ { HIF_CONTROL, 40, 13, NTHW_FPGA_REG_TYPE_MIXED, 4097, 3, hif_control_fields },
+ { HIF_PROD_ID_EX, 112, 32, NTHW_FPGA_REG_TYPE_RO, 1, 3, hif_prod_id_ex_fields },
+ { HIF_PROD_ID_LSB, 0, 32, NTHW_FPGA_REG_TYPE_RO, 626734887, 3, hif_prod_id_lsb_fields },
+ { HIF_PROD_ID_MSB, 8, 22, NTHW_FPGA_REG_TYPE_RO, 200, 2, hif_prod_id_msb_fields },
+ { HIF_SAMPLE_TIME, 96, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, hif_sample_time_fields },
+ { HIF_STATUS, 32, 10, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, hif_status_fields },
+ { HIF_STAT_CTRL, 64, 2, NTHW_FPGA_REG_TYPE_WO, 0, 2, hif_stat_ctrl_fields },
+ { HIF_STAT_REFCLK, 72, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, hif_stat_refclk_fields },
+ { HIF_STAT_RX, 88, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, hif_stat_rx_fields },
+ { HIF_STAT_TX, 80, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, hif_stat_tx_fields },
+ { HIF_TEST0, 48, 32, NTHW_FPGA_REG_TYPE_RW, 287454020, 1, hif_test0_fields },
+ { HIF_TEST1, 56, 32, NTHW_FPGA_REG_TYPE_RW, 2864434397, 1, hif_test1_fields },
+ { HIF_UUID0, 128, 32, NTHW_FPGA_REG_TYPE_RO, 1237800326, 1, hif_uuid0_fields },
+ { HIF_UUID1, 144, 32, NTHW_FPGA_REG_TYPE_RO, 3057550372, 1, hif_uuid1_fields },
+ { HIF_UUID2, 160, 32, NTHW_FPGA_REG_TYPE_RO, 2445752330, 1, hif_uuid2_fields },
+ { HIF_UUID3, 176, 32, NTHW_FPGA_REG_TYPE_RO, 1864147557, 1, hif_uuid3_fields },
+};
+
+static nthw_fpga_field_init_s iic_adr_fields[] = {
+ { IIC_ADR_SLV_ADR, 7, 1, 0 },
+};
+
+static nthw_fpga_field_init_s iic_cr_fields[] = {
+ { IIC_CR_EN, 1, 0, 0 }, { IIC_CR_GC_EN, 1, 6, 0 }, { IIC_CR_MSMS, 1, 2, 0 },
+ { IIC_CR_RST, 1, 7, 0 }, { IIC_CR_RSTA, 1, 5, 0 }, { IIC_CR_TX, 1, 3, 0 },
+ { IIC_CR_TXAK, 1, 4, 0 }, { IIC_CR_TXFIFO_RESET, 1, 1, 0 },
+};
+
+static nthw_fpga_field_init_s iic_dgie_fields[] = {
+ { IIC_DGIE_GIE, 1, 31, 0 },
+};
+
+static nthw_fpga_field_init_s iic_gpo_fields[] = {
+ { IIC_GPO_GPO_VAL, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_ier_fields[] = {
+ { IIC_IER_INT0, 1, 0, 0 }, { IIC_IER_INT1, 1, 1, 0 }, { IIC_IER_INT2, 1, 2, 0 },
+ { IIC_IER_INT3, 1, 3, 0 }, { IIC_IER_INT4, 1, 4, 0 }, { IIC_IER_INT5, 1, 5, 0 },
+ { IIC_IER_INT6, 1, 6, 0 }, { IIC_IER_INT7, 1, 7, 0 },
+};
+
+static nthw_fpga_field_init_s iic_isr_fields[] = {
+ { IIC_ISR_INT0, 1, 0, 0 }, { IIC_ISR_INT1, 1, 1, 0 }, { IIC_ISR_INT2, 1, 2, 0 },
+ { IIC_ISR_INT3, 1, 3, 0 }, { IIC_ISR_INT4, 1, 4, 0 }, { IIC_ISR_INT5, 1, 5, 0 },
+ { IIC_ISR_INT6, 1, 6, 0 }, { IIC_ISR_INT7, 1, 7, 0 },
+};
+
+static nthw_fpga_field_init_s iic_rx_fifo_fields[] = {
+ { IIC_RX_FIFO_RXDATA, 8, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_rx_fifo_ocy_fields[] = {
+ { IIC_RX_FIFO_OCY_OCY_VAL, 4, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_rx_fifo_pirq_fields[] = {
+ { IIC_RX_FIFO_PIRQ_CMP_VAL, 4, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_softr_fields[] = {
+ { IIC_SOFTR_RKEY, 4, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s iic_sr_fields[] = {
+ { IIC_SR_AAS, 1, 1, 0 }, { IIC_SR_ABGC, 1, 0, 0 }, { IIC_SR_BB, 1, 2, 0 },
+ { IIC_SR_RXFIFO_EMPTY, 1, 6, 1 }, { IIC_SR_RXFIFO_FULL, 1, 5, 0 }, { IIC_SR_SRW, 1, 3, 0 },
+ { IIC_SR_TXFIFO_EMPTY, 1, 7, 1 }, { IIC_SR_TXFIFO_FULL, 1, 4, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tbuf_fields[] = {
+ { IIC_TBUF_TBUF_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_ten_adr_fields[] = {
+ { IIC_TEN_ADR_MSB_SLV_ADR, 3, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_thddat_fields[] = {
+ { IIC_THDDAT_THDDAT_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_thdsta_fields[] = {
+ { IIC_THDSTA_THDSTA_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_thigh_fields[] = {
+ { IIC_THIGH_THIGH_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tlow_fields[] = {
+ { IIC_TLOW_TLOW_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tsudat_fields[] = {
+ { IIC_TSUDAT_TSUDAT_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tsusta_fields[] = {
+ { IIC_TSUSTA_TSUSTA_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tsusto_fields[] = {
+ { IIC_TSUSTO_TSUSTO_VAL, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tx_fifo_fields[] = {
+ { IIC_TX_FIFO_START, 1, 8, 0 },
+ { IIC_TX_FIFO_STOP, 1, 9, 0 },
+ { IIC_TX_FIFO_TXDATA, 8, 0, 0 },
+};
+
+static nthw_fpga_field_init_s iic_tx_fifo_ocy_fields[] = {
+ { IIC_TX_FIFO_OCY_OCY_VAL, 4, 0, 0 },
+};
+
+static nthw_fpga_register_init_s iic_registers[] = {
+ { IIC_ADR, 68, 8, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_adr_fields },
+ { IIC_CR, 64, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_cr_fields },
+ { IIC_DGIE, 7, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_dgie_fields },
+ { IIC_GPO, 73, 1, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_gpo_fields },
+ { IIC_IER, 10, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_ier_fields },
+ { IIC_ISR, 8, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_isr_fields },
+ { IIC_RX_FIFO, 67, 8, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_rx_fifo_fields },
+ { IIC_RX_FIFO_OCY, 70, 4, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_rx_fifo_ocy_fields },
+ { IIC_RX_FIFO_PIRQ, 72, 4, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_rx_fifo_pirq_fields },
+ { IIC_SOFTR, 16, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, iic_softr_fields },
+ { IIC_SR, 65, 8, NTHW_FPGA_REG_TYPE_RO, 192, 8, iic_sr_fields },
+ { IIC_TBUF, 78, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tbuf_fields },
+ { IIC_TEN_ADR, 71, 3, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_ten_adr_fields },
+ { IIC_THDDAT, 81, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_thddat_fields },
+ { IIC_THDSTA, 76, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_thdsta_fields },
+ { IIC_THIGH, 79, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_thigh_fields },
+ { IIC_TLOW, 80, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tlow_fields },
+ { IIC_TSUDAT, 77, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tsudat_fields },
+ { IIC_TSUSTA, 74, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tsusta_fields },
+ { IIC_TSUSTO, 75, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tsusto_fields },
+ { IIC_TX_FIFO, 66, 10, NTHW_FPGA_REG_TYPE_WO, 0, 3, iic_tx_fifo_fields },
+ { IIC_TX_FIFO_OCY, 69, 4, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_tx_fifo_ocy_fields },
+};
+
+static nthw_fpga_field_init_s mac_pcs_bad_code_fields[] = {
+ { MAC_PCS_BAD_CODE_CODE_ERR, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_bip_err_fields[] = {
+ { MAC_PCS_BIP_ERR_BIP_ERR, 640, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_block_lock_fields[] = {
+ { MAC_PCS_BLOCK_LOCK_LOCK, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_block_lock_chg_fields[] = {
+ { MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_debounce_ctrl_fields[] = {
+ { MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY, 8, 8, 10 },
+ { MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN, 1, 16, 0 },
+ { MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY, 8, 0, 10 },
+ { MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL, 2, 17, 2 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_drp_ctrl_fields[] = {
+ { MAC_PCS_DRP_CTRL_ADR, 10, 16, 0 }, { MAC_PCS_DRP_CTRL_DATA, 16, 0, 0 },
+ { MAC_PCS_DRP_CTRL_DBG_BUSY, 1, 30, 0x0000 }, { MAC_PCS_DRP_CTRL_DONE, 1, 31, 0x0000 },
+ { MAC_PCS_DRP_CTRL_MOD_ADR, 3, 26, 0 }, { MAC_PCS_DRP_CTRL_WREN, 1, 29, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_ctrl_fields[] = {
+ { MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN, 5, 0, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_cw_cnt_fields[] = {
+ { MAC_PCS_FEC_CW_CNT_CW_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_0_fields[] = {
+ { MAC_PCS_FEC_ERR_CNT_0_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_1_fields[] = {
+ { MAC_PCS_FEC_ERR_CNT_1_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_2_fields[] = {
+ { MAC_PCS_FEC_ERR_CNT_2_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_3_fields[] = {
+ { MAC_PCS_FEC_ERR_CNT_3_ERR_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_0_fields[] = {
+ { MAC_PCS_FEC_LANE_DLY_0_DLY, 14, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_1_fields[] = {
+ { MAC_PCS_FEC_LANE_DLY_1_DLY, 14, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_2_fields[] = {
+ { MAC_PCS_FEC_LANE_DLY_2_DLY, 14, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_3_fields[] = {
+ { MAC_PCS_FEC_LANE_DLY_3_DLY, 14, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_lane_map_fields[] = {
+ { MAC_PCS_FEC_LANE_MAP_MAPPING, 8, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_stat_fields[] = {
+ { MAC_PCS_FEC_STAT_AM_LOCK, 1, 10, 0x0000 },
+ { MAC_PCS_FEC_STAT_AM_LOCK_0, 1, 3, 0x0000 },
+ { MAC_PCS_FEC_STAT_AM_LOCK_1, 1, 4, 0x0000 },
+ { MAC_PCS_FEC_STAT_AM_LOCK_2, 1, 5, 0x0000 },
+ { MAC_PCS_FEC_STAT_AM_LOCK_3, 1, 6, 0x0000 },
+ { MAC_PCS_FEC_STAT_BLOCK_LOCK, 1, 9, 0x0000 },
+ { MAC_PCS_FEC_STAT_BYPASS, 1, 0, 0x0000 },
+ { MAC_PCS_FEC_STAT_FEC_LANE_ALGN, 1, 7, 0x0000 },
+ { MAC_PCS_FEC_STAT_HI_SER, 1, 2, 0x0000 },
+ { MAC_PCS_FEC_STAT_PCS_LANE_ALGN, 1, 8, 0x0000 },
+ { MAC_PCS_FEC_STAT_VALID, 1, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_fec_ucw_cnt_fields[] = {
+ { MAC_PCS_FEC_UCW_CNT_UCW_CNT, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_ctl_rx_fields[] = {
+ { MAC_PCS_GTY_CTL_RX_CDR_HOLD_0, 1, 24, 0 }, { MAC_PCS_GTY_CTL_RX_CDR_HOLD_1, 1, 25, 0 },
+ { MAC_PCS_GTY_CTL_RX_CDR_HOLD_2, 1, 26, 0 }, { MAC_PCS_GTY_CTL_RX_CDR_HOLD_3, 1, 27, 0 },
+ { MAC_PCS_GTY_CTL_RX_EQUA_RST_0, 1, 20, 0 }, { MAC_PCS_GTY_CTL_RX_EQUA_RST_1, 1, 21, 0 },
+ { MAC_PCS_GTY_CTL_RX_EQUA_RST_2, 1, 22, 0 }, { MAC_PCS_GTY_CTL_RX_EQUA_RST_3, 1, 23, 0 },
+ { MAC_PCS_GTY_CTL_RX_LPM_EN_0, 1, 16, 0 }, { MAC_PCS_GTY_CTL_RX_LPM_EN_1, 1, 17, 0 },
+ { MAC_PCS_GTY_CTL_RX_LPM_EN_2, 1, 18, 0 }, { MAC_PCS_GTY_CTL_RX_LPM_EN_3, 1, 19, 0 },
+ { MAC_PCS_GTY_CTL_RX_POLARITY_0, 1, 0, 0 }, { MAC_PCS_GTY_CTL_RX_POLARITY_1, 1, 1, 0 },
+ { MAC_PCS_GTY_CTL_RX_POLARITY_2, 1, 2, 0 }, { MAC_PCS_GTY_CTL_RX_POLARITY_3, 1, 3, 0 },
+ { MAC_PCS_GTY_CTL_RX_RATE_0, 3, 4, 0 }, { MAC_PCS_GTY_CTL_RX_RATE_1, 3, 7, 0 },
+ { MAC_PCS_GTY_CTL_RX_RATE_2, 3, 10, 0 }, { MAC_PCS_GTY_CTL_RX_RATE_3, 3, 13, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_ctl_tx_fields[] = {
+ { MAC_PCS_GTY_CTL_TX_INHIBIT_0, 1, 4, 0 }, { MAC_PCS_GTY_CTL_TX_INHIBIT_1, 1, 5, 0 },
+ { MAC_PCS_GTY_CTL_TX_INHIBIT_2, 1, 6, 0 }, { MAC_PCS_GTY_CTL_TX_INHIBIT_3, 1, 7, 0 },
+ { MAC_PCS_GTY_CTL_TX_POLARITY_0, 1, 0, 0 }, { MAC_PCS_GTY_CTL_TX_POLARITY_1, 1, 1, 0 },
+ { MAC_PCS_GTY_CTL_TX_POLARITY_2, 1, 2, 0 }, { MAC_PCS_GTY_CTL_TX_POLARITY_3, 1, 3, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_diff_ctl_fields[] = {
+ { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0, 5, 0, 24 },
+ { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1, 5, 5, 24 },
+ { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2, 5, 10, 24 },
+ { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3, 5, 15, 24 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_loop_fields[] = {
+ { MAC_PCS_GTY_LOOP_GT_LOOP_0, 3, 0, 0 },
+ { MAC_PCS_GTY_LOOP_GT_LOOP_1, 3, 3, 0 },
+ { MAC_PCS_GTY_LOOP_GT_LOOP_2, 3, 6, 0 },
+ { MAC_PCS_GTY_LOOP_GT_LOOP_3, 3, 9, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_post_cursor_fields[] = {
+ { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0, 5, 0, 20 },
+ { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1, 5, 5, 20 },
+ { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2, 5, 10, 20 },
+ { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3, 5, 15, 20 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_prbs_sel_fields[] = {
+ { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0, 4, 16, 0 },
+ { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1, 4, 20, 0 },
+ { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2, 4, 24, 0 },
+ { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3, 4, 28, 0 },
+ { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0, 4, 0, 0 },
+ { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1, 4, 4, 0 },
+ { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2, 4, 8, 0 },
+ { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3, 4, 12, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_pre_cursor_fields[] = {
+ { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0, 5, 0, 0 },
+ { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1, 5, 5, 0 },
+ { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2, 5, 10, 0 },
+ { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3, 5, 15, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_rx_buf_stat_fields[] = {
+ { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0, 3, 0, 0x0000 },
+ { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1, 3, 3, 0x0000 },
+ { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2, 3, 6, 0x0000 },
+ { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3, 3, 9, 0x0000 },
+ { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0, 3, 12, 0x0000 },
+ { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1, 3, 15, 0x0000 },
+ { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2, 3, 18, 0x0000 },
+ { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3, 3, 21, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_scan_ctl_fields[] = {
+ { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0, 1, 0, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1, 1, 1, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2, 1, 2, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3, 1, 3, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0, 1, 4, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1, 1, 5, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2, 1, 6, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3, 1, 7, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0, 1, 12, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1, 1, 13, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2, 1, 14, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3, 1, 15, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0, 1, 8, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1, 1, 9, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2, 1, 10, 0 },
+ { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3, 1, 11, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_scan_stat_fields[] = {
+ { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0, 1, 0, 0x0000 },
+ { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1, 1, 1, 0x0000 },
+ { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2, 1, 2, 0x0000 },
+ { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3, 1, 3, 0x0000 },
+ { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0, 1, 4, 0x0000 },
+ { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1, 1, 5, 0x0000 },
+ { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2, 1, 6, 0x0000 },
+ { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3, 1, 7, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_gty_stat_fields[] = {
+ { MAC_PCS_GTY_STAT_RX_RST_DONE_0, 1, 4, 0x0000 },
+ { MAC_PCS_GTY_STAT_RX_RST_DONE_1, 1, 5, 0x0000 },
+ { MAC_PCS_GTY_STAT_RX_RST_DONE_2, 1, 6, 0x0000 },
+ { MAC_PCS_GTY_STAT_RX_RST_DONE_3, 1, 7, 0x0000 },
+ { MAC_PCS_GTY_STAT_TX_BUF_STAT_0, 2, 8, 0x0000 },
+ { MAC_PCS_GTY_STAT_TX_BUF_STAT_1, 2, 10, 0x0000 },
+ { MAC_PCS_GTY_STAT_TX_BUF_STAT_2, 2, 12, 0x0000 },
+ { MAC_PCS_GTY_STAT_TX_BUF_STAT_3, 2, 14, 0x0000 },
+ { MAC_PCS_GTY_STAT_TX_RST_DONE_0, 1, 0, 0x0000 },
+ { MAC_PCS_GTY_STAT_TX_RST_DONE_1, 1, 1, 0x0000 },
+ { MAC_PCS_GTY_STAT_TX_RST_DONE_2, 1, 2, 0x0000 },
+ { MAC_PCS_GTY_STAT_TX_RST_DONE_3, 1, 3, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_link_summary_fields[] = {
+ { MAC_PCS_LINK_SUMMARY_ABS, 1, 0, 0x0000 },
+ { MAC_PCS_LINK_SUMMARY_LH_ABS, 1, 2, 0x0000 },
+ { MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT, 1, 13, 0 },
+ { MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT, 1, 14, 0 },
+ { MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT, 8, 4, 0 },
+ { MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE, 1, 3, 0x0000 },
+ { MAC_PCS_LINK_SUMMARY_LOCAL_FAULT, 1, 17, 0x0000 },
+ { MAC_PCS_LINK_SUMMARY_NIM_INTERR, 1, 12, 0x0000 },
+ { MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE, 1, 1, 0x0000 },
+ { MAC_PCS_LINK_SUMMARY_REMOTE_FAULT, 1, 18, 0x0000 },
+ { MAC_PCS_LINK_SUMMARY_RESERVED, 2, 15, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_mac_pcs_config_fields[] = {
+ { MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST, 1, 3, 0 },
+ { MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE, 1, 5, 0 },
+ { MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC, 1, 6, 0 },
+ { MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST, 1, 1, 0 },
+ { MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN, 1, 7, 0 },
+ { MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST, 1, 2, 0 },
+ { MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE, 1, 8, 1 },
+ { MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE, 1, 4, 1 },
+ { MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST, 1, 0, 0 },
+ { MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE, 1, 9, 0 },
+ { MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI, 1, 10, 0 },
+ { MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN, 1, 11, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_max_pkt_len_fields[] = {
+ { MAC_PCS_MAX_PKT_LEN_MAX_LEN, 14, 0, 10000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_phymac_misc_fields[] = {
+ { MAC_PCS_PHYMAC_MISC_TS_EOP, 1, 3, 1 },
+ { MAC_PCS_PHYMAC_MISC_TX_MUX_STATE, 4, 4, 0x0000 },
+ { MAC_PCS_PHYMAC_MISC_TX_SEL_HOST, 1, 0, 1 },
+ { MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP, 1, 2, 0 },
+ { MAC_PCS_PHYMAC_MISC_TX_SEL_TFG, 1, 1, 0 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_phy_stat_fields[] = {
+ { MAC_PCS_PHY_STAT_ALARM, 1, 2, 0x0000 },
+ { MAC_PCS_PHY_STAT_MOD_PRS, 1, 1, 0x0000 },
+ { MAC_PCS_PHY_STAT_RX_LOS, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_stat_pcs_rx_fields[] = {
+ { MAC_PCS_STAT_PCS_RX_ALIGNED, 1, 1, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_ALIGNED_ERR, 1, 2, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS, 1, 9, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_HI_BER, 1, 8, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT, 1, 4, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_LOCAL_FAULT, 1, 6, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_MISALIGNED, 1, 3, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT, 1, 5, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_REMOTE_FAULT, 1, 7, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_STATUS, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_stat_pcs_rx_latch_fields[] = {
+ { MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED, 1, 1, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR, 1, 2, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS, 1, 9, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_LATCH_HI_BER, 1, 8, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT, 1, 4, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT, 1, 6, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED, 1, 3, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT, 1, 5, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT, 1, 7, 0x0000 },
+ { MAC_PCS_STAT_PCS_RX_LATCH_STATUS, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_stat_pcs_tx_fields[] = {
+ { MAC_PCS_STAT_PCS_TX_LOCAL_FAULT, 1, 0, 0x0000 },
+ { MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED, 1, 5, 0x0000 },
+ { MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR, 1, 4, 0x0000 },
+ { MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED, 1, 9, 0x0000 },
+ { MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR, 1, 3, 0x0000 },
+ { MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED, 1, 8, 0x0000 },
+ { MAC_PCS_STAT_PCS_TX_TX_OVFOUT, 1, 2, 0x0000 },
+ { MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED, 1, 7, 0x0000 },
+ { MAC_PCS_STAT_PCS_TX_TX_UNFOUT, 1, 1, 0x0000 },
+ { MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED, 1, 6, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_synced_fields[] = {
+ { MAC_PCS_SYNCED_SYNC, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_synced_err_fields[] = {
+ { MAC_PCS_SYNCED_ERR_SYNC_ERROR, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_test_err_fields[] = {
+ { MAC_PCS_TEST_ERR_CODE_ERR, 16, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_timestamp_comp_fields[] = {
+ { MAC_PCS_TIMESTAMP_COMP_RX_DLY, 16, 0, 1451 },
+ { MAC_PCS_TIMESTAMP_COMP_TX_DLY, 16, 16, 1440 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_vl_demuxed_fields[] = {
+ { MAC_PCS_VL_DEMUXED_LOCK, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s mac_pcs_vl_demuxed_chg_fields[] = {
+ { MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG, 20, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s mac_pcs_registers[] = {
+ { MAC_PCS_BAD_CODE, 26, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_bad_code_fields },
+ { MAC_PCS_BIP_ERR, 31, 640, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_bip_err_fields },
+ { MAC_PCS_BLOCK_LOCK, 27, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_block_lock_fields },
+ {
+ MAC_PCS_BLOCK_LOCK_CHG, 28, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+ mac_pcs_block_lock_chg_fields
+ },
+ {
+ MAC_PCS_DEBOUNCE_CTRL, 1, 19, NTHW_FPGA_REG_TYPE_RW, 264714, 4,
+ mac_pcs_debounce_ctrl_fields
+ },
+ { MAC_PCS_DRP_CTRL, 43, 32, NTHW_FPGA_REG_TYPE_MIXED, 0, 6, mac_pcs_drp_ctrl_fields },
+ { MAC_PCS_FEC_CTRL, 2, 5, NTHW_FPGA_REG_TYPE_RW, 0, 1, mac_pcs_fec_ctrl_fields },
+ { MAC_PCS_FEC_CW_CNT, 9, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_fec_cw_cnt_fields },
+ {
+ MAC_PCS_FEC_ERR_CNT_0, 11, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+ mac_pcs_fec_err_cnt_0_fields
+ },
+ {
+ MAC_PCS_FEC_ERR_CNT_1, 12, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+ mac_pcs_fec_err_cnt_1_fields
+ },
+ {
+ MAC_PCS_FEC_ERR_CNT_2, 13, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+ mac_pcs_fec_err_cnt_2_fields
+ },
+ {
+ MAC_PCS_FEC_ERR_CNT_3, 14, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+ mac_pcs_fec_err_cnt_3_fields
+ },
+ {
+ MAC_PCS_FEC_LANE_DLY_0, 5, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+ mac_pcs_fec_lane_dly_0_fields
+ },
+ {
+ MAC_PCS_FEC_LANE_DLY_1, 6, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+ mac_pcs_fec_lane_dly_1_fields
+ },
+ {
+ MAC_PCS_FEC_LANE_DLY_2, 7, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+ mac_pcs_fec_lane_dly_2_fields
+ },
+ {
+ MAC_PCS_FEC_LANE_DLY_3, 8, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+ mac_pcs_fec_lane_dly_3_fields
+ },
+ { MAC_PCS_FEC_LANE_MAP, 4, 8, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_fec_lane_map_fields },
+ { MAC_PCS_FEC_STAT, 3, 11, NTHW_FPGA_REG_TYPE_RO, 0, 11, mac_pcs_fec_stat_fields },
+ { MAC_PCS_FEC_UCW_CNT, 10, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_fec_ucw_cnt_fields },
+ { MAC_PCS_GTY_CTL_RX, 38, 28, NTHW_FPGA_REG_TYPE_RW, 0, 20, mac_pcs_gty_ctl_rx_fields },
+ { MAC_PCS_GTY_CTL_TX, 39, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, mac_pcs_gty_ctl_tx_fields },
+ {
+ MAC_PCS_GTY_DIFF_CTL, 35, 20, NTHW_FPGA_REG_TYPE_RW, 811800, 4,
+ mac_pcs_gty_diff_ctl_fields
+ },
+ { MAC_PCS_GTY_LOOP, 20, 12, NTHW_FPGA_REG_TYPE_RW, 0, 4, mac_pcs_gty_loop_fields },
+ {
+ MAC_PCS_GTY_POST_CURSOR, 36, 20, NTHW_FPGA_REG_TYPE_RW, 676500, 4,
+ mac_pcs_gty_post_cursor_fields
+ },
+ { MAC_PCS_GTY_PRBS_SEL, 40, 32, NTHW_FPGA_REG_TYPE_RW, 0, 8, mac_pcs_gty_prbs_sel_fields },
+ {
+ MAC_PCS_GTY_PRE_CURSOR, 37, 20, NTHW_FPGA_REG_TYPE_RW, 0, 4,
+ mac_pcs_gty_pre_cursor_fields
+ },
+ {
+ MAC_PCS_GTY_RX_BUF_STAT, 34, 24, NTHW_FPGA_REG_TYPE_RO, 0, 8,
+ mac_pcs_gty_rx_buf_stat_fields
+ },
+ {
+ MAC_PCS_GTY_SCAN_CTL, 41, 16, NTHW_FPGA_REG_TYPE_RW, 0, 16,
+ mac_pcs_gty_scan_ctl_fields
+ },
+ {
+ MAC_PCS_GTY_SCAN_STAT, 42, 8, NTHW_FPGA_REG_TYPE_RO, 0, 8,
+ mac_pcs_gty_scan_stat_fields
+ },
+ { MAC_PCS_GTY_STAT, 33, 16, NTHW_FPGA_REG_TYPE_RO, 0, 12, mac_pcs_gty_stat_fields },
+ { MAC_PCS_LINK_SUMMARY, 0, 19, NTHW_FPGA_REG_TYPE_RO, 0, 11, mac_pcs_link_summary_fields },
+ {
+ MAC_PCS_MAC_PCS_CONFIG, 19, 12, NTHW_FPGA_REG_TYPE_RW, 272, 12,
+ mac_pcs_mac_pcs_config_fields
+ },
+ {
+ MAC_PCS_MAX_PKT_LEN, 17, 14, NTHW_FPGA_REG_TYPE_RW, 10000, 1,
+ mac_pcs_max_pkt_len_fields
+ },
+ { MAC_PCS_PHYMAC_MISC, 16, 8, NTHW_FPGA_REG_TYPE_MIXED, 9, 5, mac_pcs_phymac_misc_fields },
+ { MAC_PCS_PHY_STAT, 15, 3, NTHW_FPGA_REG_TYPE_RO, 0, 3, mac_pcs_phy_stat_fields },
+ { MAC_PCS_STAT_PCS_RX, 21, 10, NTHW_FPGA_REG_TYPE_RO, 0, 10, mac_pcs_stat_pcs_rx_fields },
+ {
+ MAC_PCS_STAT_PCS_RX_LATCH, 22, 10, NTHW_FPGA_REG_TYPE_RO, 0, 10,
+ mac_pcs_stat_pcs_rx_latch_fields
+ },
+ { MAC_PCS_STAT_PCS_TX, 23, 10, NTHW_FPGA_REG_TYPE_RO, 0, 10, mac_pcs_stat_pcs_tx_fields },
+ { MAC_PCS_SYNCED, 24, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_synced_fields },
+ { MAC_PCS_SYNCED_ERR, 25, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_synced_err_fields },
+ { MAC_PCS_TEST_ERR, 32, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_test_err_fields },
+ {
+ MAC_PCS_TIMESTAMP_COMP, 18, 32, NTHW_FPGA_REG_TYPE_RW, 94373291, 2,
+ mac_pcs_timestamp_comp_fields
+ },
+ { MAC_PCS_VL_DEMUXED, 29, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_vl_demuxed_fields },
+ {
+ MAC_PCS_VL_DEMUXED_CHG, 30, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1,
+ mac_pcs_vl_demuxed_chg_fields
+ },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_ctrl_fields[] = {
+ { PCI_RD_TG_TG_CTRL_TG_RD_RDY, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_rdaddr_fields[] = {
+ { PCI_RD_TG_TG_RDADDR_RAM_ADDR, 9, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_rddata0_fields[] = {
+ { PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_rddata1_fields[] = {
+ { PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_rddata2_fields[] = {
+ { PCI_RD_TG_TG_RDDATA2_REQ_HID, 6, 22, 0 },
+ { PCI_RD_TG_TG_RDDATA2_REQ_SIZE, 22, 0, 0 },
+ { PCI_RD_TG_TG_RDDATA2_WAIT, 1, 30, 0 },
+ { PCI_RD_TG_TG_RDDATA2_WRAP, 1, 31, 0 },
+};
+
+static nthw_fpga_field_init_s pci_rd_tg_tg_rd_run_fields[] = {
+ { PCI_RD_TG_TG_RD_RUN_RD_ITERATION, 16, 0, 0 },
+};
+
+static nthw_fpga_register_init_s pci_rd_tg_registers[] = {
+ { PCI_RD_TG_TG_CTRL, 5, 1, NTHW_FPGA_REG_TYPE_RO, 0, 1, pci_rd_tg_tg_ctrl_fields },
+ { PCI_RD_TG_TG_RDADDR, 3, 9, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rdaddr_fields },
+ { PCI_RD_TG_TG_RDDATA0, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rddata0_fields },
+ { PCI_RD_TG_TG_RDDATA1, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rddata1_fields },
+ { PCI_RD_TG_TG_RDDATA2, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 4, pci_rd_tg_tg_rddata2_fields },
+ { PCI_RD_TG_TG_RD_RUN, 4, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rd_run_fields },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_ctrl_fields[] = {
+ { PCI_WR_TG_TG_CTRL_TG_WR_RDY, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_seq_fields[] = {
+ { PCI_WR_TG_TG_SEQ_SEQUENCE, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_wraddr_fields[] = {
+ { PCI_WR_TG_TG_WRADDR_RAM_ADDR, 9, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata0_fields[] = {
+ { PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata1_fields[] = {
+ { PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata2_fields[] = {
+ { PCI_WR_TG_TG_WRDATA2_INC_MODE, 1, 29, 0 }, { PCI_WR_TG_TG_WRDATA2_REQ_HID, 6, 22, 0 },
+ { PCI_WR_TG_TG_WRDATA2_REQ_SIZE, 22, 0, 0 }, { PCI_WR_TG_TG_WRDATA2_WAIT, 1, 30, 0 },
+ { PCI_WR_TG_TG_WRDATA2_WRAP, 1, 31, 0 },
+};
+
+static nthw_fpga_field_init_s pci_wr_tg_tg_wr_run_fields[] = {
+ { PCI_WR_TG_TG_WR_RUN_WR_ITERATION, 16, 0, 0 },
+};
+
+static nthw_fpga_register_init_s pci_wr_tg_registers[] = {
+ { PCI_WR_TG_TG_CTRL, 5, 1, NTHW_FPGA_REG_TYPE_RO, 0, 1, pci_wr_tg_tg_ctrl_fields },
+ { PCI_WR_TG_TG_SEQ, 6, 16, NTHW_FPGA_REG_TYPE_RW, 0, 1, pci_wr_tg_tg_seq_fields },
+ { PCI_WR_TG_TG_WRADDR, 3, 9, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wraddr_fields },
+ { PCI_WR_TG_TG_WRDATA0, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wrdata0_fields },
+ { PCI_WR_TG_TG_WRDATA1, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wrdata1_fields },
+ { PCI_WR_TG_TG_WRDATA2, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 5, pci_wr_tg_tg_wrdata2_fields },
+ { PCI_WR_TG_TG_WR_RUN, 4, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wr_run_fields },
+};
+
+static nthw_fpga_field_init_s rac_dbg_ctrl_fields[] = {
+ { RAC_DBG_CTRL_C, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rac_dbg_data_fields[] = {
+ { RAC_DBG_DATA_D, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rac_rab_buf_free_fields[] = {
+ { RAC_RAB_BUF_FREE_IB_FREE, 9, 0, 511 }, { RAC_RAB_BUF_FREE_IB_OVF, 1, 12, 0 },
+ { RAC_RAB_BUF_FREE_OB_FREE, 9, 16, 511 }, { RAC_RAB_BUF_FREE_OB_OVF, 1, 28, 0 },
+ { RAC_RAB_BUF_FREE_TIMEOUT, 1, 31, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_buf_used_fields[] = {
+ { RAC_RAB_BUF_USED_FLUSH, 1, 31, 0 },
+ { RAC_RAB_BUF_USED_IB_USED, 9, 0, 0 },
+ { RAC_RAB_BUF_USED_OB_USED, 9, 16, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ib_hi_fields[] = {
+ { RAC_RAB_DMA_IB_HI_PHYADDR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ib_lo_fields[] = {
+ { RAC_RAB_DMA_IB_LO_PHYADDR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ib_rd_fields[] = {
+ { RAC_RAB_DMA_IB_RD_PTR, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ib_wr_fields[] = {
+ { RAC_RAB_DMA_IB_WR_PTR, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ob_hi_fields[] = {
+ { RAC_RAB_DMA_OB_HI_PHYADDR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ob_lo_fields[] = {
+ { RAC_RAB_DMA_OB_LO_PHYADDR, 32, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_dma_ob_wr_fields[] = {
+ { RAC_RAB_DMA_OB_WR_PTR, 16, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rac_rab_ib_data_fields[] = {
+ { RAC_RAB_IB_DATA_D, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rac_rab_init_fields[] = {
+ { RAC_RAB_INIT_RAB, 3, 0, 7 },
+};
+
+static nthw_fpga_field_init_s rac_rab_ob_data_fields[] = {
+ { RAC_RAB_OB_DATA_D, 32, 0, 0x0000 },
+};
+
+static nthw_fpga_register_init_s rac_registers[] = {
+ { RAC_DBG_CTRL, 4200, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, rac_dbg_ctrl_fields },
+ { RAC_DBG_DATA, 4208, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, rac_dbg_data_fields },
+ {
+ RAC_RAB_BUF_FREE, 4176, 32, NTHW_FPGA_REG_TYPE_MIXED, 33489407, 5,
+ rac_rab_buf_free_fields
+ },
+ { RAC_RAB_BUF_USED, 4184, 32, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, rac_rab_buf_used_fields },
+ { RAC_RAB_DMA_IB_HI, 4360, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ib_hi_fields },
+ { RAC_RAB_DMA_IB_LO, 4352, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ib_lo_fields },
+ { RAC_RAB_DMA_IB_RD, 4424, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, rac_rab_dma_ib_rd_fields },
+ { RAC_RAB_DMA_IB_WR, 4416, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ib_wr_fields },
+ { RAC_RAB_DMA_OB_HI, 4376, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ob_hi_fields },
+ { RAC_RAB_DMA_OB_LO, 4368, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ob_lo_fields },
+ { RAC_RAB_DMA_OB_WR, 4480, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, rac_rab_dma_ob_wr_fields },
+ { RAC_RAB_IB_DATA, 4160, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_ib_data_fields },
+ { RAC_RAB_INIT, 4192, 3, NTHW_FPGA_REG_TYPE_RW, 7, 1, rac_rab_init_fields },
+ { RAC_RAB_OB_DATA, 4168, 32, NTHW_FPGA_REG_TYPE_RC1, 0, 1, rac_rab_ob_data_fields },
+};
+
+static nthw_fpga_field_init_s rst9563_ctrl_fields[] = {
+ { RST9563_CTRL_PTP_MMCM_CLKSEL, 1, 2, 1 },
+ { RST9563_CTRL_TS_CLKSEL, 1, 1, 1 },
+ { RST9563_CTRL_TS_CLKSEL_OVERRIDE, 1, 0, 1 },
+};
+
+static nthw_fpga_field_init_s rst9563_power_fields[] = {
+ { RST9563_POWER_PU_NSEB, 1, 1, 0 },
+ { RST9563_POWER_PU_PHY, 1, 0, 0 },
+};
+
+static nthw_fpga_field_init_s rst9563_rst_fields[] = {
+ { RST9563_RST_CORE_MMCM, 1, 15, 0 }, { RST9563_RST_DDR4, 3, 3, 7 },
+ { RST9563_RST_MAC_RX, 2, 9, 3 }, { RST9563_RST_PERIPH, 1, 13, 0 },
+ { RST9563_RST_PHY, 2, 7, 3 }, { RST9563_RST_PTP, 1, 11, 1 },
+ { RST9563_RST_PTP_MMCM, 1, 16, 0 }, { RST9563_RST_RPP, 1, 2, 1 },
+ { RST9563_RST_SDC, 1, 6, 1 }, { RST9563_RST_SYS, 1, 0, 1 },
+ { RST9563_RST_SYS_MMCM, 1, 14, 0 }, { RST9563_RST_TMC, 1, 1, 1 },
+ { RST9563_RST_TS, 1, 12, 1 }, { RST9563_RST_TS_MMCM, 1, 17, 0 },
+};
+
+static nthw_fpga_field_init_s rst9563_stat_fields[] = {
+ { RST9563_STAT_CORE_MMCM_LOCKED, 1, 5, 0x0000 },
+ { RST9563_STAT_DDR4_MMCM_LOCKED, 1, 2, 0x0000 },
+ { RST9563_STAT_DDR4_PLL_LOCKED, 1, 3, 0x0000 },
+ { RST9563_STAT_PTP_MMCM_LOCKED, 1, 0, 0x0000 },
+ { RST9563_STAT_SYS_MMCM_LOCKED, 1, 4, 0x0000 },
+ { RST9563_STAT_TS_MMCM_LOCKED, 1, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s rst9563_sticky_fields[] = {
+ { RST9563_STICKY_CORE_MMCM_UNLOCKED, 1, 5, 0x0000 },
+ { RST9563_STICKY_DDR4_MMCM_UNLOCKED, 1, 2, 0x0000 },
+ { RST9563_STICKY_DDR4_PLL_UNLOCKED, 1, 3, 0x0000 },
+ { RST9563_STICKY_PTP_MMCM_UNLOCKED, 1, 0, 0x0000 },
+ { RST9563_STICKY_SYS_MMCM_UNLOCKED, 1, 4, 0x0000 },
+ { RST9563_STICKY_TS_MMCM_UNLOCKED, 1, 1, 0x0000 },
+};
+
+static nthw_fpga_register_init_s rst9563_registers[] = {
+ { RST9563_CTRL, 1, 3, NTHW_FPGA_REG_TYPE_RW, 7, 3, rst9563_ctrl_fields },
+ { RST9563_POWER, 4, 2, NTHW_FPGA_REG_TYPE_RW, 0, 2, rst9563_power_fields },
+ { RST9563_RST, 0, 18, NTHW_FPGA_REG_TYPE_RW, 8191, 14, rst9563_rst_fields },
+ { RST9563_STAT, 2, 6, NTHW_FPGA_REG_TYPE_RO, 0, 6, rst9563_stat_fields },
+ { RST9563_STICKY, 3, 6, NTHW_FPGA_REG_TYPE_RC1, 0, 6, rst9563_sticky_fields },
+};
+
+static nthw_fpga_module_init_s fpga_modules[] = {
+ { MOD_GFG, 0, MOD_GFG, 1, 1, NTHW_FPGA_BUS_TYPE_RAB2, 8704, 10, gfg_registers },
+ { MOD_GMF, 0, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9216, 12, gmf_registers },
+ { MOD_GMF, 1, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9728, 12, gmf_registers },
+ {
+ MOD_GPIO_PHY, 0, MOD_GPIO_PHY, 1, 0, NTHW_FPGA_BUS_TYPE_RAB0, 16386, 2,
+ gpio_phy_registers
+ },
+ { MOD_HIF, 0, MOD_HIF, 0, 0, NTHW_FPGA_BUS_TYPE_PCI, 0, 18, hif_registers },
+ { MOD_IIC, 0, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 768, 22, iic_registers },
+ { MOD_IIC, 1, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 896, 22, iic_registers },
+ { MOD_IIC, 2, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 24832, 22, iic_registers },
+ { MOD_IIC, 3, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 24960, 22, iic_registers },
+ {
+ MOD_MAC_PCS, 0, MOD_MAC_PCS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB2, 10240, 44,
+ mac_pcs_registers
+ },
+ {
+ MOD_MAC_PCS, 1, MOD_MAC_PCS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB2, 11776, 44,
+ mac_pcs_registers
+ },
+ {
+ MOD_PCI_RD_TG, 0, MOD_PCI_RD_TG, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 2320, 6,
+ pci_rd_tg_registers
+ },
+ {
+ MOD_PCI_WR_TG, 0, MOD_PCI_WR_TG, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 2304, 7,
+ pci_wr_tg_registers
+ },
+ { MOD_RAC, 0, MOD_RAC, 3, 0, NTHW_FPGA_BUS_TYPE_PCI, 8192, 14, rac_registers },
+ { MOD_RST9563, 0, MOD_RST9563, 0, 5, NTHW_FPGA_BUS_TYPE_RAB0, 1024, 5, rst9563_registers },
+};
+
+static nthw_fpga_prod_param_s product_parameters[] = {
+ { NT_BUILD_NUMBER, 0 },
+ { NT_BUILD_TIME, 1713859545 },
+ { NT_CATEGORIES, 64 },
+ { NT_CAT_DCT_PRESENT, 0 },
+ { NT_CAT_END_OFS_SUPPORT, 0 },
+ { NT_CAT_FUNCS, 64 },
+ { NT_CAT_KCC_BANKS, 3 },
+ { NT_CAT_KCC_PRESENT, 0 },
+ { NT_CAT_KCC_SIZE, 1536 },
+ { NT_CAT_KM_IF_CNT, 2 },
+ { NT_CAT_KM_IF_M0, 0 },
+ { NT_CAT_KM_IF_M1, 1 },
+ { NT_CAT_N_CMP, 8 },
+ { NT_CAT_N_EXT, 4 },
+ { NT_CAT_N_LEN, 8 },
+ { NT_CB_DEBUG, 0 },
+ { NT_COR_CATEGORIES, 16 },
+ { NT_COR_PRESENT, 0 },
+ { NT_CSU_PRESENT, 1 },
+ { NT_DBS_PRESENT, 1 },
+ { NT_DBS_RX_QUEUES, 128 },
+ { NT_DBS_TX_PORTS, 2 },
+ { NT_DBS_TX_QUEUES, 128 },
+ { NT_DDP_PRESENT, 0 },
+ { NT_DDP_TBL_DEPTH, 4096 },
+ { NT_EMI_SPLIT_STEPS, 16 },
+ { NT_EOF_TIMESTAMP_ONLY, 1 },
+ { NT_EPP_CATEGORIES, 32 },
+ { NT_FLM_CACHE, 1 },
+ { NT_FLM_CATEGORIES, 32 },
+ { NT_FLM_ENTRY_SIZE, 64 },
+ { NT_FLM_LOAD_APS_MAX, 260000000 },
+ { NT_FLM_LOAD_LPS_MAX, 300000000 },
+ { NT_FLM_PRESENT, 1 },
+ { NT_FLM_PRIOS, 4 },
+ { NT_FLM_PST_PROFILES, 16 },
+ { NT_FLM_SCRUB_PROFILES, 16 },
+ { NT_FLM_SIZE_MB, 12288 },
+ { NT_FLM_STATEFUL, 1 },
+ { NT_FLM_VARIANT, 2 },
+ { NT_GFG_PRESENT, 1 },
+ { NT_GFG_TX_LIVE_RECONFIG_SUPPORT, 1 },
+ { NT_GMF_FCS_PRESENT, 0 },
+ { NT_GMF_IFG_SPEED_DIV, 33 },
+ { NT_GMF_IFG_SPEED_DIV100G, 33 },
+ { NT_GMF_IFG_SPEED_MUL, 20 },
+ { NT_GMF_IFG_SPEED_MUL100G, 20 },
+ { NT_GROUP_ID, 9563 },
+ { NT_HFU_PRESENT, 1 },
+ { NT_HIF_MSIX_BAR, 1 },
+ { NT_HIF_MSIX_PBA_OFS, 8192 },
+ { NT_HIF_MSIX_PRESENT, 1 },
+ { NT_HIF_MSIX_TBL_OFS, 0 },
+ { NT_HIF_MSIX_TBL_SIZE, 8 },
+ { NT_HIF_PER_PS, 4000 },
+ { NT_HIF_SRIOV_PRESENT, 1 },
+ { NT_HIF_VF_OFFSET, 4 },
+ { NT_HSH_CATEGORIES, 16 },
+ { NT_HSH_TOEPLITZ, 1 },
+ { NT_HST_CATEGORIES, 32 },
+ { NT_HST_PRESENT, 0 },
+ { NT_IOA_CATEGORIES, 1024 },
+ { NT_IOA_PRESENT, 0 },
+ { NT_IPF_PRESENT, 0 },
+ { NT_KM_CAM_BANKS, 3 },
+ { NT_KM_CAM_RECORDS, 2048 },
+ { NT_KM_CAM_REC_WORDS, 6 },
+ { NT_KM_CATEGORIES, 32 },
+ { NT_KM_END_OFS_SUPPORT, 0 },
+ { NT_KM_EXT_EXTRACTORS, 1 },
+ { NT_KM_FLOW_TYPES, 16 },
+ { NT_KM_PRESENT, 1 },
+ { NT_KM_SWX_PRESENT, 0 },
+ { NT_KM_SYNERGY_MATCH, 0 },
+ { NT_KM_TCAM_BANKS, 12 },
+ { NT_KM_TCAM_BANK_WIDTH, 72 },
+ { NT_KM_TCAM_HIT_QUAL, 0 },
+ { NT_KM_TCAM_KEYWAY, 1 },
+ { NT_KM_WIDE, 1 },
+ { NT_LR_PRESENT, 1 },
+ { NT_MCU_PRESENT, 0 },
+ { NT_MDG_DEBUG_FLOW_CONTROL, 0 },
+ { NT_MDG_DEBUG_REG_READ_BACK, 0 },
+ { NT_MSK_CATEGORIES, 32 },
+ { NT_MSK_PRESENT, 0 },
+ { NT_NFV_OVS_PRODUCT, 0 },
+ { NT_NIMS, 2 },
+ { NT_PCI_DEVICE_ID, 453 },
+ { NT_PCI_TA_TG_PRESENT, 1 },
+ { NT_PCI_VENDOR_ID, 6388 },
+ { NT_PDB_CATEGORIES, 16 },
+ { NT_PHY_ANEG_PRESENT, 0 },
+ { NT_PHY_KRFEC_PRESENT, 0 },
+ { NT_PHY_PORTS, 2 },
+ { NT_PHY_PORTS_PER_QUAD, 1 },
+ { NT_PHY_QUADS, 2 },
+ { NT_PHY_RSFEC_PRESENT, 1 },
+ { NT_QM_CELLS, 2097152 },
+ { NT_QM_CELL_SIZE, 6144 },
+ { NT_QM_PRESENT, 0 },
+ { NT_QSL_CATEGORIES, 32 },
+ { NT_QSL_COLOR_SEL_BW, 7 },
+ { NT_QSL_QST_SIZE, 4096 },
+ { NT_QUEUES, 128 },
+ { NT_RAC_RAB_INTERFACES, 3 },
+ { NT_RAC_RAB_OB_UPDATE, 0 },
+ { NT_REVISION_ID, 39 },
+ { NT_RMC_LAG_GROUPS, 1 },
+ { NT_RMC_PRESENT, 1 },
+ { NT_ROA_CATEGORIES, 1024 },
+ { NT_ROA_PRESENT, 0 },
+ { NT_RPF_MATURING_DEL_DEFAULT, -150 },
+ { NT_RPF_PRESENT, 0 },
+ { NT_RPP_PER_PS, 3333 },
+ { NT_RTX_PRESENT, 0 },
+ { NT_RX_HOST_BUFFERS, 128 },
+ { NT_RX_PORTS, 2 },
+ { NT_RX_PORT_REPLICATE, 0 },
+ { NT_SLB_PRESENT, 0 },
+ { NT_SLC_LR_PRESENT, 1 },
+ { NT_SLC_PRESENT, 0 },
+ { NT_STA_COLORS, 64 },
+ { NT_STA_LOAD_AVG_RX, 1 },
+ { NT_STA_LOAD_AVG_TX, 1 },
+ { NT_STA_RX_PORTS, 2 },
+ { NT_TBH_DEBUG_DLN, 1 },
+ { NT_TBH_PRESENT, 0 },
+ { NT_TFD_PRESENT, 1 },
+ { NT_TPE_CATEGORIES, 16 },
+ { NT_TSM_OST_ONLY, 0 },
+ { NT_TS_APPEND, 0 },
+ { NT_TS_INJECT_PRESENT, 0 },
+ { NT_TX_CPY_PACKET_READERS, 0 },
+ { NT_TX_CPY_PRESENT, 1 },
+ { NT_TX_CPY_SIDEBAND_READERS, 7 },
+ { NT_TX_CPY_VARIANT, 0 },
+ { NT_TX_CPY_WRITERS, 6 },
+ { NT_TX_HOST_BUFFERS, 128 },
+ { NT_TX_INS_OFS_ZERO, 1 },
+ { NT_TX_INS_PRESENT, 1 },
+ { NT_TX_MTU_PROFILE_IFR, 16 },
+ { NT_TX_ON_TIMESTAMP, 1 },
+ { NT_TX_PORTS, 2 },
+ { NT_TX_PORT_REPLICATE, 1 },
+ { NT_TX_RPL_DEPTH, 4096 },
+ { NT_TX_RPL_EXT_CATEGORIES, 1024 },
+ { NT_TX_RPL_OFS_ZERO, 1 },
+ { NT_TX_RPL_PRESENT, 1 },
+ { NT_TYPE_ID, 200 },
+ { NT_USE_TRIPLE_SPEED, 0 },
+ { NT_VERSION_ID, 55 },
+ { NT_VLI_PRESENT, 0 },
+ { 0, -1 }, /* END */
+};
+
+nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000 = {
+ 200, 9563, 55, 39, 0, 0, 1713859545, 152, product_parameters, 15, fpga_modules,
+};
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
new file mode 100644
index 0000000000..ea731ae979
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c
@@ -0,0 +1,6 @@
+
+
+#include "nthw_fpga_instances.h"
+nthw_fpga_prod_init_s *nthw_fpga_instances[] = { &nthw_fpga_9563_055_039_0000, NULL };
+
+/* EOF */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
new file mode 100644
index 0000000000..c19b43c19b
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h
@@ -0,0 +1,7 @@
+
+
+#include "fpga_model.h"
+extern nthw_fpga_prod_init_s *nthw_fpga_instances[];
+extern nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000;
+
+/* EOF */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
new file mode 100644
index 0000000000..1efe9eb6e3
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
@@ -0,0 +1,36 @@
+/*
+ * nthw_fpga_mod_defs.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_MOD_DEFS_H_
+#define _NTHW_FPGA_MOD_DEFS_H_
+
+#define MOD_UNKNOWN (0L)/* Unknown/uninitialized - keep this as the first element */
+#define MOD_GFG (0xfc423807UL)
+#define MOD_GMF (0x68b1d15aUL)
+#define MOD_GPIO_PHY (0xbbe81659UL)
+#define MOD_HIF (0x7815363UL)
+#define MOD_I2CM (0x93bc7780UL)
+#define MOD_IIC (0x7629cddbUL)
+#define MOD_MAC_PCS (0x7abe24c7UL)
+#define MOD_PCIE3 (0xfbc48c18UL)
+#define MOD_PCI_RD_TG (0x9ad9eed2UL)
+#define MOD_PCI_WR_TG (0x274b69e1UL)
+#define MOD_RAC (0xae830b42UL)
+#define MOD_RST9563 (0x385d6d1dUL)
+#define MOD_SDC (0xd2369530UL)
+#define MOD_IDX_COUNT (14)
+
+/* aliases - only aliases go below this point */
+#endif /* _NTHW_FPGA_MOD_DEFS_H_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c
new file mode 100644
index 0000000000..c636549b13
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c
@@ -0,0 +1,21 @@
+
+
+#include "nthw_fpga_mod_str_map.h"
+const struct nthw_fpga_mod_str_s sa_nthw_fpga_mod_str_map[] = {
+ { MOD_GFG, "GFG" },
+ { MOD_GMF, "GMF" },
+ { MOD_GPIO_PHY, "GPIO_PHY" },
+ { MOD_HIF, "HIF" },
+ { MOD_I2CM, "I2CM" },
+ { MOD_IIC, "IIC" },
+ { MOD_MAC_PCS, "MAC_PCS" },
+ { MOD_PCIE3, "PCIE3" },
+ { MOD_PCI_RD_TG, "PCI_RD_TG" },
+ { MOD_PCI_WR_TG, "PCI_WR_TG" },
+ { MOD_RAC, "RAC" },
+ { MOD_RST9563, "RST9563" },
+ { MOD_SDC, "SDC" },
+ { 0UL, NULL }
+};
+
+/* EOF */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h
new file mode 100644
index 0000000000..6bebe56329
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h
@@ -0,0 +1,11 @@
+
+
+#include "nthw_fpga_mod_defs.h"
+#include "fpga_model.h"
+struct nthw_fpga_mod_str_s {
+ const nthw_id_t a;
+ const char *b;
+};
+extern const struct nthw_fpga_mod_str_s sa_nthw_fpga_mod_str_map[];
+
+/* EOF */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h
new file mode 100644
index 0000000000..a51d8b3888
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h
@@ -0,0 +1,232 @@
+/*
+ * nthw_fpga_param_defs.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_PARAM_DEFS_
+#define _NTHW_FPGA_PARAM_DEFS_
+
+#define NTHW_PARAM_UNKNOWN (0UL)
+#define NT_BUILD_NUMBER (0x489b50fbUL)
+#define NT_BUILD_TIME (0x6e66771fUL)
+#define NT_CATEGORIES (0xfdbcebdcUL)
+#define NT_CAT_CCT_SIZE (0x3a505ddaUL)
+#define NT_CAT_CTE_SIZE (0x50a32ea4UL)
+#define NT_CAT_CTS_SIZE (0x852ccf22UL)
+#define NT_CAT_DCT_PRESENT (0x898c5638UL)
+#define NT_CAT_DCT_SIZE (0x309554c3UL)
+#define NT_CAT_END_OFS_SUPPORT (0x925f11d9UL)
+#define NT_CAT_FPC (0x417fd17bUL)
+#define NT_CAT_FTE_SIZE (0x184320c0UL)
+#define NT_CAT_FUNCS (0x6af66e16UL)
+#define NT_CAT_KCC_BANKS (0x426534f3UL)
+#define NT_CAT_KCC_PRESENT (0xd2d58d46UL)
+#define NT_CAT_KCC_SIZE (0xf766744cUL)
+#define NT_CAT_KCE_SIZE (0x213f9751UL)
+#define NT_CAT_KM_IF_CNT (0x8c934524UL)
+#define NT_CAT_KM_IF_M0 (0x666dd699UL)
+#define NT_CAT_KM_IF_M1 (0x116ae60fUL)
+#define NT_CAT_N_CMP (0x3a692ad4UL)
+#define NT_CAT_N_EXT (0xe3c746bUL)
+#define NT_CAT_N_LEN (0x3e3da82UL)
+#define NT_CAT_RCK_SIZE (0x78c1dc21UL)
+#define NT_CAT_VALUES (0xec523dbbUL)
+#define NT_CB_DEBUG (0xa0bccd31UL)
+#define NT_COR_CATEGORIES (0x7392b58dUL)
+#define NT_COR_PRESENT (0xbe0d1fdeUL)
+#define NT_CPY_MASK_MEM (0x24f85e48UL)
+#define NT_CSU_PRESENT (0xe7fe1371UL)
+#define NT_DBS_PRESENT (0x75b395aeUL)
+#define NT_DBS_RX_QUEUES (0x927069fUL)
+#define NT_DBS_TX_PORTS (0xae2d6250UL)
+#define NT_DBS_TX_QUEUES (0x7a3d7f15UL)
+#define NT_DDP_PRESENT (0x4120d92cUL)
+#define NT_DDP_TBL_DEPTH (0xf52e011UL)
+#define NT_EMI_SPLIT_STEPS (0xe4b3210fUL)
+#define NT_EOF_TIMESTAMP_ONLY (0xe476891bUL)
+#define NT_EPP_CATEGORIES (0xf41c134bUL)
+#define NT_EXT_MEM_NUM (0x43a48169UL)
+#define NT_EXT_MEM_SINGLE_SIZE_GB (0x1817e71eUL)
+#define NT_FLM_CACHE (0x414157e4UL)
+#define NT_FLM_CATEGORIES (0x3477c5a3UL)
+#define NT_FLM_ENTRY_SIZE (0x9ca7f0b6UL)
+#define NT_FLM_LOAD_APS_MAX (0xe4d4f4edUL)
+#define NT_FLM_LOAD_LPS_MAX (0x8503952dUL)
+#define NT_FLM_PRESENT (0x5714853fUL)
+#define NT_FLM_PRIOS (0x92afe487UL)
+#define NT_FLM_PST_PROFILES (0xf4a0d627UL)
+#define NT_FLM_SCRUB_PROFILES (0x6b6f6b21UL)
+#define NT_FLM_SIZE_MB (0x5667a5deUL)
+#define NT_FLM_STATEFUL (0xc8bf17a8UL)
+#define NT_FLM_VARIANT (0x5beb9485UL)
+#define NT_GFG_PRESENT (0x149640a8UL)
+#define NT_GFG_TX_LIVE_RECONFIG_SUPPORT (0x7b5ad1e0UL)
+#define NT_GMF_FCS_PRESENT (0xc15365efUL)
+#define NT_GMF_IFG_SPEED_DIV (0xc06cdcbdUL)
+#define NT_GMF_IFG_SPEED_DIV100G (0x43e1fb80UL)
+#define NT_GMF_IFG_SPEED_DIV100M (0xa334129eUL)
+#define NT_GMF_IFG_SPEED_DIV10G (0x49197e96UL)
+#define NT_GMF_IFG_SPEED_DIV1G (0xb1324f18UL)
+#define NT_GMF_IFG_SPEED_DIV2 (0xafc51de0UL)
+#define NT_GMF_IFG_SPEED_DIV25G (0x3628348aUL)
+#define NT_GMF_IFG_SPEED_DIV3 (0xd8c22d76UL)
+#define NT_GMF_IFG_SPEED_DIV4 (0x46a6b8d5UL)
+#define NT_GMF_IFG_SPEED_DIV40G (0x4fd2bc7dUL)
+#define NT_GMF_IFG_SPEED_DIV50G (0x4e10d64aUL)
+#define NT_GMF_IFG_SPEED_MUL (0xd4a84315UL)
+#define NT_GMF_IFG_SPEED_MUL100G (0x883df390UL)
+#define NT_GMF_IFG_SPEED_MUL100M (0x68e81a8eUL)
+#define NT_GMF_IFG_SPEED_MUL10G (0xf4a2e226UL)
+#define NT_GMF_IFG_SPEED_MUL1G (0xb75ce3e8UL)
+#define NT_GMF_IFG_SPEED_MUL2 (0x77dcf2a5UL)
+#define NT_GMF_IFG_SPEED_MUL25G (0x8b93a83aUL)
+#define NT_GMF_IFG_SPEED_MUL3 (0xdbc233UL)
+#define NT_GMF_IFG_SPEED_MUL4 (0x9ebf5790UL)
+#define NT_GMF_IFG_SPEED_MUL40G (0xf26920cdUL)
+#define NT_GMF_IFG_SPEED_MUL50G (0xf3ab4afaUL)
+#define NT_GROUP_ID (0x113978c5UL)
+#define NT_HFU_PRESENT (0x558de99UL)
+#define NT_HIF_MSIX_BAR (0xc10014e9UL)
+#define NT_HIF_MSIX_PBA_OFS (0x900307fbUL)
+#define NT_HIF_MSIX_PRESENT (0x77a98665UL)
+#define NT_HIF_MSIX_TBL_OFS (0x9cdce759UL)
+#define NT_HIF_MSIX_TBL_SIZE (0x6ce7b76UL)
+#define NT_HIF_PER_PS (0x38c954b1UL)
+#define NT_HIF_SRIOV_PRESENT (0x49f8c203UL)
+#define NT_HIF_VF_OFFSET (0x9fb3c9b0UL)
+#define NT_HSH_CATEGORIES (0xf43894dcUL)
+#define NT_HSH_TOEPLITZ (0x603f96a3UL)
+#define NT_HST_CATEGORIES (0xfd2a34a1UL)
+#define NT_HST_PRESENT (0xd3a48076UL)
+#define NT_IOA_CATEGORIES (0xda23501aUL)
+#define NT_IOA_PRESENT (0xc9ef39eeUL)
+#define NT_IPF_PRESENT (0x7b2b8e42UL)
+#define NT_KM_CAM_BANKS (0x3cad3371UL)
+#define NT_KM_CAM_RECORDS (0x24256ab5UL)
+#define NT_KM_CAM_REC_WORDS (0xe8e0ef3UL)
+#define NT_KM_CATEGORIES (0x4d2a4c96UL)
+#define NT_KM_END_OFS_SUPPORT (0x4a90ff33UL)
+#define NT_KM_EXT_EXTRACTORS (0xf135193cUL)
+#define NT_KM_FLOW_SETS (0x359cddf3UL)
+#define NT_KM_FLOW_TYPES (0xb79ff984UL)
+#define NT_KM_PRESENT (0xb54eaee3UL)
+#define NT_KM_SWX_PRESENT (0x2715aebeUL)
+#define NT_KM_SYNERGY_MATCH (0x935e5b7fUL)
+#define NT_KM_TCAM_BANKS (0x6f6f0894UL)
+#define NT_KM_TCAM_BANK_WIDTH (0x4c5015aeUL)
+#define NT_KM_TCAM_HIT_QUAL (0xd3fb2aafUL)
+#define NT_KM_TCAM_KEYWAY (0x45318c61UL)
+#define NT_KM_WIDE (0x7ba773c4UL)
+#define NT_LR_PRESENT (0x24eb383aUL)
+#define NT_LTX_CATEGORIES (0x9cfff063UL)
+#define NT_MCU_DRAM_SIZE (0xe33d7922UL)
+#define NT_MCU_PRESENT (0x9226b99fUL)
+#define NT_MCU_TYPE (0xce45b840UL)
+#define NT_MDG_DEBUG_FLOW_CONTROL (0x4f199a18UL)
+#define NT_MDG_DEBUG_REG_READ_BACK (0xc674095UL)
+#define NT_MSK_CATEGORIES (0x7052841UL)
+#define NT_MSK_PRESENT (0xd18aa194UL)
+#define NT_NAME (0x224bb693UL)
+#define NT_NFV_OVS_PRODUCT (0xd8223124UL)
+#define NT_NIMS (0xd88c527aUL)
+#define NT_PATCH_NUMBER (0xecd14417UL)
+#define NT_PCI_DEVICE_ID (0x254dede8UL)
+#define NT_PCI_INT_AVR (0x40c50ef1UL)
+#define NT_PCI_INT_EQM (0x85853d1fUL)
+#define NT_PCI_INT_IIC0 (0xbf363717UL)
+#define NT_PCI_INT_IIC1 (0xc8310781UL)
+#define NT_PCI_INT_IIC2 (0x5138563bUL)
+#define NT_PCI_INT_IIC3 (0x263f66adUL)
+#define NT_PCI_INT_IIC4 (0xb85bf30eUL)
+#define NT_PCI_INT_IIC5 (0xcf5cc398UL)
+#define NT_PCI_INT_PORT (0x8facd5e1UL)
+#define NT_PCI_INT_PORT0 (0x2359a11aUL)
+#define NT_PCI_INT_PORT1 (0x545e918cUL)
+#define NT_PCI_INT_PPS (0x7c7c50a6UL)
+#define NT_PCI_INT_QSPI (0x731ce6cbUL)
+#define NT_PCI_INT_SPIM (0x473efd18UL)
+#define NT_PCI_INT_SPIS (0xbd31c07bUL)
+#define NT_PCI_INT_STA (0xe9ef5ab3UL)
+#define NT_PCI_INT_TIMER (0x14ad9f2fUL)
+#define NT_PCI_INT_TINT (0xe2346359UL)
+#define NT_PCI_TA_TG_PRESENT (0x3cc176a0UL)
+#define NT_PCI_VENDOR_ID (0x47eac44fUL)
+#define NT_PDB_CATEGORIES (0x8290fe65UL)
+#define NT_PHY_ANEG_PRESENT (0x626ddda5UL)
+#define NT_PHY_KRFEC_PRESENT (0x8ab2cf25UL)
+#define NT_PHY_PORTS (0x41986112UL)
+#define NT_PHY_PORTS_PER_QUAD (0xf4b396e6UL)
+#define NT_PHY_QUADS (0x17fef021UL)
+#define NT_PHY_RSFEC_PRESENT (0x22852f78UL)
+#define NT_PORTS (0x32e8ff06UL)
+#define NT_PROD_ID_LAYOUT_VERSION (0x42106495UL)
+#define NT_QM_BLOCKS (0xb735e210UL)
+#define NT_QM_CELLS (0x510e07f1UL)
+#define NT_QM_CELL_SIZE (0xbddf0f74UL)
+#define NT_QM_PRESENT (0x85c2bfc2UL)
+#define NT_QSL_CATEGORIES (0x3fda6c8fUL)
+#define NT_QSL_COLOR_SEL_BW (0x549c264dUL)
+#define NT_QSL_QST_SIZE (0x41d03837UL)
+#define NT_QUEUES (0xf8a94e49UL)
+#define NT_RAC_RAB_INTERFACES (0x7b742b2bUL)
+#define NT_RAC_RAB_OB_UPDATE (0x3a44d066UL)
+#define NT_REVISION_ID (0xd212229fUL)
+#define NT_RMC_LAG_GROUPS (0xa7d5b2fbUL)
+#define NT_RMC_PRESENT (0x6e3b82daUL)
+#define NT_ROA_CATEGORIES (0xf3a9579bUL)
+#define NT_ROA_PRESENT (0x44387a61UL)
+#define NT_RPF_MATURING_DEL_DEFAULT (0xd4e7e4d2UL)
+#define NT_RPF_PRESENT (0xf6fccdcdUL)
+#define NT_RPP_PER_PS (0xb2f28916UL)
+#define NT_RTX_PRESENT (0x9b15f454UL)
+#define NT_RX_HOST_BUFFERS (0x9207c413UL)
+#define NT_RX_PORTS (0x3639a86eUL)
+#define NT_RX_PORT_REPLICATE (0xed09d794UL)
+#define NT_SLB_PRESENT (0x570c2267UL)
+#define NT_SLC_LR_PRESENT (0xe600975aUL)
+#define NT_SLC_PRESENT (0x40773624UL)
+#define NT_STA_COLORS (0xe1e90b5bUL)
+#define NT_STA_LOAD_AVG_RX (0x94efbfa1UL)
+#define NT_STA_LOAD_AVG_TX (0xc2b51827UL)
+#define NT_STA_RX_PORTS (0x75da30f9UL)
+#define NT_TBH_DEBUG_DLN (0x1faf2e1dUL)
+#define NT_TBH_PRESENT (0xf5d08dc9UL)
+#define NT_TFD_PRESENT (0x1a0fdea7UL)
+#define NT_TPE_CATEGORIES (0x9b1a54bdUL)
+#define NT_TSM_OST_ONLY (0x4899103aUL)
+#define NT_TS_APPEND (0x4544c692UL)
+#define NT_TS_INJECT_PRESENT (0xb2aa4f0eUL)
+#define NT_TX_CPY_PACKET_READERS (0x37f470f0UL)
+#define NT_TX_CPY_PRESENT (0xe54af81cUL)
+#define NT_TX_CPY_SIDEBAND_READERS (0x52220d68UL)
+#define NT_TX_CPY_VARIANT (0xe9b5e9a6UL)
+#define NT_TX_CPY_WRITERS (0xd9dbd4UL)
+#define NT_TX_HOST_BUFFERS (0xb0fd10e1UL)
+#define NT_TX_INS_OFS_ZERO (0x5510aa2dUL)
+#define NT_TX_INS_PRESENT (0xabac9b5dUL)
+#define NT_TX_MTU_PROFILE_IFR (0x8d313bc2UL)
+#define NT_TX_ON_TIMESTAMP (0x51d7fce0UL)
+#define NT_TX_PORTS (0xf056a1e9UL)
+#define NT_TX_PORT_REPLICATE (0x4a3d609cUL)
+#define NT_TX_RPL_DEPTH (0x61f86eb9UL)
+#define NT_TX_RPL_EXT_CATEGORIES (0x421e973cUL)
+#define NT_TX_RPL_OFS_ZERO (0x2bfd677UL)
+#define NT_TX_RPL_PRESENT (0x6c65e429UL)
+#define NT_TYPE_ID (0xd03446b2UL)
+#define NT_USE_TRIPLE_SPEED (0x54350589UL)
+#define NT_UUID (0xad179833UL)
+#define NT_VERSION (0x92295f02UL)
+#define NT_VERSION_ID (0xb4becc51UL)
+#define NT_VLI_PRESENT (0xa40e10f8UL)
+
+#endif /* _NTHW_FPGA_PARAM_DEFS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
new file mode 100644
index 0000000000..9c3262fb58
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
@@ -0,0 +1,35 @@
+/*
+ * nthw_fpga_reg_defs.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_
+#define _NTHW_FPGA_REG_DEFS_
+
+#include "nthw_fpga_reg_defs_gfg.h"
+#include "nthw_fpga_reg_defs_gmf.h"
+#include "nthw_fpga_reg_defs_gpio_phy.h"
+#include "nthw_fpga_reg_defs_hif.h"
+#include "nthw_fpga_reg_defs_i2cm.h"
+#include "nthw_fpga_reg_defs_iic.h"
+#include "nthw_fpga_reg_defs_mac_pcs.h"
+#include "nthw_fpga_reg_defs_pcie3.h"
+#include "nthw_fpga_reg_defs_pci_rd_tg.h"
+#include "nthw_fpga_reg_defs_pci_wr_tg.h"
+#include "nthw_fpga_reg_defs_rac.h"
+#include "nthw_fpga_reg_defs_rst9563.h"
+#include "nthw_fpga_reg_defs_sdc.h"
+
+/* aliases */
+
+#endif /* NTHW_FPGA_REG_DEFS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h
new file mode 100644
index 0000000000..6ee75c571e
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h
@@ -0,0 +1,126 @@
+/*
+ * nthw_fpga_reg_defs_gfg.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_GFG_
+#define _NTHW_FPGA_REG_DEFS_GFG_
+
+/* GFG */
+#define NTHW_MOD_GFG (0xfc423807UL)
+#define GFG_BURSTSIZE0 (0xd62af404UL)
+#define GFG_BURSTSIZE0_VAL (0xa2e4d17eUL)
+#define GFG_BURSTSIZE1 (0xa12dc492UL)
+#define GFG_BURSTSIZE1_VAL (0x9f84f8ceUL)
+#define GFG_BURSTSIZE2 (0x38249528UL)
+#define GFG_BURSTSIZE2_VAL (0xd824821eUL)
+#define GFG_BURSTSIZE3 (0x4f23a5beUL)
+#define GFG_BURSTSIZE3_VAL (0xe544abaeUL)
+#define GFG_BURSTSIZE4 (0xd147301dUL)
+#define GFG_BURSTSIZE4_VAL (0x576477beUL)
+#define GFG_BURSTSIZE5 (0xa640008bUL)
+#define GFG_BURSTSIZE5_VAL (0x6a045e0eUL)
+#define GFG_BURSTSIZE6 (0x3f495131UL)
+#define GFG_BURSTSIZE6_VAL (0x2da424deUL)
+#define GFG_BURSTSIZE7 (0x484e61a7UL)
+#define GFG_BURSTSIZE7_VAL (0x10c40d6eUL)
+#define GFG_CTRL0 (0xc3e26c0fUL)
+#define GFG_CTRL0_ENABLE (0xfe65937UL)
+#define GFG_CTRL0_MODE (0x81d94c52UL)
+#define GFG_CTRL0_PRBS_EN (0xb43e6c6UL)
+#define GFG_CTRL0_SIZE (0xe1d32f93UL)
+#define GFG_CTRL1 (0xb4e55c99UL)
+#define GFG_CTRL1_ENABLE (0xc34c59a9UL)
+#define GFG_CTRL1_MODE (0x4a859ff7UL)
+#define GFG_CTRL1_PRBS_EN (0x1c38f285UL)
+#define GFG_CTRL1_SIZE (0x2a8ffc36UL)
+#define GFG_CTRL2 (0x2dec0d23UL)
+#define GFG_CTRL2_ENABLE (0x4dc35e4aUL)
+#define GFG_CTRL2_MODE (0xcc11ed59UL)
+#define GFG_CTRL2_PRBS_EN (0x25b5ce40UL)
+#define GFG_CTRL2_SIZE (0xac1b8e98UL)
+#define GFG_CTRL3 (0x5aeb3db5UL)
+#define GFG_CTRL3_ENABLE (0x81695ed4UL)
+#define GFG_CTRL3_MODE (0x74d3efcUL)
+#define GFG_CTRL3_PRBS_EN (0x32ceda03UL)
+#define GFG_CTRL3_SIZE (0x67475d3dUL)
+#define GFG_CTRL4 (0xc48fa816UL)
+#define GFG_CTRL4_ENABLE (0x8bac57cdUL)
+#define GFG_CTRL4_MODE (0x1a480e44UL)
+#define GFG_CTRL4_PRBS_EN (0x56afb7caUL)
+#define GFG_CTRL4_SIZE (0x7a426d85UL)
+#define GFG_CTRL5 (0xb3889880UL)
+#define GFG_CTRL5_ENABLE (0x47065753UL)
+#define GFG_CTRL5_MODE (0xd114dde1UL)
+#define GFG_CTRL5_PRBS_EN (0x41d4a389UL)
+#define GFG_CTRL5_SIZE (0xb11ebe20UL)
+#define GFG_CTRL6 (0x2a81c93aUL)
+#define GFG_CTRL6_ENABLE (0xc98950b0UL)
+#define GFG_CTRL6_MODE (0x5780af4fUL)
+#define GFG_CTRL6_PRBS_EN (0x78599f4cUL)
+#define GFG_CTRL6_SIZE (0x378acc8eUL)
+#define GFG_CTRL7 (0x5d86f9acUL)
+#define GFG_CTRL7_ENABLE (0x523502eUL)
+#define GFG_CTRL7_MODE (0x9cdc7ceaUL)
+#define GFG_CTRL7_PRBS_EN (0x6f228b0fUL)
+#define GFG_CTRL7_SIZE (0xfcd61f2bUL)
+#define GFG_RUN0 (0xb72be46cUL)
+#define GFG_RUN0_RUN (0xa457d3c8UL)
+#define GFG_RUN1 (0xc02cd4faUL)
+#define GFG_RUN1_RUN (0x9937fa78UL)
+#define GFG_RUN2 (0x59258540UL)
+#define GFG_RUN2_RUN (0xde9780a8UL)
+#define GFG_RUN3 (0x2e22b5d6UL)
+#define GFG_RUN3_RUN (0xe3f7a918UL)
+#define GFG_RUN4 (0xb0462075UL)
+#define GFG_RUN4_RUN (0x51d77508UL)
+#define GFG_RUN5 (0xc74110e3UL)
+#define GFG_RUN5_RUN (0x6cb75cb8UL)
+#define GFG_RUN6 (0x5e484159UL)
+#define GFG_RUN6_RUN (0x2b172668UL)
+#define GFG_RUN7 (0x294f71cfUL)
+#define GFG_RUN7_RUN (0x16770fd8UL)
+#define GFG_SIZEMASK0 (0x7015abe3UL)
+#define GFG_SIZEMASK0_VAL (0xe9c7ed93UL)
+#define GFG_SIZEMASK1 (0x7129b75UL)
+#define GFG_SIZEMASK1_VAL (0xd4a7c423UL)
+#define GFG_SIZEMASK2 (0x9e1bcacfUL)
+#define GFG_SIZEMASK2_VAL (0x9307bef3UL)
+#define GFG_SIZEMASK3 (0xe91cfa59UL)
+#define GFG_SIZEMASK3_VAL (0xae679743UL)
+#define GFG_SIZEMASK4 (0x77786ffaUL)
+#define GFG_SIZEMASK4_VAL (0x1c474b53UL)
+#define GFG_SIZEMASK5 (0x7f5f6cUL)
+#define GFG_SIZEMASK5_VAL (0x212762e3UL)
+#define GFG_SIZEMASK6 (0x99760ed6UL)
+#define GFG_SIZEMASK6_VAL (0x66871833UL)
+#define GFG_SIZEMASK7 (0xee713e40UL)
+#define GFG_SIZEMASK7_VAL (0x5be73183UL)
+#define GFG_STREAMID0 (0xbd4ba9aeUL)
+#define GFG_STREAMID0_VAL (0x42d077caUL)
+#define GFG_STREAMID1 (0xca4c9938UL)
+#define GFG_STREAMID1_VAL (0x7fb05e7aUL)
+#define GFG_STREAMID2 (0x5345c882UL)
+#define GFG_STREAMID2_VAL (0x381024aaUL)
+#define GFG_STREAMID3 (0x2442f814UL)
+#define GFG_STREAMID3_VAL (0x5700d1aUL)
+#define GFG_STREAMID4 (0xba266db7UL)
+#define GFG_STREAMID4_VAL (0xb750d10aUL)
+#define GFG_STREAMID5 (0xcd215d21UL)
+#define GFG_STREAMID5_VAL (0x8a30f8baUL)
+#define GFG_STREAMID6 (0x54280c9bUL)
+#define GFG_STREAMID6_VAL (0xcd90826aUL)
+#define GFG_STREAMID7 (0x232f3c0dUL)
+#define GFG_STREAMID7_VAL (0xf0f0abdaUL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_GFG_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h
new file mode 100644
index 0000000000..be3c12d177
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h
@@ -0,0 +1,68 @@
+/*
+ * nthw_fpga_reg_defs_gmf.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_GMF_
+#define _NTHW_FPGA_REG_DEFS_GMF_
+
+/* GMF */
+#define NTHW_MOD_GMF (0x68b1d15aUL)
+#define GMF_CTRL (0x28d359b4UL)
+#define GMF_CTRL_ENABLE (0xe41c837cUL)
+#define GMF_CTRL_FCS_ALWAYS (0x8f36cec1UL)
+#define GMF_CTRL_IFG_AUTO_ADJUST_ENABLE (0x5b5669b0UL)
+#define GMF_CTRL_IFG_ENABLE (0x995f1bfbUL)
+#define GMF_CTRL_IFG_TX_NOW_ALWAYS (0xb11744c2UL)
+#define GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE (0xe9e4ee2aUL)
+#define GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK (0x32dc6426UL)
+#define GMF_CTRL_IFG_TX_ON_TS_ALWAYS (0x21dcad67UL)
+#define GMF_CTRL_TS_INJECT_ALWAYS (0x353fa4aaUL)
+#define GMF_CTRL_TS_INJECT_DUAL_STEP (0xc4c0195cUL)
+#define GMF_DEBUG_LANE_MARKER (0xa51eb8a9UL)
+#define GMF_DEBUG_LANE_MARKER_COMPENSATION (0x4f44f92aUL)
+#define GMF_IFG_MAX_ADJUST_SLACK (0xe49f3408UL)
+#define GMF_IFG_MAX_ADJUST_SLACK_SLACK (0x9a2de1f7UL)
+#define GMF_IFG_SET_CLOCK_DELTA (0x8a614d6fUL)
+#define GMF_IFG_SET_CLOCK_DELTA_DELTA (0x1da821d6UL)
+#define GMF_IFG_SET_CLOCK_DELTA_ADJUST (0xaa468304UL)
+#define GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA (0x2c165992UL)
+#define GMF_IFG_TX_NOW_ON_TS (0xd32fab5eUL)
+#define GMF_IFG_TX_NOW_ON_TS_TS (0x612771f4UL)
+#define GMF_SPEED (0x48bec0a1UL)
+#define GMF_SPEED_IFG_SPEED (0x273c8281UL)
+#define GMF_STAT (0xa49d7efUL)
+#define GMF_STAT_CTRL_EMPTY (0x3f6e8adcUL)
+#define GMF_STAT_DATA_CTRL_EMPTY (0xc18fc6e9UL)
+#define GMF_STAT_SB_EMPTY (0x99314d52UL)
+#define GMF_STAT_CTRL (0xfd31633eUL)
+#define GMF_STAT_CTRL_FILL_LEVEL (0xe8cd56d6UL)
+#define GMF_STAT_DATA0 (0x51838aabUL)
+#define GMF_STAT_DATA0_EMPTY (0xcfcad9c0UL)
+#define GMF_STAT_DATA1 (0x2684ba3dUL)
+#define GMF_STAT_DATA1_EMPTY (0x69bdd274UL)
+#define GMF_STAT_DATA_BUFFER (0xa6431f34UL)
+#define GMF_STAT_DATA_BUFFER_FREE (0x3476e461UL)
+#define GMF_STAT_DATA_BUFFER_USED (0x1f46b1UL)
+#define GMF_STAT_MAX_DELAYED_PKT (0x3fb5c76dUL)
+#define GMF_STAT_MAX_DELAYED_PKT_NS (0x2eb58efbUL)
+#define GMF_STAT_NEXT_PKT (0x558ee30dUL)
+#define GMF_STAT_NEXT_PKT_NS (0x26814d33UL)
+#define GMF_STAT_STICKY (0x5a0f2ef7UL)
+#define GMF_STAT_STICKY_DATA_UNDERFLOWED (0x9a3dfcb6UL)
+#define GMF_STAT_STICKY_IFG_ADJUSTED (0xea849a5fUL)
+#define GMF_TS_INJECT (0x66e57281UL)
+#define GMF_TS_INJECT_OFFSET (0x8c2c9cb6UL)
+#define GMF_TS_INJECT_POS (0xdded481UL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_GMF_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h
new file mode 100644
index 0000000000..6574263d50
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h
@@ -0,0 +1,48 @@
+/*
+ * nthw_fpga_reg_defs_gpio_phy.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_GPIO_PHY_
+#define _NTHW_FPGA_REG_DEFS_GPIO_PHY_
+
+/* GPIO_PHY */
+#define NTHW_MOD_GPIO_PHY (0xbbe81659UL)
+#define GPIO_PHY_CFG (0x39548432UL)
+#define GPIO_PHY_CFG_E_PORT0_RXLOS (0x2dfe5bUL)
+#define GPIO_PHY_CFG_E_PORT1_RXLOS (0xa65af5efUL)
+#define GPIO_PHY_CFG_PORT0_INT_B (0xa882887cUL)
+#define GPIO_PHY_CFG_PORT0_LPMODE (0x65df41beUL)
+#define GPIO_PHY_CFG_PORT0_MODPRS_B (0x6aef8e94UL)
+#define GPIO_PHY_CFG_PORT0_PLL_INTR (0xbf1f8c5dUL)
+#define GPIO_PHY_CFG_PORT0_RESET_B (0x1ef06a6cUL)
+#define GPIO_PHY_CFG_PORT1_INT_B (0xef583c8UL)
+#define GPIO_PHY_CFG_PORT1_LPMODE (0xa9754120UL)
+#define GPIO_PHY_CFG_PORT1_MODPRS_B (0x852de5aaUL)
+#define GPIO_PHY_CFG_PORT1_PLL_INTR (0x50dde763UL)
+#define GPIO_PHY_CFG_PORT1_RESET_B (0x98b7e2fUL)
+#define GPIO_PHY_GPIO (0xf5c5d393UL)
+#define GPIO_PHY_GPIO_E_PORT0_RXLOS (0xfb05c9faUL)
+#define GPIO_PHY_GPIO_E_PORT1_RXLOS (0x5d72c24eUL)
+#define GPIO_PHY_GPIO_PORT0_INT_B (0x6aceab27UL)
+#define GPIO_PHY_GPIO_PORT0_LPMODE (0x99a485e1UL)
+#define GPIO_PHY_GPIO_PORT0_MODPRS_B (0xcbc535ddUL)
+#define GPIO_PHY_GPIO_PORT0_PLL_INTR (0x1e353714UL)
+#define GPIO_PHY_GPIO_PORT0_RESET_B (0xe5d85dcdUL)
+#define GPIO_PHY_GPIO_PORT1_INT_B (0xccb9a093UL)
+#define GPIO_PHY_GPIO_PORT1_LPMODE (0x550e857fUL)
+#define GPIO_PHY_GPIO_PORT1_MODPRS_B (0x24075ee3UL)
+#define GPIO_PHY_GPIO_PORT1_PLL_INTR (0xf1f75c2aUL)
+#define GPIO_PHY_GPIO_PORT1_RESET_B (0xf2a3498eUL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_GPIO_PHY_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h
new file mode 100644
index 0000000000..4bd2ca52c9
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h
@@ -0,0 +1,79 @@
+/*
+ * nthw_fpga_reg_defs_hif.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_HIF_
+#define _NTHW_FPGA_REG_DEFS_HIF_
+
+/* HIF */
+#define NTHW_MOD_HIF (0x7815363UL)
+#define HIF_BUILD_TIME (0x1eaf6ab8UL)
+#define HIF_BUILD_TIME_TIME (0xb2dfbda5UL)
+#define HIF_CONFIG (0xb64b595cUL)
+#define HIF_CONFIG_EXT_TAG (0x57e685bUL)
+#define HIF_CONFIG_MAX_READ (0x7d56ce45UL)
+#define HIF_CONFIG_MAX_TLP (0xe1c563e4UL)
+#define HIF_CONTROL (0xedb9ed3dUL)
+#define HIF_CONTROL_BLESSED (0x680018b7UL)
+#define HIF_CONTROL_FSR (0x498a2097UL)
+#define HIF_CONTROL_WRAW (0xc1a7bc42UL)
+#define HIF_PROD_ID_EX (0xc9c9efb2UL)
+#define HIF_PROD_ID_EX_LAYOUT (0xc6564c80UL)
+#define HIF_PROD_ID_EX_LAYOUT_VERSION (0x9803a0e2UL)
+#define HIF_PROD_ID_EX_RESERVED (0x1189af8aUL)
+#define HIF_PROD_ID_EXT (0x9ba2612fUL)
+#define HIF_PROD_ID_EXT_LAYOUT (0xe315afa1UL)
+#define HIF_PROD_ID_EXT_LAYOUT_VERSION (0x1f7aa616UL)
+#define HIF_PROD_ID_EXT_RESERVED (0xa4152ce8UL)
+#define HIF_PROD_ID_LSB (0x8353363aUL)
+#define HIF_PROD_ID_LSB_GROUP_ID (0xbb9614f7UL)
+#define HIF_PROD_ID_LSB_REV_ID (0x5458192eUL)
+#define HIF_PROD_ID_LSB_VER_ID (0x40abcc6fUL)
+#define HIF_PROD_ID_MSB (0x82915c0dUL)
+#define HIF_PROD_ID_MSB_BUILD_NO (0x1135f11bUL)
+#define HIF_PROD_ID_MSB_PATCH_NO (0xcbf446bcUL)
+#define HIF_PROD_ID_MSB_TYPE_ID (0xb49af41cUL)
+#define HIF_SAMPLE_TIME (0xad0472aaUL)
+#define HIF_SAMPLE_TIME_SAMPLE_TIME (0x56bd0a0bUL)
+#define HIF_STATUS (0x19c1133cUL)
+#define HIF_STATUS_RD_ERR (0x15e9f376UL)
+#define HIF_STATUS_TAGS_IN_USE (0x9789b255UL)
+#define HIF_STATUS_WR_ERR (0xaa8400e7UL)
+#define HIF_STAT_CTRL (0xd9478d74UL)
+#define HIF_STAT_CTRL_STAT_ENA (0xf26c834cUL)
+#define HIF_STAT_CTRL_STAT_REQ (0x1546ff16UL)
+#define HIF_STAT_REFCLK (0x656cf83fUL)
+#define HIF_STAT_REFCLK_REFCLK250 (0xb9dd01fcUL)
+#define HIF_STAT_RX (0x8c483f48UL)
+#define HIF_STAT_RX_COUNTER (0xd99bc360UL)
+#define HIF_STAT_TX (0xda1298ceUL)
+#define HIF_STAT_TX_COUNTER (0xd485b327UL)
+#define HIF_TEST0 (0xdab033c0UL)
+#define HIF_TEST0_DATA (0xb7f3cba2UL)
+#define HIF_TEST1 (0xadb70356UL)
+#define HIF_TEST1_DATA (0x7caf1807UL)
+#define HIF_TEST2 (0x34be52ecUL)
+#define HIF_TEST2_DATA (0xfa3b6aa9UL)
+#define HIF_TEST3 (0x43b9627aUL)
+#define HIF_TEST3_DATA (0x3167b90cUL)
+#define HIF_UUID0 (0xecba7918UL)
+#define HIF_UUID0_UUID0 (0x84b3f35eUL)
+#define HIF_UUID1 (0x9bbd498eUL)
+#define HIF_UUID1_UUID1 (0x55c3c87cUL)
+#define HIF_UUID2 (0x2b41834UL)
+#define HIF_UUID2_UUID2 (0xfd22835bUL)
+#define HIF_UUID3 (0x75b328a2UL)
+#define HIF_UUID3_UUID3 (0x2c52b879UL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_HIF_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h
new file mode 100644
index 0000000000..56248d5261
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h
@@ -0,0 +1,38 @@
+/*
+ * nthw_fpga_reg_defs_i2cm.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_I2CM_
+#define _NTHW_FPGA_REG_DEFS_I2CM_
+
+/* I2CM */
+#define NTHW_MOD_I2CM (0x93bc7780UL)
+#define I2CM_CMD_STATUS (0xcb66305bUL)
+#define I2CM_CMD_STATUS_CMD_STATUS (0x9c9460a9UL)
+#define I2CM_CTRL (0x7c06d3b0UL)
+#define I2CM_CTRL_EN (0x57d0a8aaUL)
+#define I2CM_CTRL_IEN (0x9fdc39ebUL)
+#define I2CM_DATA (0xd3d751a9UL)
+#define I2CM_DATA_DATA (0x2ea487faUL)
+#define I2CM_IO_EXP (0xe8dfa320UL)
+#define I2CM_IO_EXP_INT_B (0x85e5ff3fUL)
+#define I2CM_IO_EXP_RST (0x207c9928UL)
+#define I2CM_PRER_HIGH (0xf1139b49UL)
+#define I2CM_PRER_HIGH_PRER_HIGH (0xc6ff6431UL)
+#define I2CM_PRER_LOW (0x84f76481UL)
+#define I2CM_PRER_LOW_PRER_LOW (0x396755aaUL)
+#define I2CM_SELECT (0xecd56d8eUL)
+#define I2CM_SELECT_SELECT (0xb9d992d8UL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_I2CM_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h
new file mode 100644
index 0000000000..42a60cff12
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h
@@ -0,0 +1,96 @@
+/*
+ * nthw_fpga_reg_defs_iic.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_IIC_
+#define _NTHW_FPGA_REG_DEFS_IIC_
+
+/* IIC */
+#define NTHW_MOD_IIC (0x7629cddbUL)
+#define IIC_ADR (0x94832a56UL)
+#define IIC_ADR_SLV_ADR (0xe34a95b4UL)
+#define IIC_CR (0x2e99752eUL)
+#define IIC_CR_EN (0x38b0a8b8UL)
+#define IIC_CR_GC_EN (0x6a93c608UL)
+#define IIC_CR_MSMS (0xd3370cefUL)
+#define IIC_CR_RST (0x9d83289fUL)
+#define IIC_CR_RSTA (0xb3f49376UL)
+#define IIC_CR_TX (0x9fbd3ef9UL)
+#define IIC_CR_TXAK (0x4daa2c41UL)
+#define IIC_CR_TXFIFO_RESET (0x9d442d45UL)
+#define IIC_DGIE (0xca86a888UL)
+#define IIC_DGIE_GIE (0xda9f5b68UL)
+#define IIC_GPO (0xdda6ed68UL)
+#define IIC_GPO_GPO_VAL (0x6c51285eUL)
+#define IIC_IER (0x838b4aafUL)
+#define IIC_IER_INT0 (0x27d5f60eUL)
+#define IIC_IER_INT1 (0x50d2c698UL)
+#define IIC_IER_INT2 (0xc9db9722UL)
+#define IIC_IER_INT3 (0xbedca7b4UL)
+#define IIC_IER_INT4 (0x20b83217UL)
+#define IIC_IER_INT5 (0x57bf0281UL)
+#define IIC_IER_INT6 (0xceb6533bUL)
+#define IIC_IER_INT7 (0xb9b163adUL)
+#define IIC_ISR (0x9f13ff78UL)
+#define IIC_ISR_INT0 (0x23db5ffaUL)
+#define IIC_ISR_INT1 (0x54dc6f6cUL)
+#define IIC_ISR_INT2 (0xcdd53ed6UL)
+#define IIC_ISR_INT3 (0xbad20e40UL)
+#define IIC_ISR_INT4 (0x24b69be3UL)
+#define IIC_ISR_INT5 (0x53b1ab75UL)
+#define IIC_ISR_INT6 (0xcab8facfUL)
+#define IIC_ISR_INT7 (0xbdbfca59UL)
+#define IIC_RX_FIFO (0x46f255afUL)
+#define IIC_RX_FIFO_RXDATA (0x90c24f9dUL)
+#define IIC_RX_FIFO_OCY (0xc6457d11UL)
+#define IIC_RX_FIFO_OCY_OCY_VAL (0xee6b4716UL)
+#define IIC_RX_FIFO_PIRQ (0x4201f0b4UL)
+#define IIC_RX_FIFO_PIRQ_CMP_VAL (0xc5121291UL)
+#define IIC_SOFTR (0xfb3f55bfUL)
+#define IIC_SOFTR_RKEY (0x8c9a6beeUL)
+#define IIC_SR (0x645b677fUL)
+#define IIC_SR_AAS (0x66a5d25dUL)
+#define IIC_SR_ABGC (0x4831e30UL)
+#define IIC_SR_BB (0x1ea7e5d6UL)
+#define IIC_SR_RXFIFO_EMPTY (0xe419563UL)
+#define IIC_SR_RXFIFO_FULL (0x60ecb95aUL)
+#define IIC_SR_SRW (0x1f8520c8UL)
+#define IIC_SR_TXFIFO_EMPTY (0xe17c3083UL)
+#define IIC_SR_TXFIFO_FULL (0x88597319UL)
+#define IIC_TBUF (0xe32a311bUL)
+#define IIC_TBUF_TBUF_VAL (0xd48a5ee6UL)
+#define IIC_TEN_ADR (0xb5d88814UL)
+#define IIC_TEN_ADR_MSB_SLV_ADR (0x1bf3647bUL)
+#define IIC_THDDAT (0x9dc42de9UL)
+#define IIC_THDDAT_THDDAT_VAL (0xa4fe6780UL)
+#define IIC_THDSTA (0xdec59ae3UL)
+#define IIC_THDSTA_THDSTA_VAL (0xc3705793UL)
+#define IIC_THIGH (0x43194ec3UL)
+#define IIC_THIGH_THIGH_VAL (0x320d9d1bUL)
+#define IIC_TLOW (0x3329c638UL)
+#define IIC_TLOW_TLOW_VAL (0x167c1ff3UL)
+#define IIC_TSUDAT (0x6251bb80UL)
+#define IIC_TSUDAT_TSUDAT_VAL (0x7b1fdb1dUL)
+#define IIC_TSUSTA (0x21500c8aUL)
+#define IIC_TSUSTA_TSUSTA_VAL (0x1c91eb0eUL)
+#define IIC_TSUSTO (0xc6e8218dUL)
+#define IIC_TSUSTO_TSUSTO_VAL (0x4a908671UL)
+#define IIC_TX_FIFO (0x25226095UL)
+#define IIC_TX_FIFO_START (0xc24fb6c4UL)
+#define IIC_TX_FIFO_STOP (0xe7ae5f6cUL)
+#define IIC_TX_FIFO_TXDATA (0xbe59e736UL)
+#define IIC_TX_FIFO_OCY (0x2ef0b752UL)
+#define IIC_TX_FIFO_OCY_OCY_VAL (0x73b74c05UL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_IIC_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h
new file mode 100644
index 0000000000..3ad544798c
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h
@@ -0,0 +1,298 @@
+/*
+ * nthw_fpga_reg_defs_mac_pcs.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_MAC_PCS_
+#define _NTHW_FPGA_REG_DEFS_MAC_PCS_
+
+/* MAC_PCS */
+#define NTHW_MOD_MAC_PCS (0x7abe24c7UL)
+#define MAC_PCS_BAD_CODE (0x10d9fce5UL)
+#define MAC_PCS_BAD_CODE_CODE_ERR (0xb08ecc3fUL)
+#define MAC_PCS_BIP_ERR (0x7aead929UL)
+#define MAC_PCS_BIP_ERR_BIP_ERR (0x7e06ff82UL)
+#define MAC_PCS_BLOCK_LOCK (0xa44a8a0bUL)
+#define MAC_PCS_BLOCK_LOCK_LOCK (0x6adfd96bUL)
+#define MAC_PCS_BLOCK_LOCK_CHG (0xf0603b66UL)
+#define MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG (0x9ef4519dUL)
+#define MAC_PCS_CLKRX_FRQ (0x999882b5UL)
+#define MAC_PCS_CLKRX_FRQ_RX_FREQ (0x8b935059UL)
+#define MAC_PCS_CLKTX_FRQ (0x4fc161a8UL)
+#define MAC_PCS_CLKTX_FRQ_TX_FREQ (0x10812ed5UL)
+#define MAC_PCS_DEBOUNCE_CTRL (0x37a3bb69UL)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY (0xf5845748UL)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN (0x1a8a9237UL)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY (0xaceccbf4UL)
+#define MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL (0x7f66469eUL)
+#define MAC_PCS_DRP_CONFIG (0x1281f4d8UL)
+#define MAC_PCS_DRP_CONFIG_DRP_ADR (0x398caa76UL)
+#define MAC_PCS_DRP_CONFIG_DRP_DI (0x83b54c6fUL)
+#define MAC_PCS_DRP_CONFIG_DRP_EN (0x4cae88dUL)
+#define MAC_PCS_DRP_CONFIG_DRP_MOD_ADR (0xc24d1deaUL)
+#define MAC_PCS_DRP_CONFIG_DRP_WREN (0x926388aeUL)
+#define MAC_PCS_DRP_CTRL (0x6df0725eUL)
+#define MAC_PCS_DRP_CTRL_ADR (0x5a9962c8UL)
+#define MAC_PCS_DRP_CTRL_DATA (0x2173d834UL)
+#define MAC_PCS_DRP_CTRL_DBG_BUSY (0x26dd3668UL)
+#define MAC_PCS_DRP_CTRL_DONE (0x9cadcbfcUL)
+#define MAC_PCS_DRP_CTRL_MOD_ADR (0x4352354dUL)
+#define MAC_PCS_DRP_CTRL_WREN (0xbed903edUL)
+#define MAC_PCS_DRP_DATA (0xc221f047UL)
+#define MAC_PCS_DRP_DATA_DRP_DO (0xbeb48b96UL)
+#define MAC_PCS_DRP_DATA_DRP_RDY (0x2238822eUL)
+#define MAC_PCS_FEC_CTRL (0x8eea756UL)
+#define MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN (0xd0c0525eUL)
+#define MAC_PCS_FEC_CW_CNT (0x59e0c4deUL)
+#define MAC_PCS_FEC_CW_CNT_CW_CNT (0xd0b8ee0UL)
+#define MAC_PCS_FEC_ERR_CNT_0 (0xee88619cUL)
+#define MAC_PCS_FEC_ERR_CNT_0_ERR_CNT (0x4fdf126bUL)
+#define MAC_PCS_FEC_ERR_CNT_1 (0x998f510aUL)
+#define MAC_PCS_FEC_ERR_CNT_1_ERR_CNT (0x58a40628UL)
+#define MAC_PCS_FEC_ERR_CNT_2 (0x8600b0UL)
+#define MAC_PCS_FEC_ERR_CNT_2_ERR_CNT (0x61293aedUL)
+#define MAC_PCS_FEC_ERR_CNT_3 (0x77813026UL)
+#define MAC_PCS_FEC_ERR_CNT_3_ERR_CNT (0x76522eaeUL)
+#define MAC_PCS_FEC_LANE_DLY_0 (0xc18f945eUL)
+#define MAC_PCS_FEC_LANE_DLY_0_DLY (0xd9f1d54bUL)
+#define MAC_PCS_FEC_LANE_DLY_1 (0xb688a4c8UL)
+#define MAC_PCS_FEC_LANE_DLY_1_DLY (0xe491fcfbUL)
+#define MAC_PCS_FEC_LANE_DLY_2 (0x2f81f572UL)
+#define MAC_PCS_FEC_LANE_DLY_2_DLY (0xa331862bUL)
+#define MAC_PCS_FEC_LANE_DLY_3 (0x5886c5e4UL)
+#define MAC_PCS_FEC_LANE_DLY_3_DLY (0x9e51af9bUL)
+#define MAC_PCS_FEC_LANE_MAP (0x21d4bd54UL)
+#define MAC_PCS_FEC_LANE_MAP_MAPPING (0x87d12932UL)
+#define MAC_PCS_FEC_STAT (0x2a74290dUL)
+#define MAC_PCS_FEC_STAT_AM_LOCK (0x289b2822UL)
+#define MAC_PCS_FEC_STAT_AM_LOCK_0 (0xc824a589UL)
+#define MAC_PCS_FEC_STAT_AM_LOCK_1 (0xbf23951fUL)
+#define MAC_PCS_FEC_STAT_AM_LOCK_2 (0x262ac4a5UL)
+#define MAC_PCS_FEC_STAT_AM_LOCK_3 (0x512df433UL)
+#define MAC_PCS_FEC_STAT_BLOCK_LOCK (0x6a7d0f5fUL)
+#define MAC_PCS_FEC_STAT_BYPASS (0x2e754185UL)
+#define MAC_PCS_FEC_STAT_FEC_LANE_ALGN (0xfd302594UL)
+#define MAC_PCS_FEC_STAT_HI_SER (0xc3501768UL)
+#define MAC_PCS_FEC_STAT_PCS_LANE_ALGN (0xa8193db8UL)
+#define MAC_PCS_FEC_STAT_VALID (0x90dd6fe1UL)
+#define MAC_PCS_FEC_UCW_CNT (0xd1354660UL)
+#define MAC_PCS_FEC_UCW_CNT_UCW_CNT (0xf90f900UL)
+#define MAC_PCS_FRAMING_ERR (0x73b6341dUL)
+#define MAC_PCS_FRAMING_ERR_FRAMING_ERR (0xd4bfdbf4UL)
+#define MAC_PCS_GTY_CTL (0x325263edUL)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_0 (0x423e0e64UL)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_1 (0x35393ef2UL)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_2 (0xac306f48UL)
+#define MAC_PCS_GTY_CTL_CDR_HOLD_3 (0xdb375fdeUL)
+#define MAC_PCS_GTY_CTL_RX (0x1f131df2UL)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_0 (0x3c2aeb81UL)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_1 (0x4b2ddb17UL)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_2 (0xd2248aadUL)
+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_3 (0xa523ba3bUL)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_0 (0x78b8f7dbUL)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_1 (0xfbfc74dUL)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_2 (0x96b696f7UL)
+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_3 (0xe1b1a661UL)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_0 (0xce64b22bUL)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_1 (0xb96382bdUL)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_2 (0x206ad307UL)
+#define MAC_PCS_GTY_CTL_RX_LPM_EN_3 (0x576de391UL)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_0 (0x80681033UL)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_1 (0xf76f20a5UL)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_2 (0x6e66711fUL)
+#define MAC_PCS_GTY_CTL_RX_POLARITY_3 (0x19614189UL)
+#define MAC_PCS_GTY_CTL_RX_RATE_0 (0x6c6c737dUL)
+#define MAC_PCS_GTY_CTL_RX_RATE_1 (0x1b6b43ebUL)
+#define MAC_PCS_GTY_CTL_RX_RATE_2 (0x82621251UL)
+#define MAC_PCS_GTY_CTL_RX_RATE_3 (0xf56522c7UL)
+#define MAC_PCS_GTY_CTL_TX (0x4949ba74UL)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_0 (0xd2423364UL)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_1 (0xa54503f2UL)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_2 (0x3c4c5248UL)
+#define MAC_PCS_GTY_CTL_TX_INHIBIT_3 (0x4b4b62deUL)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_0 (0x208dcfeeUL)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_1 (0x578aff78UL)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_2 (0xce83aec2UL)
+#define MAC_PCS_GTY_CTL_TX_POLARITY_3 (0xb9849e54UL)
+#define MAC_PCS_GTY_DIFF_CTL (0x8756c12fUL)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0 (0xf08ceefdUL)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1 (0x878bde6bUL)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2 (0x1e828fd1UL)
+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3 (0x6985bf47UL)
+#define MAC_PCS_GTY_LOOP (0x4dd7ddbUL)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_0 (0xd55e5438UL)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_1 (0xa25964aeUL)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_2 (0x3b503514UL)
+#define MAC_PCS_GTY_LOOP_GT_LOOP_3 (0x4c570582UL)
+#define MAC_PCS_GTY_POST_CURSOR (0x4699c607UL)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0 (0x23ff66e9UL)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1 (0x54f8567fUL)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2 (0xcdf107c5UL)
+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3 (0xbaf63753UL)
+#define MAC_PCS_GTY_PRBS_SEL (0x6610ec4eUL)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0 (0xb535fd56UL)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1 (0xc232cdc0UL)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2 (0x5b3b9c7aUL)
+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3 (0x2c3cacecUL)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0 (0x15d0228bUL)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1 (0x62d7121dUL)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2 (0xfbde43a7UL)
+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3 (0x8cd97331UL)
+#define MAC_PCS_GTY_PRE_CURSOR (0x989e0463UL)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0 (0x264242bdUL)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1 (0x5145722bUL)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2 (0xc84c2391UL)
+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3 (0xbf4b1307UL)
+#define MAC_PCS_GTY_RX_BUF_STAT (0xf37901e8UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0 (0xab8b9404UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1 (0xdc8ca492UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2 (0x4585f528UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3 (0x3282c5beUL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0 (0x476782c4UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1 (0x3060b252UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2 (0xa969e3e8UL)
+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3 (0xde6ed37eUL)
+#define MAC_PCS_GTY_SCAN_CTL (0x782ddd2aUL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0 (0xc2791c66UL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1 (0xb57e2cf0UL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2 (0x2c777d4aUL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3 (0x5b704ddcUL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0 (0xebe5938aUL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1 (0x9ce2a31cUL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2 (0x5ebf2a6UL)
+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3 (0x72ecc230UL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0 (0x3243ecaeUL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1 (0x4544dc38UL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2 (0xdc4d8d82UL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3 (0xab4abd14UL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0 (0xf77381daUL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1 (0x8074b14cUL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2 (0x197de0f6UL)
+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3 (0x6e7ad060UL)
+#define MAC_PCS_GTY_SCAN_STAT (0x8070b7b9UL)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0 (0xe5ddd3f9UL)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1 (0x92dae36fUL)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2 (0xbd3b2d5UL)
+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3 (0x7cd48243UL)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0 (0xb0217badUL)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1 (0xc7264b3bUL)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2 (0x5e2f1a81UL)
+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3 (0x29282a17UL)
+#define MAC_PCS_GTY_STAT (0x853a9f14UL)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_0 (0x71cda8d6UL)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_1 (0x6ca9840UL)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_2 (0x9fc3c9faUL)
+#define MAC_PCS_GTY_STAT_RX_RST_DONE_3 (0xe8c4f96cUL)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_0 (0xf766f49eUL)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_1 (0x8061c408UL)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_2 (0x196895b2UL)
+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_3 (0x6e6fa524UL)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_0 (0xd128770bUL)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_1 (0xa62f479dUL)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_2 (0x3f261627UL)
+#define MAC_PCS_GTY_STAT_TX_RST_DONE_3 (0x482126b1UL)
+#define MAC_PCS_LANE_ALIGNER_FILL (0x7f7c92b4UL)
+#define MAC_PCS_LANE_ALIGNER_FILL_FILL (0x5d03a992UL)
+#define MAC_PCS_LINK_SUMMARY (0x7506c2cfUL)
+#define MAC_PCS_LINK_SUMMARY_ABS (0xeaec5364UL)
+#define MAC_PCS_LINK_SUMMARY_LH_ABS (0x75386439UL)
+#define MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT (0xfe0a1d22UL)
+#define MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT (0xe891aedUL)
+#define MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT (0x91098b1fUL)
+#define MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE (0x66c65523UL)
+#define MAC_PCS_LINK_SUMMARY_LOCAL_FAULT (0x87148e11UL)
+#define MAC_PCS_LINK_SUMMARY_NIM_INTERR (0x3d95c18UL)
+#define MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE (0x27ce6435UL)
+#define MAC_PCS_LINK_SUMMARY_REMOTE_FAULT (0xb1206568UL)
+#define MAC_PCS_LINK_SUMMARY_RESERVED (0x254bc0e3UL)
+#define MAC_PCS_MAC_PCS_CONFIG (0x1534e5c0UL)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST (0xe964d0f5UL)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE (0x3301c934UL)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC (0xf01103aUL)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST (0x65a6baccUL)
+#define MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN (0xf932af1bUL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST (0x1d11ab6UL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE (0x401bb0beUL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE (0x25816398UL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST (0x8d13708fUL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE (0xbcff1ba5UL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI (0xc4dd154eUL)
+#define MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN (0xdbc87be9UL)
+#define MAC_PCS_MAX_PKT_LEN (0x396b0d64UL)
+#define MAC_PCS_MAX_PKT_LEN_MAX_LEN (0x6d95b01fUL)
+#define MAC_PCS_MF_ERR (0xb0be669dUL)
+#define MAC_PCS_MF_ERR_MF_ERR (0x6c7b7561UL)
+#define MAC_PCS_MF_LEN_ERR (0x559f33efUL)
+#define MAC_PCS_MF_LEN_ERR_MF_LEN_ERR (0x196e21f6UL)
+#define MAC_PCS_MF_REPEAT_ERR (0xc7dedbb3UL)
+#define MAC_PCS_MF_REPEAT_ERR_MF_REPEAT_ERR (0xb5be34c7UL)
+#define MAC_PCS_PHYMAC_MISC (0x4d213de4UL)
+#define MAC_PCS_PHYMAC_MISC_TS_EOP (0xc9232087UL)
+#define MAC_PCS_PHYMAC_MISC_TX_MUX_STATE (0x761f1c74UL)
+#define MAC_PCS_PHYMAC_MISC_TX_SEL_HOST (0xb50087a5UL)
+#define MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP (0xbe5ce3b1UL)
+#define MAC_PCS_PHYMAC_MISC_TX_SEL_TFG (0x106d1efUL)
+#define MAC_PCS_PHY_STAT (0x533a519cUL)
+#define MAC_PCS_PHY_STAT_ALARM (0x57360efaUL)
+#define MAC_PCS_PHY_STAT_MOD_PRS (0x5d9d2135UL)
+#define MAC_PCS_PHY_STAT_RX_LOS (0xf9354fecUL)
+#define MAC_PCS_STAT_PCS_RX (0xb11d1a0cUL)
+#define MAC_PCS_STAT_PCS_RX_ALIGNED (0xc04d3946UL)
+#define MAC_PCS_STAT_PCS_RX_ALIGNED_ERR (0x82e5aacbUL)
+#define MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS (0xe2ebace5UL)
+#define MAC_PCS_STAT_PCS_RX_HI_BER (0x44ed301UL)
+#define MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT (0xd302122UL)
+#define MAC_PCS_STAT_PCS_RX_LOCAL_FAULT (0x2fd7a554UL)
+#define MAC_PCS_STAT_PCS_RX_MISALIGNED (0x4f8958c8UL)
+#define MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT (0xce46c6b2UL)
+#define MAC_PCS_STAT_PCS_RX_REMOTE_FAULT (0xb73e135cUL)
+#define MAC_PCS_STAT_PCS_RX_STATUS (0x6087afc3UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH (0x12a96a4UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED (0xffeb7af8UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR (0x43af96a9UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS (0x9a4f180dUL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_HI_BER (0x170bb0a7UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT (0x97082914UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT (0xee9d9936UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED (0x64a891f6UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT (0x547ece84UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT (0x14435914UL)
+#define MAC_PCS_STAT_PCS_RX_LATCH_STATUS (0x73c2cc65UL)
+#define MAC_PCS_STAT_PCS_TX (0xe747bd8aUL)
+#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT (0xd715eee2UL)
+#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED (0x125aedaaUL)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR (0x892ad851UL)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED (0xf39f6854UL)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR (0x6075c4dfUL)
+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED (0xcd4c168aUL)
+#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT (0x4483a41fUL)
+#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED (0xcbd66e98UL)
+#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT (0xb65e59a1UL)
+#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED (0x9157fdd8UL)
+#define MAC_PCS_SYNCED (0x76ad78aaUL)
+#define MAC_PCS_SYNCED_SYNC (0xbff0beadUL)
+#define MAC_PCS_SYNCED_ERR (0x136856e9UL)
+#define MAC_PCS_SYNCED_ERR_SYNC_ERROR (0x16c52dc7UL)
+#define MAC_PCS_TEST_ERR (0xbf52be89UL)
+#define MAC_PCS_TEST_ERR_CODE_ERR (0x33a662cUL)
+#define MAC_PCS_TIMESTAMP_COMP (0x3054d1fcUL)
+#define MAC_PCS_TIMESTAMP_COMP_RX_DLY (0xa6496d75UL)
+#define MAC_PCS_TIMESTAMP_COMP_TX_DLY (0x70108e68UL)
+#define MAC_PCS_VL_DEMUXED (0xe1a41659UL)
+#define MAC_PCS_VL_DEMUXED_LOCK (0xf1e85d36UL)
+#define MAC_PCS_VL_DEMUXED_CHG (0xa326d6a6UL)
+#define MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG (0x9327587fUL)
+#define MAC_PCS_VL_NUMBER (0x149d9e3UL)
+#define MAC_PCS_VL_NUMBER_VL_NUMBER (0x3b87c706UL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_MAC_PCS_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h
new file mode 100644
index 0000000000..c21a1b20c3
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h
@@ -0,0 +1,37 @@
+/*
+ * nthw_fpga_reg_defs_pci_rd_tg.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PCI_RD_TG_
+#define _NTHW_FPGA_REG_DEFS_PCI_RD_TG_
+
+/* PCI_RD_TG */
+#define NTHW_MOD_PCI_RD_TG (0x9ad9eed2UL)
+#define PCI_RD_TG_TG_CTRL (0x5a899dc8UL)
+#define PCI_RD_TG_TG_CTRL_TG_RD_RDY (0x66c70bffUL)
+#define PCI_RD_TG_TG_RDADDR (0x39e1af65UL)
+#define PCI_RD_TG_TG_RDADDR_RAM_ADDR (0xf6b0ecd1UL)
+#define PCI_RD_TG_TG_RDDATA0 (0x4bcd36f9UL)
+#define PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW (0xa4479fe8UL)
+#define PCI_RD_TG_TG_RDDATA1 (0x3cca066fUL)
+#define PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH (0x6b3563dfUL)
+#define PCI_RD_TG_TG_RDDATA2 (0xa5c357d5UL)
+#define PCI_RD_TG_TG_RDDATA2_REQ_HID (0x5dab4bc3UL)
+#define PCI_RD_TG_TG_RDDATA2_REQ_SIZE (0x85dd8d92UL)
+#define PCI_RD_TG_TG_RDDATA2_WAIT (0x85ba70b2UL)
+#define PCI_RD_TG_TG_RDDATA2_WRAP (0x546e238aUL)
+#define PCI_RD_TG_TG_RD_RUN (0xd6542f54UL)
+#define PCI_RD_TG_TG_RD_RUN_RD_ITERATION (0xcdc6e166UL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_PCI_RD_TG_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h
new file mode 100644
index 0000000000..491152bb97
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h
@@ -0,0 +1,40 @@
+/*
+ * nthw_fpga_reg_defs_pci_wr_tg.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PCI_WR_TG_
+#define _NTHW_FPGA_REG_DEFS_PCI_WR_TG_
+
+/* PCI_WR_TG */
+#define NTHW_MOD_PCI_WR_TG (0x274b69e1UL)
+#define PCI_WR_TG_TG_CTRL (0xa48366c7UL)
+#define PCI_WR_TG_TG_CTRL_TG_WR_RDY (0x9983a3e8UL)
+#define PCI_WR_TG_TG_SEQ (0x8b3e0bd6UL)
+#define PCI_WR_TG_TG_SEQ_SEQUENCE (0xebf1c760UL)
+#define PCI_WR_TG_TG_WRADDR (0x2b7b95a5UL)
+#define PCI_WR_TG_TG_WRADDR_RAM_ADDR (0x5fdc2aceUL)
+#define PCI_WR_TG_TG_WRDATA0 (0xd0bb6e73UL)
+#define PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW (0x97cb1c89UL)
+#define PCI_WR_TG_TG_WRDATA1 (0xa7bc5ee5UL)
+#define PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH (0x51b3be92UL)
+#define PCI_WR_TG_TG_WRDATA2 (0x3eb50f5fUL)
+#define PCI_WR_TG_TG_WRDATA2_INC_MODE (0x5be5577UL)
+#define PCI_WR_TG_TG_WRDATA2_REQ_HID (0xf4c78ddcUL)
+#define PCI_WR_TG_TG_WRDATA2_REQ_SIZE (0x87ceca1UL)
+#define PCI_WR_TG_TG_WRDATA2_WAIT (0xb29cb8ffUL)
+#define PCI_WR_TG_TG_WRDATA2_WRAP (0x6348ebc7UL)
+#define PCI_WR_TG_TG_WR_RUN (0xc4ce1594UL)
+#define PCI_WR_TG_TG_WR_RUN_WR_ITERATION (0xe83c0a22UL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_PCI_WR_TG_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h
new file mode 100644
index 0000000000..4b8bf53cd9
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h
@@ -0,0 +1,281 @@
+/*
+ * nthw_fpga_reg_defs_pcie3.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_PCIE3_
+#define _NTHW_FPGA_REG_DEFS_PCIE3_
+
+/* PCIE3 */
+#define NTHW_MOD_PCIE3 (0xfbc48c18UL)
+#define PCIE3_BUILD_SEED (0x7a6457c5UL)
+#define PCIE3_BUILD_SEED_BUILD_SEED (0x626b816fUL)
+#define PCIE3_BUILD_TIME (0x51772c86UL)
+#define PCIE3_BUILD_TIME_TIME (0xe6ca8be1UL)
+#define PCIE3_CONFIG (0xe7ef0d51UL)
+#define PCIE3_CONFIG_EXT_TAG (0xce1f05adUL)
+#define PCIE3_CONFIG_MAX_READ (0x2943f801UL)
+#define PCIE3_CONFIG_MAX_TLP (0x2aa40e12UL)
+#define PCIE3_CONTROL (0x935935d4UL)
+#define PCIE3_CONTROL_RD_ATTR (0xc59aa0a3UL)
+#define PCIE3_CONTROL_WRAW (0x1fdd0c42UL)
+#define PCIE3_CONTROL_WR_ATTR (0x422d6e82UL)
+#define PCIE3_CORESPEED (0x5cbe0925UL)
+#define PCIE3_CORESPEED_CORESPEED (0x52ed2515UL)
+#define PCIE3_CORESPEED_DDR3SPEED (0xb69dba56UL)
+#define PCIE3_DRP_COMMON (0xffd331a2UL)
+#define PCIE3_DRP_COMMON_DRP_ADDR (0xbbfbc2fbUL)
+#define PCIE3_DRP_COMMON_DRP_RDY (0x8289f931UL)
+#define PCIE3_DRP_COMMON_GTH_SEL (0x40ac636fUL)
+#define PCIE3_DRP_COMMON_WR (0xbe76449eUL)
+#define PCIE3_DRP_DATE (0xeaae0e97UL)
+#define PCIE3_DRP_DATE_DRP_DATA (0xa27d4522UL)
+#define PCIE3_EP_TO_RP_ERR (0x3784de0fUL)
+#define PCIE3_EP_TO_RP_ERR_ERR_COR (0x3bb2d717UL)
+#define PCIE3_EP_TO_RP_ERR_ERR_FATAL (0xe6571da2UL)
+#define PCIE3_EP_TO_RP_ERR_ERR_NONFATAL (0xb3be48faUL)
+#define PCIE3_INT_CLR (0xcde216faUL)
+#define PCIE3_INT_CLR_AVR (0x1982c8eUL)
+#define PCIE3_INT_CLR_FHM (0x5d9e0821UL)
+#define PCIE3_INT_CLR_INT_0 (0x6cabf375UL)
+#define PCIE3_INT_CLR_INT_1 (0x1bacc3e3UL)
+#define PCIE3_INT_CLR_INT_10 (0xcdc3c020UL)
+#define PCIE3_INT_CLR_INT_11 (0xbac4f0b6UL)
+#define PCIE3_INT_CLR_INT_12 (0x23cda10cUL)
+#define PCIE3_INT_CLR_INT_13 (0x54ca919aUL)
+#define PCIE3_INT_CLR_INT_14 (0xcaae0439UL)
+#define PCIE3_INT_CLR_INT_15 (0xbda934afUL)
+#define PCIE3_INT_CLR_INT_16 (0x24a06515UL)
+#define PCIE3_INT_CLR_INT_17 (0x53a75583UL)
+#define PCIE3_INT_CLR_INT_18 (0xc3184812UL)
+#define PCIE3_INT_CLR_INT_19 (0xb41f7884UL)
+#define PCIE3_INT_CLR_INT_2 (0x82a59259UL)
+#define PCIE3_INT_CLR_INT_20 (0xe6ee93e3UL)
+#define PCIE3_INT_CLR_INT_21 (0x91e9a375UL)
+#define PCIE3_INT_CLR_INT_22 (0x8e0f2cfUL)
+#define PCIE3_INT_CLR_INT_23 (0x7fe7c259UL)
+#define PCIE3_INT_CLR_INT_24 (0xe18357faUL)
+#define PCIE3_INT_CLR_INT_25 (0x9684676cUL)
+#define PCIE3_INT_CLR_INT_26 (0xf8d36d6UL)
+#define PCIE3_INT_CLR_INT_27 (0x788a0640UL)
+#define PCIE3_INT_CLR_INT_28 (0xe8351bd1UL)
+#define PCIE3_INT_CLR_INT_29 (0x9f322b47UL)
+#define PCIE3_INT_CLR_INT_3 (0xf5a2a2cfUL)
+#define PCIE3_INT_CLR_INT_30 (0xfff5a2a2UL)
+#define PCIE3_INT_CLR_INT_31 (0x88f29234UL)
+#define PCIE3_INT_CLR_INT_4 (0x6bc6376cUL)
+#define PCIE3_INT_CLR_INT_5 (0x1cc107faUL)
+#define PCIE3_INT_CLR_INT_6 (0x85c85640UL)
+#define PCIE3_INT_CLR_INT_7 (0xf2cf66d6UL)
+#define PCIE3_INT_CLR_INT_8 (0x62707b47UL)
+#define PCIE3_INT_CLR_INT_9 (0x15774bd1UL)
+#define PCIE3_INT_CLR_PORT (0x4f57e46eUL)
+#define PCIE3_INT_CLR_PPS (0x3d2172d9UL)
+#define PCIE3_INT_CLR_QSPI (0xb3e7d744UL)
+#define PCIE3_INT_CLR_SPIM (0x87c5cc97UL)
+#define PCIE3_INT_CLR_SPIS (0x7dcaf1f4UL)
+#define PCIE3_INT_CLR_STA (0xa8b278ccUL)
+#define PCIE3_INT_CLR_TIMER (0x696afaafUL)
+#define PCIE3_INT_FORC (0x55ea48d8UL)
+#define PCIE3_INT_FORC_AVR (0x5b8cd9ffUL)
+#define PCIE3_INT_FORC_FHM (0x78afd50UL)
+#define PCIE3_INT_FORC_INT_0 (0x9758e745UL)
+#define PCIE3_INT_FORC_INT_1 (0xe05fd7d3UL)
+#define PCIE3_INT_FORC_INT_10 (0xebe10398UL)
+#define PCIE3_INT_FORC_INT_11 (0x9ce6330eUL)
+#define PCIE3_INT_FORC_INT_12 (0x5ef62b4UL)
+#define PCIE3_INT_FORC_INT_13 (0x72e85222UL)
+#define PCIE3_INT_FORC_INT_14 (0xec8cc781UL)
+#define PCIE3_INT_FORC_INT_15 (0x9b8bf717UL)
+#define PCIE3_INT_FORC_INT_16 (0x282a6adUL)
+#define PCIE3_INT_FORC_INT_17 (0x7585963bUL)
+#define PCIE3_INT_FORC_INT_18 (0xe53a8baaUL)
+#define PCIE3_INT_FORC_INT_19 (0x923dbb3cUL)
+#define PCIE3_INT_FORC_INT_2 (0x79568669UL)
+#define PCIE3_INT_FORC_INT_20 (0xc0cc505bUL)
+#define PCIE3_INT_FORC_INT_21 (0xb7cb60cdUL)
+#define PCIE3_INT_FORC_INT_22 (0x2ec23177UL)
+#define PCIE3_INT_FORC_INT_23 (0x59c501e1UL)
+#define PCIE3_INT_FORC_INT_24 (0xc7a19442UL)
+#define PCIE3_INT_FORC_INT_25 (0xb0a6a4d4UL)
+#define PCIE3_INT_FORC_INT_26 (0x29aff56eUL)
+#define PCIE3_INT_FORC_INT_27 (0x5ea8c5f8UL)
+#define PCIE3_INT_FORC_INT_28 (0xce17d869UL)
+#define PCIE3_INT_FORC_INT_29 (0xb910e8ffUL)
+#define PCIE3_INT_FORC_INT_3 (0xe51b6ffUL)
+#define PCIE3_INT_FORC_INT_30 (0xd9d7611aUL)
+#define PCIE3_INT_FORC_INT_31 (0xaed0518cUL)
+#define PCIE3_INT_FORC_INT_4 (0x9035235cUL)
+#define PCIE3_INT_FORC_INT_5 (0xe73213caUL)
+#define PCIE3_INT_FORC_INT_6 (0x7e3b4270UL)
+#define PCIE3_INT_FORC_INT_7 (0x93c72e6UL)
+#define PCIE3_INT_FORC_INT_8 (0x99836f77UL)
+#define PCIE3_INT_FORC_INT_9 (0xee845fe1UL)
+#define PCIE3_INT_FORC_PORT (0x680fb131UL)
+#define PCIE3_INT_FORC_PPS (0x673587a8UL)
+#define PCIE3_INT_FORC_QSPI (0x94bf821bUL)
+#define PCIE3_INT_FORC_SPIM (0xa09d99c8UL)
+#define PCIE3_INT_FORC_SPIS (0x5a92a4abUL)
+#define PCIE3_INT_FORC_STA (0xf2a68dbdUL)
+#define PCIE3_INT_FORC_TIMER (0x9299ee9fUL)
+#define PCIE3_INT_MASK (0x9fb55ba0UL)
+#define PCIE3_INT_MASK_AVR (0xadf52690UL)
+#define PCIE3_INT_MASK_FHM (0xf1f3023fUL)
+#define PCIE3_INT_MASK_IIC0 (0x856e56f1UL)
+#define PCIE3_INT_MASK_IIC1 (0xf2696667UL)
+#define PCIE3_INT_MASK_IIC2 (0x6b6037ddUL)
+#define PCIE3_INT_MASK_IIC3 (0x1c67074bUL)
+#define PCIE3_INT_MASK_IIC4 (0x820392e8UL)
+#define PCIE3_INT_MASK_IIC5 (0xf504a27eUL)
+#define PCIE3_INT_MASK_INT_0 (0x583f89d9UL)
+#define PCIE3_INT_MASK_INT_1 (0x2f38b94fUL)
+#define PCIE3_INT_MASK_INT_10 (0x1297bb99UL)
+#define PCIE3_INT_MASK_INT_11 (0x65908b0fUL)
+#define PCIE3_INT_MASK_INT_12 (0xfc99dab5UL)
+#define PCIE3_INT_MASK_INT_13 (0x8b9eea23UL)
+#define PCIE3_INT_MASK_INT_14 (0x15fa7f80UL)
+#define PCIE3_INT_MASK_INT_15 (0x62fd4f16UL)
+#define PCIE3_INT_MASK_INT_16 (0xfbf41eacUL)
+#define PCIE3_INT_MASK_INT_17 (0x8cf32e3aUL)
+#define PCIE3_INT_MASK_INT_18 (0x1c4c33abUL)
+#define PCIE3_INT_MASK_INT_19 (0x6b4b033dUL)
+#define PCIE3_INT_MASK_INT_2 (0xb631e8f5UL)
+#define PCIE3_INT_MASK_INT_20 (0x39bae85aUL)
+#define PCIE3_INT_MASK_INT_21 (0x4ebdd8ccUL)
+#define PCIE3_INT_MASK_INT_22 (0xd7b48976UL)
+#define PCIE3_INT_MASK_INT_23 (0xa0b3b9e0UL)
+#define PCIE3_INT_MASK_INT_24 (0x3ed72c43UL)
+#define PCIE3_INT_MASK_INT_25 (0x49d01cd5UL)
+#define PCIE3_INT_MASK_INT_26 (0xd0d94d6fUL)
+#define PCIE3_INT_MASK_INT_27 (0xa7de7df9UL)
+#define PCIE3_INT_MASK_INT_28 (0x37616068UL)
+#define PCIE3_INT_MASK_INT_29 (0x406650feUL)
+#define PCIE3_INT_MASK_INT_3 (0xc136d863UL)
+#define PCIE3_INT_MASK_INT_30 (0x20a1d91bUL)
+#define PCIE3_INT_MASK_INT_31 (0x57a6e98dUL)
+#define PCIE3_INT_MASK_INT_4 (0x5f524dc0UL)
+#define PCIE3_INT_MASK_INT_5 (0x28557d56UL)
+#define PCIE3_INT_MASK_INT_6 (0xb15c2cecUL)
+#define PCIE3_INT_MASK_INT_7 (0xc65b1c7aUL)
+#define PCIE3_INT_MASK_INT_8 (0x56e401ebUL)
+#define PCIE3_INT_MASK_INT_9 (0x21e3317dUL)
+#define PCIE3_INT_MASK_PORT (0xb5f4b407UL)
+#define PCIE3_INT_MASK_PPS (0x914c78c7UL)
+#define PCIE3_INT_MASK_QSPI (0x4944872dUL)
+#define PCIE3_INT_MASK_SPIM (0x7d669cfeUL)
+#define PCIE3_INT_MASK_SPIS (0x8769a19dUL)
+#define PCIE3_INT_MASK_STA (0x4df72d2UL)
+#define PCIE3_INT_MASK_TIMER (0x5dfe8003UL)
+#define PCIE3_LAT_CTRL (0x5c509767UL)
+#define PCIE3_LAT_CTRL_CLEAR_RAM (0x8a124a71UL)
+#define PCIE3_LAT_CTRL_ENABLE (0x47ce18e9UL)
+#define PCIE3_LAT_CTRL_PRESCAL (0x471e1378UL)
+#define PCIE3_LAT_CTRL_RAM_VLD (0x8efd11f9UL)
+#define PCIE3_LAT_CTRL_READ_RAM (0x9cfa1247UL)
+#define PCIE3_LAT_CTRL_STATUS (0xcf6eb5c7UL)
+#define PCIE3_LAT_MAX (0x316931d1UL)
+#define PCIE3_LAT_MAX_MAX (0xcb993f8fUL)
+#define PCIE3_LAT_RAMADR (0x745612a7UL)
+#define PCIE3_LAT_RAMADR_ADR (0x7516436aUL)
+#define PCIE3_LAT_RAMDATA (0xfc506b8dUL)
+#define PCIE3_LAT_RAMDATA_DATA (0x73152393UL)
+#define PCIE3_LINK_STATUS (0xab303a44UL)
+#define PCIE3_LINK_STATUS_CLEAR (0x2fda333UL)
+#define PCIE3_LINK_STATUS_RETRAIN_CNT (0xd32d9b1dUL)
+#define PCIE3_MARKADR_LSB (0xbf66115UL)
+#define PCIE3_MARKADR_LSB_ADR (0xfa67c336UL)
+#define PCIE3_MARKADR_MSB (0xa340b22UL)
+#define PCIE3_MARKADR_MSB_ADR (0x5c10c882UL)
+#define PCIE3_PB_INTERVAL (0x6d0029bfUL)
+#define PCIE3_PB_INTERVAL_INTERVAL (0xd3638bc4UL)
+#define PCIE3_PB_MAX_RD (0x14d4cfd0UL)
+#define PCIE3_PB_MAX_RD_PB (0xafae2778UL)
+#define PCIE3_PB_MAX_WR (0x9d778ec4UL)
+#define PCIE3_PB_MAX_WR_PB (0x123ca04bUL)
+#define PCIE3_PCIE_CTRL (0x6a657a79UL)
+#define PCIE3_PCIE_CTRL_EXT_TAG_ENA (0xc0feaf2UL)
+#define PCIE3_PCI_ENDPOINT (0xef3fb5fcUL)
+#define PCIE3_PCI_ENDPOINT_DMA_EP0_ALLOW_MASK (0x96497384UL)
+#define PCIE3_PCI_ENDPOINT_DMA_EP1_ALLOW_MASK (0xdec3febUL)
+#define PCIE3_PCI_ENDPOINT_GET_MSG (0x8d574999UL)
+#define PCIE3_PCI_ENDPOINT_IF_ID (0xe093c118UL)
+#define PCIE3_PCI_ENDPOINT_SEND_MSG (0x3c6e3993UL)
+#define PCIE3_PCI_TEST0 (0x9035b95dUL)
+#define PCIE3_PCI_TEST0_DATA (0xf1e900b8UL)
+#define PCIE3_PCI_TEST1 (0xe73289cbUL)
+#define PCIE3_PCI_TEST1_DATA (0x3ab5d31dUL)
+#define PCIE3_PCI_TEST2 (0x7e3bd871UL)
+#define PCIE3_PCI_TEST2_DATA (0xbc21a1b3UL)
+#define PCIE3_PCI_TEST3 (0x93ce8e7UL)
+#define PCIE3_PCI_TEST3_DATA (0x777d7216UL)
+#define PCIE3_PROD_ID_EX (0x8611a98cUL)
+#define PCIE3_PROD_ID_EX_LAYOUT (0x9df9070dUL)
+#define PCIE3_PROD_ID_EX_LAYOUT_VERSION (0xb1b84c8bUL)
+#define PCIE3_PROD_ID_EX_RESERVED (0x7eaa8a3bUL)
+#define PCIE3_PROD_ID_LSB (0x427df3d7UL)
+#define PCIE3_PROD_ID_LSB_GROUP_ID (0x79fb4c8UL)
+#define PCIE3_PROD_ID_LSB_REV_ID (0xc70a49f8UL)
+#define PCIE3_PROD_ID_LSB_VER_ID (0xd3f99cb9UL)
+#define PCIE3_PROD_ID_MSB (0x43bf99e0UL)
+#define PCIE3_PROD_ID_MSB_BUILD_NO (0xad3c5124UL)
+#define PCIE3_PROD_ID_MSB_PATCH_NO (0x77fde683UL)
+#define PCIE3_PROD_ID_MSB_TYPE_ID (0xdbb9d1adUL)
+#define PCIE3_RESET_CTRL (0xcc9a6c8bUL)
+#define PCIE3_RESET_CTRL_MASK (0xf060fbbcUL)
+#define PCIE3_RP_TO_EP_ERR (0x51d7e85fUL)
+#define PCIE3_RP_TO_EP_ERR_ERR_COR (0x394f4c0dUL)
+#define PCIE3_RP_TO_EP_ERR_ERR_FATAL (0x31a7af48UL)
+#define PCIE3_RP_TO_EP_ERR_ERR_NONFATAL (0x7c85237dUL)
+#define PCIE3_SAMPLE_TIME (0x6c2ab747UL)
+#define PCIE3_SAMPLE_TIME_SAMPLE_TIME (0xae51ac57UL)
+#define PCIE3_STATUS (0x48654731UL)
+#define PCIE3_STATUS_RD_ERR (0x153789c6UL)
+#define PCIE3_STATUS_TAGS_IN_USE (0x4dbe283UL)
+#define PCIE3_STATUS_WR_ERR (0xaa5a7a57UL)
+#define PCIE3_STATUS0 (0xa54dba5cUL)
+#define PCIE3_STATUS0_TAGS_IN_USE (0x67828096UL)
+#define PCIE3_STATUS0_UR_ADDR (0xcbf0c755UL)
+#define PCIE3_STATUS0_UR_DWORD (0x3e60a758UL)
+#define PCIE3_STATUS0_UR_FBE (0xba0c2851UL)
+#define PCIE3_STATUS0_UR_FMT (0x5724146cUL)
+#define PCIE3_STATUS0_UR_LBE (0xb79bad87UL)
+#define PCIE3_STATUS0_UR_REG (0x6cd416UL)
+#define PCIE3_STAT_CTRL (0xdef3e1d7UL)
+#define PCIE3_STAT_CTRL_STAT_ENA (0x613ed39aUL)
+#define PCIE3_STAT_CTRL_STAT_REQ (0x8614afc0UL)
+#define PCIE3_STAT_REFCLK (0xa4423dd2UL)
+#define PCIE3_STAT_REFCLK_REFCLK250 (0xf072561UL)
+#define PCIE3_STAT_RQ_RDY (0x3ab72682UL)
+#define PCIE3_STAT_RQ_RDY_COUNTER (0xbbf817faUL)
+#define PCIE3_STAT_RQ_VLD (0x9661688fUL)
+#define PCIE3_STAT_RQ_VLD_COUNTER (0x457981aaUL)
+#define PCIE3_STAT_RX (0xf2a8e7a1UL)
+#define PCIE3_STAT_RX_COUNTER (0x8d8ef524UL)
+#define PCIE3_STAT_TX (0xa4f24027UL)
+#define PCIE3_STAT_TX_COUNTER (0x80908563UL)
+#define PCIE3_TEST0 (0xa0e404f1UL)
+#define PCIE3_TEST0_DATA (0xf82b8d9cUL)
+#define PCIE3_TEST1 (0xd7e33467UL)
+#define PCIE3_TEST1_DATA (0x33775e39UL)
+#define PCIE3_TEST2_DATA (0x7151e5e8UL)
+#define PCIE3_TEST3_DATA (0xba0d364dUL)
+#define PCIE3_UUID0 (0x96ee4e29UL)
+#define PCIE3_UUID0_UUID0 (0x459d36b3UL)
+#define PCIE3_UUID1 (0xe1e97ebfUL)
+#define PCIE3_UUID1_UUID1 (0x94ed0d91UL)
+#define PCIE3_UUID2 (0x78e02f05UL)
+#define PCIE3_UUID2_UUID2 (0x3c0c46b6UL)
+#define PCIE3_UUID3 (0xfe71f93UL)
+#define PCIE3_UUID3_UUID3 (0xed7c7d94UL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_PCIE3_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h
new file mode 100644
index 0000000000..b4af411b47
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h
@@ -0,0 +1,72 @@
+/*
+ * nthw_fpga_reg_defs_rac.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_RAC_
+#define _NTHW_FPGA_REG_DEFS_RAC_
+
+/* RAC */
+#define NTHW_MOD_RAC (0xae830b42UL)
+#define RAC_DBG_CTRL (0x587273e2UL)
+#define RAC_DBG_CTRL_C (0x4fe263UL)
+#define RAC_DBG_DATA (0xf7a3f1fbUL)
+#define RAC_DBG_DATA_D (0x69d9305UL)
+#define RAC_DUMMY0 (0xd8e9ed5bUL)
+#define RAC_DUMMY1 (0xafeeddcdUL)
+#define RAC_DUMMY2 (0x36e78c77UL)
+#define RAC_NDM_REGISTER (0x36b9e7d0UL)
+#define RAC_NDM_REGISTER_NDM (0xf791ef23UL)
+#define RAC_NMB_DATA (0xc0e60c69UL)
+#define RAC_NMB_DATA_NMB_DATA (0x21f71466UL)
+#define RAC_NMB_RD_ADR (0x274e1df2UL)
+#define RAC_NMB_RD_ADR_ADR (0xf2e063d0UL)
+#define RAC_NMB_RD_ADR_RES (0x829c7f2eUL)
+#define RAC_NMB_STATUS (0x2070b64UL)
+#define RAC_NMB_STATUS_BUS_TIMEOUT (0x7b220848UL)
+#define RAC_NMB_STATUS_NMB_READY (0xe67a182bUL)
+#define RAC_NMB_WR_ADR (0x9823ee63UL)
+#define RAC_NMB_WR_ADR_ADR (0xcb13936fUL)
+#define RAC_NMB_WR_ADR_RES (0xbb6f8f91UL)
+#define RAC_RAB_BUF_FREE (0x60f7f2d8UL)
+#define RAC_RAB_BUF_FREE_IB_FREE (0x4ddd870fUL)
+#define RAC_RAB_BUF_FREE_IB_OVF (0x92388832UL)
+#define RAC_RAB_BUF_FREE_OB_FREE (0x2e0db235UL)
+#define RAC_RAB_BUF_FREE_OB_OVF (0x44616b2fUL)
+#define RAC_RAB_BUF_FREE_TIMEOUT (0x1d0ae34eUL)
+#define RAC_RAB_BUF_USED (0x549e5008UL)
+#define RAC_RAB_BUF_USED_FLUSH (0xeb99f9baUL)
+#define RAC_RAB_BUF_USED_IB_USED (0xd4c7d150UL)
+#define RAC_RAB_BUF_USED_OB_USED (0xb717e46aUL)
+#define RAC_RAB_DMA_IB_HI (0x3adf4e92UL)
+#define RAC_RAB_DMA_IB_HI_PHYADDR (0x482070e9UL)
+#define RAC_RAB_DMA_IB_LO (0xb7d02ea3UL)
+#define RAC_RAB_DMA_IB_LO_PHYADDR (0x32d1a919UL)
+#define RAC_RAB_DMA_IB_RD (0xf443c8f4UL)
+#define RAC_RAB_DMA_IB_RD_PTR (0xa19bede2UL)
+#define RAC_RAB_DMA_IB_WR (0x7de089e0UL)
+#define RAC_RAB_DMA_IB_WR_PTR (0x1ef61e73UL)
+#define RAC_RAB_DMA_OB_HI (0xb59fbb32UL)
+#define RAC_RAB_DMA_OB_HI_PHYADDR (0xe8c5af34UL)
+#define RAC_RAB_DMA_OB_LO (0x3890db03UL)
+#define RAC_RAB_DMA_OB_LO_PHYADDR (0x923476c4UL)
+#define RAC_RAB_DMA_OB_WR (0xf2a07c40UL)
+#define RAC_RAB_DMA_OB_WR_PTR (0x6dec67f9UL)
+#define RAC_RAB_IB_DATA (0xea524b52UL)
+#define RAC_RAB_IB_DATA_D (0x52ecd3c6UL)
+#define RAC_RAB_INIT (0x47d5556eUL)
+#define RAC_RAB_INIT_RAB (0xda582a35UL)
+#define RAC_RAB_OB_DATA (0x89827e68UL)
+#define RAC_RAB_OB_DATA_D (0x21f6aa4cUL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_RAC_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h
new file mode 100644
index 0000000000..0a1fecd649
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h
@@ -0,0 +1,59 @@
+/*
+ * nthw_fpga_reg_defs_rst9563.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_RST9563_
+#define _NTHW_FPGA_REG_DEFS_RST9563_
+
+/* RST9563 */
+#define NTHW_MOD_RST9563 (0x385d6d1dUL)
+#define RST9563_CTRL (0x8fe7585fUL)
+#define RST9563_CTRL_PTP_MMCM_CLKSEL (0xf441b405UL)
+#define RST9563_CTRL_TS_CLKSEL (0x210e9a78UL)
+#define RST9563_CTRL_TS_CLKSEL_OVERRIDE (0x304bbf3UL)
+#define RST9563_POWER (0xdb6d3006UL)
+#define RST9563_POWER_PU_NSEB (0x68a55de6UL)
+#define RST9563_POWER_PU_PHY (0xdc0b7719UL)
+#define RST9563_RST (0x366a2a03UL)
+#define RST9563_RST_CORE_MMCM (0x4055af70UL)
+#define RST9563_RST_DDR4 (0x367cad64UL)
+#define RST9563_RST_MAC_RX (0x46da79e6UL)
+#define RST9563_RST_PERIPH (0xd39d53bdUL)
+#define RST9563_RST_PHY (0x50c57f90UL)
+#define RST9563_RST_PTP (0xcf6e9a69UL)
+#define RST9563_RST_PTP_MMCM (0xf69029c8UL)
+#define RST9563_RST_RPP (0xa8868b03UL)
+#define RST9563_RST_SDC (0x35477bfUL)
+#define RST9563_RST_SYS (0xe18f0bc7UL)
+#define RST9563_RST_SYS_MMCM (0x9f5c3d45UL)
+#define RST9563_RST_TMC (0xd7d9da73UL)
+#define RST9563_RST_TS (0x216dd0e7UL)
+#define RST9563_RST_TSM_REF_MMCM (0x664f1a24UL)
+#define RST9563_RST_TS_MMCM (0xce54ff59UL)
+#define RST9563_STAT (0xad7dd604UL)
+#define RST9563_STAT_CORE_MMCM_LOCKED (0xfd6d0a5aUL)
+#define RST9563_STAT_DDR4_MMCM_LOCKED (0xb902f1d0UL)
+#define RST9563_STAT_DDR4_PLL_LOCKED (0xe8a6d1b9UL)
+#define RST9563_STAT_PTP_MMCM_LOCKED (0x4e4fd2a9UL)
+#define RST9563_STAT_SYS_MMCM_LOCKED (0x5502a445UL)
+#define RST9563_STAT_TS_MMCM_LOCKED (0xe6405b02UL)
+#define RST9563_STICKY (0x97e2efe3UL)
+#define RST9563_STICKY_CORE_MMCM_UNLOCKED (0xac340bb6UL)
+#define RST9563_STICKY_DDR4_MMCM_UNLOCKED (0x4737148cUL)
+#define RST9563_STICKY_DDR4_PLL_UNLOCKED (0xf9857d1bUL)
+#define RST9563_STICKY_PTP_MMCM_UNLOCKED (0x2a4e9819UL)
+#define RST9563_STICKY_SYS_MMCM_UNLOCKED (0x61e3ebbdUL)
+#define RST9563_STICKY_TS_MMCM_UNLOCKED (0x7e9f941eUL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_RST9563_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h
new file mode 100644
index 0000000000..ed3a25ebfa
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h
@@ -0,0 +1,44 @@
+/*
+ * nthw_fpga_reg_defs_sdc.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_SDC_
+#define _NTHW_FPGA_REG_DEFS_SDC_
+
+/* SDC */
+#define NTHW_MOD_SDC (0xd2369530UL)
+#define SDC_CELL_CNT (0xc6d82110UL)
+#define SDC_CELL_CNT_CELL_CNT (0xdd4de629UL)
+#define SDC_CELL_CNT_PERIOD (0x8dfef1d4UL)
+#define SDC_CELL_CNT_PERIOD_CELL_CNT_PERIOD (0x2b5819c1UL)
+#define SDC_CTRL (0x1577b205UL)
+#define SDC_CTRL_INIT (0x70e62104UL)
+#define SDC_CTRL_RESET_POINTERS (0xec1c0f9cUL)
+#define SDC_CTRL_RUN_TEST (0x2efbe98eUL)
+#define SDC_CTRL_STOP_CLIENT (0xb11ebe2dUL)
+#define SDC_CTRL_TEST_EN (0xaa1fa4UL)
+#define SDC_FILL_LVL (0xd3b30232UL)
+#define SDC_FILL_LVL_FILL_LVL (0xc97281acUL)
+#define SDC_MAX_FILL_LVL (0x326de743UL)
+#define SDC_MAX_FILL_LVL_MAX_FILL_LVL (0x915fbf73UL)
+#define SDC_STAT (0x37ed3c5eUL)
+#define SDC_STAT_CALIB (0x27122e80UL)
+#define SDC_STAT_CELL_CNT_STOPPED (0x517d5cafUL)
+#define SDC_STAT_ERR_FOUND (0x3bb6bd0UL)
+#define SDC_STAT_INIT_DONE (0x1dc2e095UL)
+#define SDC_STAT_MMCM_LOCK (0xd9aac1c2UL)
+#define SDC_STAT_PLL_LOCK (0x3bcab6ebUL)
+#define SDC_STAT_RESETTING (0xa85349c1UL)
+
+#endif /* _NTHW_FPGA_REG_DEFS_SDC_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
+
+/*
+ * EOF
+ */
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index 23af812e05..7acffaebdd 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -14,6 +14,7 @@
#include "ntdrv_4ga.h"
#include "ntos_drv.h"
#include "ntos_system.h"
+#include "nthw_fpga_instances.h"
#include "ntnic_vfio.h"
#include "ntnic_mod_reg.h"
#include "nt_util.h"
--
2.45.0
next prev parent reply other threads:[~2024-06-27 7:41 UTC|newest]
Thread overview: 101+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
2024-05-30 14:48 ` [PATCH v1 02/17] net/ntnic: add core platform functionality Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 03/17] net/ntnic: add interfaces for " Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 04/17] net/ntnic: add FPGA model implementation Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 05/17] net/ntnic: add NTNIC adapter interfaces Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 06/17] net/ntnic: add interfaces for PMD driver modules Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 07/17] net/ntnic: add API " Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 08/17] net/ntnic: add interfaces for flow API engine Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 09/17] net/ntnic: add VFIO module Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 10/17] net/ntnic: add Logs and utilities implementation Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 11/17] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 12/17] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 13/17] net/ntnic: add adapter initialization Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 14/17] net/ntnic: add adapter initialization API Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 15/17] net/ntnic: add link management module Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 16/17] net/ntnic: add link 100G module Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 17/17] net/ntnic: add NIM module Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 02/17] net/ntnic: add core platform functionality Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 03/17] net/ntnic: add interfaces for " Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 04/17] net/ntnic: add FPGA model implementation Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 05/17] net/ntnic: add NTNIC adapter interfaces Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 06/17] net/ntnic: add interfaces for PMD driver modules Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 07/17] net/ntnic: add API " Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 08/17] net/ntnic: add interfaces for flow API engine Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 09/17] net/ntnic: add VFIO module Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 10/17] net/ntnic: add Logs and utilities implementation Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 11/17] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 12/17] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 13/17] net/ntnic: add adapter initialization Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 14/17] net/ntnic: add adapter initialization API Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 15/17] net/ntnic: add link management module Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 16/17] net/ntnic: add link 100G module Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 17/17] net/ntnic: add NIM module Serhii Iliushyk
2024-06-03 16:17 ` [PATCH v3 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
2024-06-03 16:17 ` [PATCH v3 02/17] net/ntnic: add core platform functionality Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 03/17] net/ntnic: add interfaces for " Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 04/17] net/ntnic: add FPGA model implementation Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 05/17] net/ntnic: add NTNIC adapter interfaces Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 06/17] net/ntnic: add interfaces for PMD driver modules Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 07/17] net/ntnic: add API " Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 08/17] net/ntnic: add interfaces for flow API engine Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 09/17] net/ntnic: add VFIO module Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 10/17] net/ntnic: add Logs and utilities implementation Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 11/17] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 12/17] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 13/17] net/ntnic: add adapter initialization Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 14/17] net/ntnic: add adapter initialization API Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 15/17] net/ntnic: add link management module Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 16/17] net/ntnic: add link 100G module Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 17/17] net/ntnic: add NIM module Serhii Iliushyk
2024-06-04 10:29 ` [PATCH v3 01/17] net/ntnic: Add registers for NapaTech SmartNiC Mykola Kostenok
2024-06-07 13:03 ` Serhii Iliushyk
2024-06-12 8:50 ` Ferruh Yigit
2024-06-12 8:55 ` Ferruh Yigit
2024-06-26 19:55 ` [PATCH v4 01/23] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 02/23] net/ntnic: add logging implementation Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 03/23] net/ntnic: add minimal initialization for PCI device Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 04/23] net/ntnic: add NT utilities implementation Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 05/23] net/ntnic: add VFIO module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 06/23] net/ntnic: add NT NIC driver dependencies Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 07/23] net/ntnic: add core platform functionality Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 08/23] net/ntnic: add adapter initialization Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 09/23] net/ntnic: add registers and FPGA model for NapaTech NIC Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 10/23] net/ntnic: add core platform functionality Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 11/23] net/ntnic: add FPGA initialization functionality Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 12/23] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 13/23] net/ntnic: add reset module for " Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 14/23] net/ntnic: add clock profiles " Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 15/23] net/ntnic: add MAC and packet features Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 16/23] net/ntnic: add link management module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 17/23] net/ntnic: add link 100G module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 18/23] net/ntnic: add NIM module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 19/23] net/ntnic: add QSFP support Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 20/23] net/ntnic: add QSFP28 support Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 21/23] net/ntnic: add GPIO PHY module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 22/23] net/ntnic: add MAC PCS register interface module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 23/23] net/ntnic: add GMF (Generic MAC Feeder) module Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 01/23] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 02/23] net/ntnic: add logging implementation Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 03/23] net/ntnic: add minimal initialization for PCI device Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 04/23] net/ntnic: add NT utilities implementation Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 05/23] net/ntnic: add VFIO module Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 06/23] net/ntnic: add NT NIC driver dependencies Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 07/23] net/ntnic: add core platform functionality Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 08/23] net/ntnic: add adapter initialization Serhii Iliushyk
2024-06-27 7:38 ` Serhii Iliushyk [this message]
2024-06-27 7:38 ` [PATCH v5 10/23] net/ntnic: add core platform functionality Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 11/23] net/ntnic: add FPGA initialization functionality Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 12/23] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 13/23] net/ntnic: add reset module for " Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 14/23] net/ntnic: add clock profiles " Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 15/23] net/ntnic: add MAC and packet features Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 16/23] net/ntnic: add link management module Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 17/23] net/ntnic: add link 100G module Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 18/23] net/ntnic: add NIM module Serhii Iliushyk
2024-06-27 7:39 ` [PATCH v5 19/23] net/ntnic: add QSFP support Serhii Iliushyk
2024-06-27 7:39 ` [PATCH v5 20/23] net/ntnic: add QSFP28 support Serhii Iliushyk
2024-06-27 7:39 ` [PATCH v5 21/23] net/ntnic: add GPIO PHY module Serhii Iliushyk
2024-06-27 7:39 ` [PATCH v5 22/23] net/ntnic: add MAC PCS register interface module Serhii Iliushyk
2024-06-27 7:39 ` [PATCH v5 23/23] net/ntnic: add GMF (Generic MAC Feeder) module Serhii Iliushyk
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