From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C78C341F41; Thu, 27 Jun 2024 11:09:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B5118406BC; Thu, 27 Jun 2024 11:09:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 5E8B6402C6 for ; Thu, 27 Jun 2024 11:09:08 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45R7ZZoh021299 for ; Thu, 27 Jun 2024 02:09:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=pfpt0220; bh=02hyKXG0ZrR4VJYFdnEDQWM BoolIWUhwNXUz823nSB4=; b=jss8FCnNv9CzDkDEY7RP1AB3bid4dvGLcxsoJyk fus08FGSV+8HznJGIKI3gA3zaonoco0uFwXpGgKPa/Yd2kYjEnMoob28DRedDbZ8 JkkwNYC5CT+ix7moNDYtsqGyJTn8SALK80AGkOU5TcDy2Id+LDNvAYGa5Rbo9qjz apoIbgFT9LuVr+3msBOgMe/E7DMhN/lyLJfPMbCi8jHROS8cD6GUR8eC7XKddJqx j///4TUwpkWXPTk9uTXWxCKxmXH7nnyFEogV1qgV5xLTNNT83UGzDgvkcKNh/edw LAXPvxsA6NZqMXOcEHfy4QbaVFITaK9PRQPGSO4WiQaWZBQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 400rkg25wy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 27 Jun 2024 02:09:06 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 27 Jun 2024 02:09:05 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 27 Jun 2024 02:09:05 -0700 Received: from localhost.localdomain (unknown [10.28.36.158]) by maili.marvell.com (Postfix) with ESMTP id 8D8B83F7086; Thu, 27 Jun 2024 02:09:02 -0700 (PDT) From: Rahul Bhansali To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Rahul Bhansali Subject: [PATCH 1/2] common/cnxk: enable second pass RQ in mask config Date: Thu, 27 Jun 2024 14:38:58 +0530 Message-ID: <20240627090859.2860207-1-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: Xwg2psYC6uybGIYXPI5uWgPcrq-OgZnm X-Proofpoint-ORIG-GUID: Xwg2psYC6uybGIYXPI5uWgPcrq-OgZnm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-27_05,2024-06-25_01,2024-05-17_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This will enable second pass RQ and drop interrupt by default in mask configuration to avoid buffer leak possibilities during dev stop and interrupts to indicate drops if any. Signed-off-by: Rahul Bhansali --- drivers/common/cnxk/roc_features.h | 6 ++++++ drivers/common/cnxk/roc_nix_inl.c | 9 ++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_features.h b/drivers/common/cnxk/roc_features.h index 3b512be132..6abb35c296 100644 --- a/drivers/common/cnxk/roc_features.h +++ b/drivers/common/cnxk/roc_features.h @@ -90,4 +90,10 @@ roc_feature_nix_has_rx_inject(void) return (roc_model_is_cn10ka_b0() || roc_model_is_cn10kb()); } +static inline bool +roc_feature_nix_has_second_pass_drop(void) +{ + return 0; +} + #endif diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 74a688abbd..a984ac56d9 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -734,6 +734,13 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable) msk_req->rq_set.xqe_drop_ena = 0; msk_req->rq_set.spb_ena = 1; + if (!roc_feature_nix_has_second_pass_drop()) { + msk_req->rq_set.ena = 1; + msk_req->rq_set.rq_int_ena = 1; + msk_req->rq_mask.ena = 0; + msk_req->rq_mask.rq_int_ena = 0; + } + msk_req->rq_mask.len_ol3_dis = 0; msk_req->rq_mask.len_ol4_dis = 0; msk_req->rq_mask.len_il3_dis = 0; @@ -1467,7 +1474,7 @@ roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool enable) if (!idev) return -EFAULT; - if (roc_feature_nix_has_inl_rq_mask()) { + if (roc_feature_nix_has_inl_rq_mask() && enable) { rc = nix_inl_rq_mask_cfg(roc_nix, enable); if (rc) { plt_err("Failed to get rq mask rc=%d", rc); -- 2.25.1