From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3AD694554D; Tue, 2 Jul 2024 16:46:57 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7F8F040C35; Tue, 2 Jul 2024 16:46:47 +0200 (CEST) Received: from smtp-fw-80007.amazon.com (smtp-fw-80007.amazon.com [99.78.197.218]) by mails.dpdk.org (Postfix) with ESMTP id 3EFC840B97 for ; Tue, 2 Jul 2024 16:46:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1719931607; x=1751467607; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=6rmwpd6QnWuKT3E7YV7/6SXWdflCKEznxvlXYJehzaQ=; b=gqt/QAn2FnPDw0b1fM5YflgJdMRcVny/Q9/k8HDyFhRJU5IDotKS3++z u4S1N6DdOd9g5Nz3RYG9wpeyfSqVUL0Z5lHQlkIyP3E2MIsza81Z1YuHY XtD+yV/SgSHSKJKaQ3Q8ZKiBEl0Vf13zHIqHtv2/+jJ/iE4OzQaQHGLhf U=; X-IronPort-AV: E=Sophos;i="6.09,178,1716249600"; d="scan'208";a="307931823" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.25.36.210]) by smtp-border-fw-80007.pdx80.corp.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 14:46:42 +0000 Received: from EX19MTAEUA002.ant.amazon.com [10.0.17.79:10089] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.1.13:2525] with esmtp (Farcaster) id bd78dc6b-9b29-4b81-b574-97f61b9fbc24; Tue, 2 Jul 2024 14:46:41 +0000 (UTC) X-Farcaster-Flow-ID: bd78dc6b-9b29-4b81-b574-97f61b9fbc24 Received: from EX19D007EUA001.ant.amazon.com (10.252.50.133) by EX19MTAEUA002.ant.amazon.com (10.252.50.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34; Tue, 2 Jul 2024 14:46:40 +0000 Received: from EX19MTAUWB001.ant.amazon.com (10.250.64.248) by EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34; Tue, 2 Jul 2024 14:46:39 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.173) by mail-relay.amazon.com (10.250.64.254) with Microsoft SMTP Server id 15.2.1258.34 via Frontend Transport; Tue, 2 Jul 2024 14:46:38 +0000 From: To: CC: , Shai Brandes Subject: [PATCH 04/15] net/ena/base: update memory barrier comment Date: Tue, 2 Jul 2024 17:46:15 +0300 Message-ID: <20240702144626.14545-5-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240702144626.14545-1-shaibran@amazon.com> References: <20240702144626.14545-1-shaibran@amazon.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Update the comment above the phase bit descriptor read in AENQ processing. Signed-off-by: Shai Brandes --- drivers/net/ena/base/ena_com.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index f9dd086484..ad4f3f9431 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -2409,8 +2409,12 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) /* Go over all the events */ while ((READ_ONCE8(aenq_common->flags) & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) { - /* Make sure the device finished writing the rest of the descriptor - * before reading it. + /* When the phase bit of the AENQ descriptor aligns with the driver's phase bit, + * it signifies the readiness of the entire AENQ descriptor. + * The driver should proceed to read the descriptor's data only after confirming + * and synchronizing the phase bit. + * This memory fence guarantees the correct sequence of accesses to the + * descriptor's memory. */ dma_rmb(); @@ -2468,8 +2472,12 @@ bool ena_com_aenq_has_keep_alive(struct ena_com_dev *ena_dev) /* Go over all the events */ while ((READ_ONCE8(aenq_common->flags) & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) { - /* Make sure the device finished writing the rest of the descriptor - * before reading it. + /* When the phase bit of the AENQ descriptor aligns with the driver's phase bit, + * it signifies the readiness of the entire AENQ descriptor. + * The driver should proceed to read the descriptor's data only after confirming + * and synchronizing the phase bit. + * This memory fence guarantees the correct sequence of accesses to the + * descriptor's memory. */ dma_rmb(); -- 2.17.1