From: <shaibran@amazon.com>
To: <ferruh.yigit@amd.com>
Cc: <dev@dpdk.org>, Shai Brandes <shaibran@amazon.com>
Subject: [PATCH 08/15] net/ena/base: add macro for bitfield access
Date: Tue, 2 Jul 2024 17:46:19 +0300 [thread overview]
Message-ID: <20240702144626.14545-9-shaibran@amazon.com> (raw)
In-Reply-To: <20240702144626.14545-1-shaibran@amazon.com>
From: Shai Brandes <shaibran@amazon.com>
Add ENA_FIELD_GET and ENA_FIELD_PREP macro to make access to
fields more readable.
Signed-off-by: Shai Brandes <shaibran@amazon.com>
---
drivers/net/ena/base/ena_com.c | 111 ++++++++++++--------
drivers/net/ena/base/ena_com.h | 10 +-
drivers/net/ena/base/ena_eth_com.c | 146 +++++++++++++++------------
drivers/net/ena/base/ena_eth_com.h | 8 +-
drivers/net/ena/base/ena_plat_dpdk.h | 3 +
5 files changed, 165 insertions(+), 113 deletions(-)
diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c
index 5f46e692b3..e5f1a31c9e 100644
--- a/drivers/net/ena/base/ena_com.c
+++ b/drivers/net/ena/base/ena_com.c
@@ -162,10 +162,13 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev,
ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
aenq_caps = 0;
- aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
- aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
- ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
- ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
+ aenq_caps |= ENA_FIELD_PREP(ena_dev->aenq.q_depth,
+ ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK,
+ ENA_ZERO_SHIFT);
+
+ aenq_caps |= ENA_FIELD_PREP(sizeof(struct ena_admin_aenq_entry),
+ ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK,
+ ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT);
ENA_REG_WRITE32(ena_dev->bus, aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
if (unlikely(!aenq_handlers)) {
@@ -856,8 +859,9 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
mmio_read->seq_num++;
read_resp->req_id = mmio_read->seq_num + 0xDEAD;
- mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
- ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
+ mmio_read_reg = ENA_FIELD_PREP(offset,
+ ENA_REGS_MMIO_REG_READ_REG_OFF_MASK,
+ ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT);
mmio_read_reg |= mmio_read->seq_num &
ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
@@ -927,9 +931,10 @@ static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
else
direction = ENA_ADMIN_SQ_DIRECTION_RX;
- destroy_cmd.sq.sq_identity |= (direction <<
- ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
- ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
+ destroy_cmd.sq.sq_identity |=
+ ENA_FIELD_PREP(direction,
+ ENA_ADMIN_SQ_SQ_DIRECTION_MASK,
+ ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT);
destroy_cmd.sq.sq_idx = io_sq->idx;
destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
@@ -1267,16 +1272,18 @@ static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
else
direction = ENA_ADMIN_SQ_DIRECTION_RX;
- create_cmd.sq_identity |= (direction <<
- ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
- ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
+ create_cmd.sq_identity |=
+ ENA_FIELD_PREP(direction,
+ ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK,
+ ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT);
create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
- create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
- ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
- ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
+ create_cmd.sq_caps_2 |=
+ ENA_FIELD_PREP(ENA_ADMIN_COMPLETION_POLICY_DESC,
+ ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK,
+ ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT);
create_cmd.sq_caps_3 |=
ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
@@ -1616,8 +1623,9 @@ int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
return ENA_COM_TIMER_EXPIRED;
}
- width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
- ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
+ width = ENA_FIELD_GET(caps,
+ ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK,
+ ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT);
ena_trc_dbg(ena_dev, "ENA dma width: %d\n", width);
@@ -1651,18 +1659,26 @@ int ena_com_validate_version(struct ena_com_dev *ena_dev)
}
ena_trc_info(ena_dev, "ENA device version: %d.%d\n",
- (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
- ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
- ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
+ ENA_FIELD_GET(ver,
+ ENA_REGS_VERSION_MAJOR_VERSION_MASK,
+ ENA_REGS_VERSION_MAJOR_VERSION_SHIFT),
+ ENA_FIELD_GET(ver,
+ ENA_REGS_VERSION_MINOR_VERSION_MASK,
+ ENA_ZERO_SHIFT));
ena_trc_info(ena_dev, "ENA controller version: %d.%d.%d implementation version %d\n",
- (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
- >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
- (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
- >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
- (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
- (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
- ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
+ ENA_FIELD_GET(ctrl_ver,
+ ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK,
+ ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT),
+ ENA_FIELD_GET(ctrl_ver,
+ ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK,
+ ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT),
+ ENA_FIELD_GET(ctrl_ver,
+ ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK,
+ ENA_ZERO_SHIFT),
+ ENA_FIELD_GET(ctrl_ver,
+ ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK,
+ ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT));
ctrl_ver_masked =
(ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
@@ -2117,16 +2133,20 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev,
ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
aq_caps = 0;
- aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
- aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
- ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
- ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
+ aq_caps |= ENA_FIELD_PREP(admin_queue->q_depth,
+ ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK,
+ ENA_ZERO_SHIFT);
+ aq_caps |= ENA_FIELD_PREP(sizeof(struct ena_admin_aq_entry),
+ ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK,
+ ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT);
acq_caps = 0;
- acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
- acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
- ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
- ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
+ acq_caps |= ENA_FIELD_PREP(admin_queue->q_depth,
+ ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK,
+ ENA_ZERO_SHIFT);
+ acq_caps |= ENA_FIELD_PREP(sizeof(struct ena_admin_acq_entry),
+ ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK,
+ ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT);
ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
@@ -2521,8 +2541,9 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev,
return ENA_COM_INVAL;
}
- timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
- ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
+ timeout = ENA_FIELD_GET(cap,
+ ENA_REGS_CAPS_RESET_TIMEOUT_MASK,
+ ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT);
if (timeout == 0) {
ena_trc_err(ena_dev, "Invalid timeout value\n");
return ENA_COM_INVAL;
@@ -2534,10 +2555,12 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev,
/* For backward compatibility, device will interpret
* bits 24-27 as MSB, bits 28-31 as LSB
*/
- reset_reason_lsb = ENA_FIELD_GET(reset_reason, ENA_RESET_REASON_LSB_MASK,
+ reset_reason_lsb = ENA_FIELD_GET(reset_reason,
+ ENA_RESET_REASON_LSB_MASK,
ENA_RESET_REASON_LSB_OFFSET);
- reset_reason_msb = ENA_FIELD_GET(reset_reason, ENA_RESET_REASON_MSB_MASK,
+ reset_reason_msb = ENA_FIELD_GET(reset_reason,
+ ENA_RESET_REASON_MSB_MASK,
ENA_RESET_REASON_MSB_OFFSET);
reset_val |= reset_reason_lsb << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT;
@@ -2549,8 +2572,9 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev,
* extended reset reason fallback to generic
*/
reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
- reset_val |= (ENA_REGS_RESET_GENERIC << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
- ENA_REGS_DEV_CTL_RESET_REASON_MASK;
+ reset_val |= ENA_FIELD_PREP(ENA_REGS_RESET_GENERIC,
+ ENA_REGS_DEV_CTL_RESET_REASON_MASK,
+ ENA_REGS_DEV_CTL_RESET_REASON_SHIFT);
}
ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
@@ -2572,8 +2596,9 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev,
return rc;
}
- timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
- ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
+ timeout = ENA_FIELD_GET(cap,
+ ENA_REGS_CAPS_ADMIN_CMD_TO_MASK,
+ ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT);
if (timeout)
/* the resolution of timeout reg is 100ms */
ena_dev->admin_queue.completion_timeout = timeout * 100000;
diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h
index 5d38b69c0f..fbb0ea39ec 100644
--- a/drivers/net/ena/base/ena_com.h
+++ b/drivers/net/ena/base/ena_com.h
@@ -1201,15 +1201,17 @@ static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
intr_reg->intr_control |=
- (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
- & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
+ ENA_FIELD_PREP(tx_delay_interval,
+ ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK,
+ ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT);
if (unmask)
intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
intr_reg->intr_control |=
- (((u32)no_moderation_update) << ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT) &
- ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK;
+ ENA_FIELD_PREP(((u32)no_moderation_update),
+ ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK,
+ ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT);
}
static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl)
diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c
index e26678827c..29cc331b1b 100644
--- a/drivers/net/ena/base/ena_eth_com.c
+++ b/drivers/net/ena/base/ena_eth_com.c
@@ -17,8 +17,9 @@ struct ena_eth_io_rx_cdesc_base *ena_com_get_next_rx_cdesc(struct ena_com_io_cq
cdesc = (struct ena_eth_io_rx_cdesc_base *)(io_cq->cdesc_addr.virt_addr
+ (head_masked * io_cq->cdesc_entry_size_in_bytes));
- desc_phase = (READ_ONCE32(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >>
- ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
+ desc_phase = ENA_FIELD_GET(READ_ONCE32(cdesc->status),
+ ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK,
+ ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT);
if (desc_phase != expected_phase)
return NULL;
@@ -302,8 +303,10 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
break;
status = READ_ONCE32(cdesc->status);
- if (unlikely((status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >>
- ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT && count != 0)) {
+ if (unlikely(ENA_FIELD_GET(status,
+ ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK,
+ ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) &&
+ count != 0)) {
ena_trc_err(dev,
"First bit is on in descriptor #%u on q_id: %u, req_id: %u\n",
count, io_cq->qid, cdesc->req_id);
@@ -321,8 +324,9 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
ena_com_cq_inc_head(io_cq);
count++;
- last = (status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >>
- ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;
+ last = ENA_FIELD_GET(status,
+ ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK,
+ ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT);
} while (!last);
if (last) {
@@ -361,32 +365,37 @@ static int ena_com_create_meta(struct ena_com_io_sq *io_sq,
meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
/* bits 0-9 of the mss */
- meta_desc->word2 |= ((u32)ena_meta->mss <<
- ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) &
- ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
+ meta_desc->word2 |=
+ ENA_FIELD_PREP((u32)ena_meta->mss,
+ ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK,
+ ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT);
/* bits 10-13 of the mss */
- meta_desc->len_ctrl |= ((ena_meta->mss >> 10) <<
- ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) &
- ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK;
+ meta_desc->len_ctrl |=
+ ENA_FIELD_PREP((ena_meta->mss >> 10),
+ ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK,
+ ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT);
/* Extended meta desc */
meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
- meta_desc->len_ctrl |= ((u32)io_sq->phase <<
- ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) &
- ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
+ meta_desc->len_ctrl |=
+ ENA_FIELD_PREP((u32)io_sq->phase,
+ ENA_ETH_IO_TX_META_DESC_PHASE_MASK,
+ ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT);
meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_FIRST_MASK;
meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
meta_desc->word2 |= ena_meta->l3_hdr_len &
ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
- meta_desc->word2 |= (ena_meta->l3_hdr_offset <<
- ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) &
- ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;
+ meta_desc->word2 |=
+ ENA_FIELD_PREP(ena_meta->l3_hdr_offset,
+ ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK,
+ ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT);
- meta_desc->word2 |= ((u32)ena_meta->l4_hdr_len <<
- ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) &
- ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;
+ meta_desc->word2 |=
+ ENA_FIELD_PREP((u32)ena_meta->l4_hdr_len,
+ ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK,
+ ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT);
return ena_com_sq_update_tail(io_sq);
}
@@ -424,21 +433,26 @@ static void ena_com_rx_set_flags(struct ena_com_io_cq *io_cq,
ena_rx_ctx->l3_proto = cdesc->status &
ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
ena_rx_ctx->l4_proto =
- (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >>
- ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;
+ ENA_FIELD_GET(cdesc->status,
+ ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK,
+ ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT);
ena_rx_ctx->l3_csum_err =
- !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >>
- ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT);
+ !!(ENA_FIELD_GET(cdesc->status,
+ ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK,
+ ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT));
ena_rx_ctx->l4_csum_err =
- !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >>
- ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT);
+ !!(ENA_FIELD_GET(cdesc->status,
+ ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK,
+ ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT));
ena_rx_ctx->l4_csum_checked =
- !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >>
- ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT);
+ !!(ENA_FIELD_GET(cdesc->status,
+ ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK,
+ ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT));
ena_rx_ctx->hash = cdesc->hash;
ena_rx_ctx->frag =
- (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >>
- ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
+ ENA_FIELD_GET(cdesc->status,
+ ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK,
+ ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT);
ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),
"l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %u frag %d cdesc_status %x\n",
@@ -523,46 +537,48 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
if (!have_meta)
desc->len_ctrl |= ENA_ETH_IO_TX_DESC_FIRST_MASK;
- desc->buff_addr_hi_hdr_sz |= ((u32)header_len <<
- ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) &
- ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;
- desc->len_ctrl |= ((u32)io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
- ENA_ETH_IO_TX_DESC_PHASE_MASK;
+ desc->buff_addr_hi_hdr_sz |= ENA_FIELD_PREP((u32)header_len,
+ ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK,
+ ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT);
+
+ desc->len_ctrl |= ENA_FIELD_PREP((u32)io_sq->phase,
+ ENA_ETH_IO_TX_DESC_PHASE_MASK,
+ ENA_ETH_IO_TX_DESC_PHASE_SHIFT);
desc->len_ctrl |= ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;
/* Bits 0-9 */
- desc->meta_ctrl |= ((u32)ena_tx_ctx->req_id <<
- ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) &
- ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
+ desc->meta_ctrl |= ENA_FIELD_PREP((u32)ena_tx_ctx->req_id,
+ ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK,
+ ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT);
- desc->meta_ctrl |= (ena_tx_ctx->df <<
- ENA_ETH_IO_TX_DESC_DF_SHIFT) &
- ENA_ETH_IO_TX_DESC_DF_MASK;
+ desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->df,
+ ENA_ETH_IO_TX_DESC_DF_MASK,
+ ENA_ETH_IO_TX_DESC_DF_SHIFT);
/* Bits 10-15 */
- desc->len_ctrl |= ((ena_tx_ctx->req_id >> 10) <<
- ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) &
- ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK;
+ desc->len_ctrl |= ENA_FIELD_PREP((ena_tx_ctx->req_id >> 10),
+ ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK,
+ ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT);
if (ena_tx_ctx->meta_valid) {
- desc->meta_ctrl |= (ena_tx_ctx->tso_enable <<
- ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) &
- ENA_ETH_IO_TX_DESC_TSO_EN_MASK;
+ desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->tso_enable,
+ ENA_ETH_IO_TX_DESC_TSO_EN_MASK,
+ ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT);
desc->meta_ctrl |= ena_tx_ctx->l3_proto &
ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
- desc->meta_ctrl |= (ena_tx_ctx->l4_proto <<
- ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) &
- ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK;
- desc->meta_ctrl |= (ena_tx_ctx->l3_csum_enable <<
- ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) &
- ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK;
- desc->meta_ctrl |= (ena_tx_ctx->l4_csum_enable <<
- ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) &
- ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK;
- desc->meta_ctrl |= (ena_tx_ctx->l4_csum_partial <<
- ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) &
- ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;
+ desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->l4_proto,
+ ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK,
+ ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT);
+ desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->l3_csum_enable,
+ ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK,
+ ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT);
+ desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->l4_csum_enable,
+ ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK,
+ ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT);
+ desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->l4_csum_partial,
+ ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK,
+ ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT);
}
for (i = 0; i < num_bufs; i++) {
@@ -581,9 +597,9 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc));
- desc->len_ctrl |= ((u32)io_sq->phase <<
- ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
- ENA_ETH_IO_TX_DESC_PHASE_MASK;
+ desc->len_ctrl |= ENA_FIELD_PREP((u32)io_sq->phase,
+ ENA_ETH_IO_TX_DESC_PHASE_MASK,
+ ENA_ETH_IO_TX_DESC_PHASE_SHIFT);
}
desc->len_ctrl |= ena_bufs->len &
@@ -702,7 +718,9 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK |
ENA_ETH_IO_RX_DESC_LAST_MASK |
ENA_ETH_IO_RX_DESC_COMP_REQ_MASK |
- (io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK);
+ ENA_FIELD_GET(io_sq->phase,
+ ENA_ETH_IO_RX_DESC_PHASE_MASK,
+ ENA_ZERO_SHIFT);
desc->req_id = req_id;
diff --git a/drivers/net/ena/base/ena_eth_com.h b/drivers/net/ena/base/ena_eth_com.h
index f91cf67c09..8a12ed5fba 100644
--- a/drivers/net/ena/base/ena_eth_com.h
+++ b/drivers/net/ena/base/ena_eth_com.h
@@ -188,7 +188,9 @@ static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq,
if (!io_cq->numa_node_cfg_reg)
return;
- numa_cfg.numa_cfg = (numa_node & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK)
+ numa_cfg.numa_cfg = (ENA_FIELD_GET(numa_node,
+ ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK,
+ ENA_ZERO_SHIFT))
| ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
ENA_REG_WRITE32(io_cq->bus, numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg);
@@ -230,7 +232,9 @@ static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq,
* expected, it mean that the device still didn't update
* this completion.
*/
- cdesc_phase = flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
+ cdesc_phase = ENA_FIELD_GET(flags,
+ ENA_ETH_IO_TX_CDESC_PHASE_MASK,
+ ENA_ZERO_SHIFT);
if (cdesc_phase != expected_phase)
return ENA_COM_TRY_AGAIN;
diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h
index 87f7083ce9..03f29a2f1d 100644
--- a/drivers/net/ena/base/ena_plat_dpdk.h
+++ b/drivers/net/ena/base/ena_plat_dpdk.h
@@ -325,6 +325,9 @@ void ena_rss_key_fill(void *key, size_t size);
#define ENA_BITS_PER_U64(bitmap) (ena_bits_per_u64(bitmap))
#define ENA_FIELD_GET(value, mask, offset) (((value) & (mask)) >> (offset))
+#define ENA_FIELD_PREP(value, mask, offset) (((value) << (offset)) & (mask))
+
+#define ENA_ZERO_SHIFT 0
static __rte_always_inline int ena_bits_per_u64(uint64_t bitmap)
{
--
2.17.1
next prev parent reply other threads:[~2024-07-02 14:47 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-02 14:46 [PATCH 00/15] net/ena: driver release 2.10.0 shaibran
2024-07-02 14:46 ` [PATCH 01/15] net/ena/base: add descriptor dump capability shaibran
2024-07-02 14:46 ` [PATCH 02/15] net/ena/base: remove unused param shaibran
2024-07-02 14:46 ` [PATCH 03/15] net/ena/base: remove redundant assert checks shaibran
2024-07-02 14:46 ` [PATCH 04/15] net/ena/base: update memory barrier comment shaibran
2024-07-02 14:46 ` [PATCH 05/15] net/ena/base: add method to check used entries shaibran
2024-07-02 14:46 ` [PATCH 06/15] net/ena/base: add an additional reset reason shaibran
2024-07-02 14:46 ` [PATCH 07/15] net/ena/base: update copyrights comments shaibran
2024-07-02 14:46 ` shaibran [this message]
2024-07-02 14:46 ` [PATCH 09/15] net/ena: logger change to improve performance shaibran
2024-07-02 14:46 ` [PATCH 10/15] net/ena: rework device uninit shaibran
2024-07-02 14:46 ` [PATCH 11/15] net/ena: fix bad checksum handling shaibran
2024-07-02 14:46 ` [PATCH 12/15] net/ena: fix invalid return value check shaibran
2024-07-02 14:46 ` [PATCH 13/15] net/ena: fix wrong handling of checksum shaibran
2024-07-02 14:46 ` [PATCH 14/15] net/ena: rework Rx checksum inspection shaibran
2024-07-02 14:46 ` [PATCH 15/15] net/ena: upgrade driver version to 2.10.0 shaibran
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