From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58B624554D; Tue, 2 Jul 2024 16:47:32 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0946E40E26; Tue, 2 Jul 2024 16:46:56 +0200 (CEST) Received: from smtp-fw-52004.amazon.com (smtp-fw-52004.amazon.com [52.119.213.154]) by mails.dpdk.org (Postfix) with ESMTP id 4C65240E0B for ; Tue, 2 Jul 2024 16:46:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1719931615; x=1751467615; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=oG5sTC/z2rmqG5JBHh2ld5B7uNwtOSxGx6/dhsWybuE=; b=KN7o6I2erHu1YJ8nctKOW1pe2a/+hfhRbtPcnOspViT0SxmDLkZwOBlm 2X7Vxe+ah79kP/RAYdP+HYuQJgoK3xSsmfbgrZ/0TYwGiqSSdJShmv6Qp 1UYbp1hWatZuQgi0Ij/jKLvBehV2SAQ1QjNSdBuXU6zufzDfqOXrhkpUX E=; X-IronPort-AV: E=Sophos;i="6.09,178,1716249600"; d="scan'208";a="215615465" Received: from iad12-co-svc-p1-lb1-vlan2.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.43.8.2]) by smtp-border-fw-52004.iad7.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 14:46:52 +0000 Received: from EX19MTAEUB001.ant.amazon.com [10.0.17.79:32361] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.35.104:2525] with esmtp (Farcaster) id ae6e5664-71f7-4fa6-b9ef-807c84cb5fd3; Tue, 2 Jul 2024 14:46:50 +0000 (UTC) X-Farcaster-Flow-ID: ae6e5664-71f7-4fa6-b9ef-807c84cb5fd3 Received: from EX19D007EUA004.ant.amazon.com (10.252.50.76) by EX19MTAEUB001.ant.amazon.com (10.252.51.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34; Tue, 2 Jul 2024 14:46:48 +0000 Received: from EX19MTAUWB001.ant.amazon.com (10.250.64.248) by EX19D007EUA004.ant.amazon.com (10.252.50.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.1258.34; Tue, 2 Jul 2024 14:46:48 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.173) by mail-relay.amazon.com (10.250.64.254) with Microsoft SMTP Server id 15.2.1258.34 via Frontend Transport; Tue, 2 Jul 2024 14:46:46 +0000 From: To: CC: , Shai Brandes Subject: [PATCH 08/15] net/ena/base: add macro for bitfield access Date: Tue, 2 Jul 2024 17:46:19 +0300 Message-ID: <20240702144626.14545-9-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240702144626.14545-1-shaibran@amazon.com> References: <20240702144626.14545-1-shaibran@amazon.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Add ENA_FIELD_GET and ENA_FIELD_PREP macro to make access to fields more readable. Signed-off-by: Shai Brandes --- drivers/net/ena/base/ena_com.c | 111 ++++++++++++-------- drivers/net/ena/base/ena_com.h | 10 +- drivers/net/ena/base/ena_eth_com.c | 146 +++++++++++++++------------ drivers/net/ena/base/ena_eth_com.h | 8 +- drivers/net/ena/base/ena_plat_dpdk.h | 3 + 5 files changed, 165 insertions(+), 113 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 5f46e692b3..e5f1a31c9e 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -162,10 +162,13 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); aenq_caps = 0; - aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; - aenq_caps |= (sizeof(struct ena_admin_aenq_entry) << - ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) & - ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK; + aenq_caps |= ENA_FIELD_PREP(ena_dev->aenq.q_depth, + ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK, + ENA_ZERO_SHIFT); + + aenq_caps |= ENA_FIELD_PREP(sizeof(struct ena_admin_aenq_entry), + ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK, + ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT); ENA_REG_WRITE32(ena_dev->bus, aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); if (unlikely(!aenq_handlers)) { @@ -856,8 +859,9 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) mmio_read->seq_num++; read_resp->req_id = mmio_read->seq_num + 0xDEAD; - mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) & - ENA_REGS_MMIO_REG_READ_REG_OFF_MASK; + mmio_read_reg = ENA_FIELD_PREP(offset, + ENA_REGS_MMIO_REG_READ_REG_OFF_MASK, + ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT); mmio_read_reg |= mmio_read->seq_num & ENA_REGS_MMIO_REG_READ_REQ_ID_MASK; @@ -927,9 +931,10 @@ static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, else direction = ENA_ADMIN_SQ_DIRECTION_RX; - destroy_cmd.sq.sq_identity |= (direction << - ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & - ENA_ADMIN_SQ_SQ_DIRECTION_MASK; + destroy_cmd.sq.sq_identity |= + ENA_FIELD_PREP(direction, + ENA_ADMIN_SQ_SQ_DIRECTION_MASK, + ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT); destroy_cmd.sq.sq_idx = io_sq->idx; destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ; @@ -1267,16 +1272,18 @@ static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, else direction = ENA_ADMIN_SQ_DIRECTION_RX; - create_cmd.sq_identity |= (direction << - ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & - ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; + create_cmd.sq_identity |= + ENA_FIELD_PREP(direction, + ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK, + ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT); create_cmd.sq_caps_2 |= io_sq->mem_queue_type & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; - create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC << - ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & - ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; + create_cmd.sq_caps_2 |= + ENA_FIELD_PREP(ENA_ADMIN_COMPLETION_POLICY_DESC, + ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK, + ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT); create_cmd.sq_caps_3 |= ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; @@ -1616,8 +1623,9 @@ int ena_com_get_dma_width(struct ena_com_dev *ena_dev) return ENA_COM_TIMER_EXPIRED; } - width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> - ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; + width = ENA_FIELD_GET(caps, + ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK, + ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT); ena_trc_dbg(ena_dev, "ENA dma width: %d\n", width); @@ -1651,18 +1659,26 @@ int ena_com_validate_version(struct ena_com_dev *ena_dev) } ena_trc_info(ena_dev, "ENA device version: %d.%d\n", - (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> - ENA_REGS_VERSION_MAJOR_VERSION_SHIFT, - ver & ENA_REGS_VERSION_MINOR_VERSION_MASK); + ENA_FIELD_GET(ver, + ENA_REGS_VERSION_MAJOR_VERSION_MASK, + ENA_REGS_VERSION_MAJOR_VERSION_SHIFT), + ENA_FIELD_GET(ver, + ENA_REGS_VERSION_MINOR_VERSION_MASK, + ENA_ZERO_SHIFT)); ena_trc_info(ena_dev, "ENA controller version: %d.%d.%d implementation version %d\n", - (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) - >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT, - (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) - >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT, - (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK), - (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >> - ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT); + ENA_FIELD_GET(ctrl_ver, + ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK, + ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT), + ENA_FIELD_GET(ctrl_ver, + ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK, + ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT), + ENA_FIELD_GET(ctrl_ver, + ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK, + ENA_ZERO_SHIFT), + ENA_FIELD_GET(ctrl_ver, + ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK, + ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT)); ctrl_ver_masked = (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) | @@ -2117,16 +2133,20 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev, ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); aq_caps = 0; - aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK; - aq_caps |= (sizeof(struct ena_admin_aq_entry) << - ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) & - ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK; + aq_caps |= ENA_FIELD_PREP(admin_queue->q_depth, + ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK, + ENA_ZERO_SHIFT); + aq_caps |= ENA_FIELD_PREP(sizeof(struct ena_admin_aq_entry), + ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK, + ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT); acq_caps = 0; - acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK; - acq_caps |= (sizeof(struct ena_admin_acq_entry) << - ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) & - ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK; + acq_caps |= ENA_FIELD_PREP(admin_queue->q_depth, + ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK, + ENA_ZERO_SHIFT); + acq_caps |= ENA_FIELD_PREP(sizeof(struct ena_admin_acq_entry), + ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK, + ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT); ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); @@ -2521,8 +2541,9 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, return ENA_COM_INVAL; } - timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> - ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; + timeout = ENA_FIELD_GET(cap, + ENA_REGS_CAPS_RESET_TIMEOUT_MASK, + ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT); if (timeout == 0) { ena_trc_err(ena_dev, "Invalid timeout value\n"); return ENA_COM_INVAL; @@ -2534,10 +2555,12 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, /* For backward compatibility, device will interpret * bits 24-27 as MSB, bits 28-31 as LSB */ - reset_reason_lsb = ENA_FIELD_GET(reset_reason, ENA_RESET_REASON_LSB_MASK, + reset_reason_lsb = ENA_FIELD_GET(reset_reason, + ENA_RESET_REASON_LSB_MASK, ENA_RESET_REASON_LSB_OFFSET); - reset_reason_msb = ENA_FIELD_GET(reset_reason, ENA_RESET_REASON_MSB_MASK, + reset_reason_msb = ENA_FIELD_GET(reset_reason, + ENA_RESET_REASON_MSB_MASK, ENA_RESET_REASON_MSB_OFFSET); reset_val |= reset_reason_lsb << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT; @@ -2549,8 +2572,9 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, * extended reset reason fallback to generic */ reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; - reset_val |= (ENA_REGS_RESET_GENERIC << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) & - ENA_REGS_DEV_CTL_RESET_REASON_MASK; + reset_val |= ENA_FIELD_PREP(ENA_REGS_RESET_GENERIC, + ENA_REGS_DEV_CTL_RESET_REASON_MASK, + ENA_REGS_DEV_CTL_RESET_REASON_SHIFT); } ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); @@ -2572,8 +2596,9 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, return rc; } - timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >> - ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT; + timeout = ENA_FIELD_GET(cap, + ENA_REGS_CAPS_ADMIN_CMD_TO_MASK, + ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT); if (timeout) /* the resolution of timeout reg is 100ms */ ena_dev->admin_queue.completion_timeout = timeout * 100000; diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index 5d38b69c0f..fbb0ea39ec 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -1201,15 +1201,17 @@ static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg, ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; intr_reg->intr_control |= - (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) - & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; + ENA_FIELD_PREP(tx_delay_interval, + ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK, + ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT); if (unmask) intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; intr_reg->intr_control |= - (((u32)no_moderation_update) << ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT) & - ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK; + ENA_FIELD_PREP(((u32)no_moderation_update), + ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK, + ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT); } static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl) diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index e26678827c..29cc331b1b 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -17,8 +17,9 @@ struct ena_eth_io_rx_cdesc_base *ena_com_get_next_rx_cdesc(struct ena_com_io_cq cdesc = (struct ena_eth_io_rx_cdesc_base *)(io_cq->cdesc_addr.virt_addr + (head_masked * io_cq->cdesc_entry_size_in_bytes)); - desc_phase = (READ_ONCE32(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> - ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT; + desc_phase = ENA_FIELD_GET(READ_ONCE32(cdesc->status), + ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK, + ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT); if (desc_phase != expected_phase) return NULL; @@ -302,8 +303,10 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, break; status = READ_ONCE32(cdesc->status); - if (unlikely((status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> - ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT && count != 0)) { + if (unlikely(ENA_FIELD_GET(status, + ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK, + ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) && + count != 0)) { ena_trc_err(dev, "First bit is on in descriptor #%u on q_id: %u, req_id: %u\n", count, io_cq->qid, cdesc->req_id); @@ -321,8 +324,9 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, ena_com_cq_inc_head(io_cq); count++; - last = (status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> - ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT; + last = ENA_FIELD_GET(status, + ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK, + ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT); } while (!last); if (last) { @@ -361,32 +365,37 @@ static int ena_com_create_meta(struct ena_com_io_sq *io_sq, meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK; /* bits 0-9 of the mss */ - meta_desc->word2 |= ((u32)ena_meta->mss << - ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) & - ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK; + meta_desc->word2 |= + ENA_FIELD_PREP((u32)ena_meta->mss, + ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK, + ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT); /* bits 10-13 of the mss */ - meta_desc->len_ctrl |= ((ena_meta->mss >> 10) << - ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) & - ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK; + meta_desc->len_ctrl |= + ENA_FIELD_PREP((ena_meta->mss >> 10), + ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK, + ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT); /* Extended meta desc */ meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK; - meta_desc->len_ctrl |= ((u32)io_sq->phase << - ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & - ENA_ETH_IO_TX_META_DESC_PHASE_MASK; + meta_desc->len_ctrl |= + ENA_FIELD_PREP((u32)io_sq->phase, + ENA_ETH_IO_TX_META_DESC_PHASE_MASK, + ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT); meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_FIRST_MASK; meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_STORE_MASK; meta_desc->word2 |= ena_meta->l3_hdr_len & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; - meta_desc->word2 |= (ena_meta->l3_hdr_offset << - ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) & - ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK; + meta_desc->word2 |= + ENA_FIELD_PREP(ena_meta->l3_hdr_offset, + ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK, + ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT); - meta_desc->word2 |= ((u32)ena_meta->l4_hdr_len << - ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & - ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK; + meta_desc->word2 |= + ENA_FIELD_PREP((u32)ena_meta->l4_hdr_len, + ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK, + ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT); return ena_com_sq_update_tail(io_sq); } @@ -424,21 +433,26 @@ static void ena_com_rx_set_flags(struct ena_com_io_cq *io_cq, ena_rx_ctx->l3_proto = cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; ena_rx_ctx->l4_proto = - (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> - ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT; + ENA_FIELD_GET(cdesc->status, + ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK, + ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT); ena_rx_ctx->l3_csum_err = - !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> - ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT); + !!(ENA_FIELD_GET(cdesc->status, + ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK, + ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT)); ena_rx_ctx->l4_csum_err = - !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> - ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT); + !!(ENA_FIELD_GET(cdesc->status, + ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK, + ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT)); ena_rx_ctx->l4_csum_checked = - !!((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >> - ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT); + !!(ENA_FIELD_GET(cdesc->status, + ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK, + ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT)); ena_rx_ctx->hash = cdesc->hash; ena_rx_ctx->frag = - (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> - ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT; + ENA_FIELD_GET(cdesc->status, + ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK, + ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT); ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %u frag %d cdesc_status %x\n", @@ -523,46 +537,48 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, if (!have_meta) desc->len_ctrl |= ENA_ETH_IO_TX_DESC_FIRST_MASK; - desc->buff_addr_hi_hdr_sz |= ((u32)header_len << - ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) & - ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK; - desc->len_ctrl |= ((u32)io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & - ENA_ETH_IO_TX_DESC_PHASE_MASK; + desc->buff_addr_hi_hdr_sz |= ENA_FIELD_PREP((u32)header_len, + ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK, + ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT); + + desc->len_ctrl |= ENA_FIELD_PREP((u32)io_sq->phase, + ENA_ETH_IO_TX_DESC_PHASE_MASK, + ENA_ETH_IO_TX_DESC_PHASE_SHIFT); desc->len_ctrl |= ENA_ETH_IO_TX_DESC_COMP_REQ_MASK; /* Bits 0-9 */ - desc->meta_ctrl |= ((u32)ena_tx_ctx->req_id << - ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) & - ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK; + desc->meta_ctrl |= ENA_FIELD_PREP((u32)ena_tx_ctx->req_id, + ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK, + ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT); - desc->meta_ctrl |= (ena_tx_ctx->df << - ENA_ETH_IO_TX_DESC_DF_SHIFT) & - ENA_ETH_IO_TX_DESC_DF_MASK; + desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->df, + ENA_ETH_IO_TX_DESC_DF_MASK, + ENA_ETH_IO_TX_DESC_DF_SHIFT); /* Bits 10-15 */ - desc->len_ctrl |= ((ena_tx_ctx->req_id >> 10) << - ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) & - ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK; + desc->len_ctrl |= ENA_FIELD_PREP((ena_tx_ctx->req_id >> 10), + ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK, + ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT); if (ena_tx_ctx->meta_valid) { - desc->meta_ctrl |= (ena_tx_ctx->tso_enable << - ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) & - ENA_ETH_IO_TX_DESC_TSO_EN_MASK; + desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->tso_enable, + ENA_ETH_IO_TX_DESC_TSO_EN_MASK, + ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT); desc->meta_ctrl |= ena_tx_ctx->l3_proto & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; - desc->meta_ctrl |= (ena_tx_ctx->l4_proto << - ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) & - ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK; - desc->meta_ctrl |= (ena_tx_ctx->l3_csum_enable << - ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) & - ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK; - desc->meta_ctrl |= (ena_tx_ctx->l4_csum_enable << - ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) & - ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK; - desc->meta_ctrl |= (ena_tx_ctx->l4_csum_partial << - ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) & - ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK; + desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->l4_proto, + ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK, + ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT); + desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->l3_csum_enable, + ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK, + ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT); + desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->l4_csum_enable, + ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK, + ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT); + desc->meta_ctrl |= ENA_FIELD_PREP(ena_tx_ctx->l4_csum_partial, + ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK, + ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT); } for (i = 0; i < num_bufs; i++) { @@ -581,9 +597,9 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc)); - desc->len_ctrl |= ((u32)io_sq->phase << - ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & - ENA_ETH_IO_TX_DESC_PHASE_MASK; + desc->len_ctrl |= ENA_FIELD_PREP((u32)io_sq->phase, + ENA_ETH_IO_TX_DESC_PHASE_MASK, + ENA_ETH_IO_TX_DESC_PHASE_SHIFT); } desc->len_ctrl |= ena_bufs->len & @@ -702,7 +718,9 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK | ENA_ETH_IO_RX_DESC_LAST_MASK | ENA_ETH_IO_RX_DESC_COMP_REQ_MASK | - (io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK); + ENA_FIELD_GET(io_sq->phase, + ENA_ETH_IO_RX_DESC_PHASE_MASK, + ENA_ZERO_SHIFT); desc->req_id = req_id; diff --git a/drivers/net/ena/base/ena_eth_com.h b/drivers/net/ena/base/ena_eth_com.h index f91cf67c09..8a12ed5fba 100644 --- a/drivers/net/ena/base/ena_eth_com.h +++ b/drivers/net/ena/base/ena_eth_com.h @@ -188,7 +188,9 @@ static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq, if (!io_cq->numa_node_cfg_reg) return; - numa_cfg.numa_cfg = (numa_node & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK) + numa_cfg.numa_cfg = (ENA_FIELD_GET(numa_node, + ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK, + ENA_ZERO_SHIFT)) | ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK; ENA_REG_WRITE32(io_cq->bus, numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg); @@ -230,7 +232,9 @@ static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, * expected, it mean that the device still didn't update * this completion. */ - cdesc_phase = flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK; + cdesc_phase = ENA_FIELD_GET(flags, + ENA_ETH_IO_TX_CDESC_PHASE_MASK, + ENA_ZERO_SHIFT); if (cdesc_phase != expected_phase) return ENA_COM_TRY_AGAIN; diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 87f7083ce9..03f29a2f1d 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -325,6 +325,9 @@ void ena_rss_key_fill(void *key, size_t size); #define ENA_BITS_PER_U64(bitmap) (ena_bits_per_u64(bitmap)) #define ENA_FIELD_GET(value, mask, offset) (((value) & (mask)) >> (offset)) +#define ENA_FIELD_PREP(value, mask, offset) (((value) << (offset)) & (mask)) + +#define ENA_ZERO_SHIFT 0 static __rte_always_inline int ena_bits_per_u64(uint64_t bitmap) { -- 2.17.1