From: Gregory Etelson <getelson@nvidia.com>
To: <dev@dpdk.org>
Cc: <getelson@nvidia.com>, <mkashani@nvidia.com>,
<rasland@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>,
Viacheslav Ovsiienko <viacheslavo@nvidia.com>,
Bing Zhao <bingz@nvidia.com>, Ori Kam <orika@nvidia.com>,
Suanming Mou <suanmingm@nvidia.com>,
Matan Azrad <matan@nvidia.com>
Subject: [PATCH] net/mlx5: fix IPv6-in-IPv6 tunnel recognition
Date: Sun, 7 Jul 2024 13:13:41 +0300 [thread overview]
Message-ID: <20240707101342.49823-1-getelson@nvidia.com> (raw)
The PMD did not recognize IPv6-in-IPv6 tunnel if IPv6 routing
extension was placed between IPv6 outer and inner headers.
The patch fixes IPv6-in-IPv6 tunnel recognition.
Fixes: 80c676259a04 ("net/mlx5: validate HWS template items")
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
drivers/net/mlx5/mlx5_flow_hw.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index ad8d73a089..7c9ba4e819 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -8228,7 +8228,8 @@ mlx5_hw_flow_tunnel_ip_check(uint64_t last_item, uint64_t *item_flags)
if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV4) {
tunnel = true;
*item_flags |= MLX5_FLOW_LAYER_IPIP;
- } else if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV6) {
+ } else if (last_item == MLX5_FLOW_LAYER_OUTER_L3_IPV6 ||
+ last_item == MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) {
tunnel = true;
*item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
} else {
--
2.43.0
next reply other threads:[~2024-07-07 10:14 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-07 10:13 Gregory Etelson [this message]
2024-07-18 7:24 ` Raslan Darawsheh
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