[PATCH 01/10] net/mlx5: add hairpin out of buffer counter

[PATCH 01/10] net/mlx5: add hairpin out of buffer counter

[Itamar Gozlan]

From: Shani Peretz <shperetz@nvidia.com>

Currently mlx5 PMD exposes rx_out_of_buffer counter that tracks
packets dropped when Rx queue was full.

To provide more granular statistics, this patch splits the
`rx_out_of_buffer` counter into two separate counters:
1. hairpin_out_of_buffer - This counter specifically tracks packets dropped
by the device's hairpin Rx queues.
2. rx_out_of_buffer - This counter tracks packets dropped by the device's
Rx queues, excluding the hairpin Rx queues.

Two hardware counter objects will be created per device,
and all the Rx queues will be assigned to these counters during the
configuration phase.

The `hairpin_out_of_buffer` counter will be created only if there is
at least one hairpin Rx queue present on the device.

Signed-off-by: Shani Peretz <shperetz@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 doc/guides/nics/mlx5.rst                |  3 ++
 doc/guides/rel_notes/release_24_07.rst  |  1 +
 drivers/net/mlx5/linux/mlx5_ethdev_os.c |  5 +++
 drivers/net/mlx5/linux/mlx5_os.c        | 14 ++++++-
 drivers/net/mlx5/mlx5.c                 |  4 ++
 drivers/net/mlx5/mlx5.h                 |  4 ++
 drivers/net/mlx5/mlx5_devx.c            | 54 ++++++++++++++++++++++++-
 drivers/net/mlx5/windows/mlx5_os.c      |  1 +
 8 files changed, 84 insertions(+), 2 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 304c6770af..caacc9f62d 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -750,6 +750,9 @@ Limitations
 
   - Hairpin between two ports could only manual binding and explicit Tx flow mode. For single port hairpin, all the combinations of auto/manual binding and explicit/implicit Tx flow mode could be supported.
   - Hairpin in switchdev SR-IOV mode is not supported till now.
+  - "out_of_buffer" statistics are not available on:
+     - NICs older than ConnectX-7.
+     - DPUs older than BlueField-3.
 
 - Quota:
 
diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst
index 700c29d8c6..29c77deb03 100644
--- a/doc/guides/rel_notes/release_24_07.rst
+++ b/doc/guides/rel_notes/release_24_07.rst
@@ -101,6 +101,7 @@ New Features
   * Added match with E-Switch manager.
   * Added flow item and actions validation to async flow API.
   * Added global out of buffer counter for hairpin queues.
+  * Added port out of buffer counter for hairpin queues.
 
 * **Updated TAP driver.**
 
diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c
index 7995ac6bbc..82f651f2f3 100644
--- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c
+++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c
@@ -1420,6 +1420,11 @@ static const struct mlx5_counter_ctrl mlx5_counters_init[] = {
 		.ctr_name = "out_of_buffer",
 		.dev = 1,
 	},
+	{
+		.dpdk_name = "hairpin_out_of_buffer",
+		.ctr_name = "hairpin_out_of_buffer",
+		.dev = 1,
+	},
 	{
 		.dpdk_name = "dev_internal_queue_oob",
 		.ctr_name = "dev_internal_queue_oob",
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 50f4810bff..5e950e9be1 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -964,6 +964,8 @@ mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev)
 		DRV_LOG(DEBUG, "Port %d queue counter object cannot be created "
 			"by DevX - fall-back to use the kernel driver global "
 			"queue counter.", dev->data->port_id);
+		priv->q_counters_allocation_failure = 1;
+
 		/* Create WQ by kernel and query its queue counter ID. */
 		if (cq) {
 			wq = mlx5_glue->create_wq(ctx,
@@ -3037,13 +3039,23 @@ mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
 		if (priv->q_counters != NULL &&
 		    strcmp(ctr_name, "out_of_buffer") == 0) {
 			if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
-				DRV_LOG(WARNING, "Devx out_of_buffer counter is not supported in the secondary process");
+				DRV_LOG(WARNING, "DevX out_of_buffer counter is not supported in the secondary process");
 				rte_errno = ENOTSUP;
 				return 1;
 			}
 			return mlx5_devx_cmd_queue_counter_query
 					(priv->q_counters, 0, (uint32_t *)stat);
 		}
+		if (priv->q_counters_hairpin != NULL &&
+		    strcmp(ctr_name, "hairpin_out_of_buffer") == 0) {
+			if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
+				DRV_LOG(WARNING, "DevX out_of_buffer counter is not supported in the secondary process");
+				rte_errno = ENOTSUP;
+				return 1;
+			}
+			return mlx5_devx_cmd_queue_counter_query
+					(priv->q_counters_hairpin, 0, (uint32_t *)stat);
+		}
 		MKSTR(path, "%s/ports/%d/hw_counters/%s",
 		      priv->sh->ibdev_path,
 		      priv->dev_port,
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index e482f7f0e5..8d266b0e64 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -2394,6 +2394,10 @@ mlx5_dev_close(struct rte_eth_dev *dev)
 		mlx5_devx_cmd_destroy(priv->q_counters);
 		priv->q_counters = NULL;
 	}
+	if (priv->q_counters_hairpin) {
+		mlx5_devx_cmd_destroy(priv->q_counters_hairpin);
+		priv->q_counters_hairpin = NULL;
+	}
 	mlx5_mprq_free_mp(dev);
 	mlx5_os_free_shared_dr(priv);
 #ifdef HAVE_MLX5_HWS_SUPPORT
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index bd149b43e5..75a1e170af 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1986,8 +1986,12 @@ struct mlx5_priv {
 	LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
 	rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */
 	uint32_t rss_shared_actions; /* RSS shared actions. */
+	/* If true, indicates that we failed to allocate a q counter in the past. */
+	bool q_counters_allocation_failure;
 	struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */
 	uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */
+	/* DevX queue counter object for all hairpin queues of the port. */
+	struct mlx5_devx_obj *q_counters_hairpin;
 	uint32_t lag_affinity_idx; /* LAG mode queue 0 affinity starting. */
 	rte_spinlock_t flex_item_sl; /* Flex item list spinlock. */
 	struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM];
diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c
index f23eb1def6..7db271acb4 100644
--- a/drivers/net/mlx5/mlx5_devx.c
+++ b/drivers/net/mlx5/mlx5_devx.c
@@ -496,6 +496,56 @@ mlx5_rxq_create_devx_cq_resources(struct mlx5_rxq_priv *rxq)
 	return 0;
 }
 
+/**
+ * Create a global queue counter for all the port hairpin queues.
+ *
+ * @param priv
+ *   Device private data.
+ *
+ * @return
+ *   The counter_set_id of the queue counter object, 0 otherwise.
+ */
+static uint32_t
+mlx5_set_hairpin_queue_counter_obj(struct mlx5_priv *priv)
+{
+	if (priv->q_counters_hairpin != NULL)
+		return priv->q_counters_hairpin->id;
+
+	/* Queue counter allocation failed in the past - don't try again. */
+	if (priv->q_counters_allocation_failure != 0)
+		return 0;
+
+	if (priv->pci_dev == NULL) {
+		DRV_LOG(DEBUG, "Hairpin out of buffer counter is "
+				"only supported on PCI device.");
+		priv->q_counters_allocation_failure = 1;
+		return 0;
+	}
+
+	switch (priv->pci_dev->id.device_id) {
+	/* Counting out of buffer drops on hairpin queues is supported only on CX7 and up. */
+	case PCI_DEVICE_ID_MELLANOX_CONNECTX7:
+	case PCI_DEVICE_ID_MELLANOX_CONNECTXVF:
+	case PCI_DEVICE_ID_MELLANOX_BLUEFIELD3:
+	case PCI_DEVICE_ID_MELLANOX_BLUEFIELDVF:
+
+		priv->q_counters_hairpin = mlx5_devx_cmd_queue_counter_alloc(priv->sh->cdev->ctx);
+		if (priv->q_counters_hairpin == NULL) {
+			/* Failed to allocate */
+			DRV_LOG(DEBUG, "Some of the statistics of port %d "
+				"will not be available.", priv->dev_data->port_id);
+			priv->q_counters_allocation_failure = 1;
+			return 0;
+		}
+		return priv->q_counters_hairpin->id;
+	default:
+		DRV_LOG(DEBUG, "Hairpin out of buffer counter "
+				"is not available on this NIC.");
+		priv->q_counters_allocation_failure = 1;
+		return 0;
+	}
+}
+
 /**
  * Create the Rx hairpin queue object.
  *
@@ -541,7 +591,9 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq)
 	unlocked_attr.wq_attr.log_hairpin_num_packets =
 			unlocked_attr.wq_attr.log_hairpin_data_sz -
 			MLX5_HAIRPIN_QUEUE_STRIDE;
-	unlocked_attr.counter_set_id = priv->counter_set_id;
+
+	unlocked_attr.counter_set_id = mlx5_set_hairpin_queue_counter_obj(priv);
+
 	rxq_ctrl->rxq.delay_drop = priv->config.hp_delay_drop;
 	unlocked_attr.delay_drop_en = priv->config.hp_delay_drop;
 	unlocked_attr.hairpin_data_buffer_type =
diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index 98022ed3c7..0ebd233595 100644
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -83,6 +83,7 @@ mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev)
 		DRV_LOG(ERR, "Port %d queue counter object cannot be created "
 			"by DevX - imissed counter will be unavailable",
 			dev->data->port_id);
+		priv->q_counters_allocation_failure = 1;
 		return;
 	}
 	priv->counter_set_id = priv->q_counters->id;
-- 
2.39.3

[PATCH 02/10] net/mlx5: fix matcher object memory leak

[Itamar Gozlan]

From: Mahmoud Maatuq <mahmoudmatook.mm@gmail.com>

This makes sure that the allocated matcher object is freed
for all branches that return NULL.

Coverity issue: 426424
Fixes: 27d171b88031 ("net/mlx5: abstract flow action and enable reconfigure")

Signed-off-by: Mahmoud Maatuq <mahmoudmatook.mm@gmail.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index d46beffd4c..8a0d58cb05 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -12010,9 +12010,12 @@ flow_matcher_create_cb(void *tool_ctx, void *cb_ctx)
 		items = *((const struct rte_flow_item **)(ctx->data2));
 		resource->matcher_object = mlx5dr_bwc_matcher_create
 				(resource->group->tbl, resource->priority, items);
-		if (!(resource->matcher_object))
+		if (!resource->matcher_object) {
+			mlx5_free(resource);
 			return NULL;
+		}
 #else
+		mlx5_free(resource);
 		return NULL;
 #endif
 	}
-- 
2.39.3

[PATCH 03/10] net/mlx5/hws: set eswitch owner vhc ID valid accordingly

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

eswitch_owner_vhca_id_valid value should be set to 1 only on
merged-eswitch device.

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_action.c | 12 ++++++++++++
 drivers/net/mlx5/hws/mlx5dr_cmd.c    |  3 ++-
 drivers/net/mlx5/hws/mlx5dr_cmd.h    |  1 +
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c
index 90f2f17bd0..03c3683f71 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -680,6 +680,8 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx,
 			fixup_stc_attr->stc_offset = stc_attr->stc_offset;
 			fixup_stc_attr->vport.esw_owner_vhca_id = ctx->caps->vhca_id;
 			fixup_stc_attr->vport.vport_num = ctx->caps->eswitch_manager_vport_number;
+			fixup_stc_attr->vport.eswitch_owner_vhca_id_valid =
+				ctx->caps->merged_eswitch;
 			use_fixup = true;
 		}
 		break;
@@ -700,6 +702,8 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx,
 			fixup_stc_attr->stc_offset = stc_attr->stc_offset;
 			fixup_stc_attr->vport.vport_num = 0;
 			fixup_stc_attr->vport.esw_owner_vhca_id = stc_attr->vport.esw_owner_vhca_id;
+			fixup_stc_attr->vport.eswitch_owner_vhca_id_valid =
+				ctx->caps->merged_eswitch;
 		}
 		use_fixup = true;
 		break;
@@ -1429,6 +1433,14 @@ static int mlx5dr_action_create_dest_vport_hws(struct mlx5dr_context *ctx,
 	action->vport.vport_num = vport_caps.vport_num;
 	action->vport.esw_owner_vhca_id = vport_caps.esw_owner_vhca_id;
 
+	if (!ctx->caps->merged_eswitch &&
+	    action->vport.esw_owner_vhca_id != ctx->caps->vhca_id) {
+		DR_LOG(ERR, "Not merged-eswitch (%d), not allowed to send to other vhca_id (%d)",
+		       ctx->caps->vhca_id, action->vport.esw_owner_vhca_id);
+		rte_errno = ENOTSUP;
+		return rte_errno;
+	}
+
 	ret = mlx5dr_action_create_stcs(action, NULL);
 	if (ret) {
 		DR_LOG(ERR, "Failed creating stc for port %d", ib_port_num);
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index 666d678b42..72fc9e3d91 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -515,7 +515,8 @@ mlx5dr_cmd_stc_modify_set_stc_param(struct mlx5dr_cmd_stc_modify_attr *stc_attr,
 			 stc_attr->vport.vport_num);
 		MLX5_SET(stc_ste_param_vport, stc_param, eswitch_owner_vhca_id,
 			 stc_attr->vport.esw_owner_vhca_id);
-		MLX5_SET(stc_ste_param_vport, stc_param, eswitch_owner_vhca_id_valid, 1);
+		MLX5_SET(stc_ste_param_vport, stc_param, eswitch_owner_vhca_id_valid,
+			 stc_attr->vport.eswitch_owner_vhca_id_valid);
 		break;
 	case MLX5_IFC_STC_ACTION_TYPE_DROP:
 	case MLX5_IFC_STC_ACTION_TYPE_NOP:
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index ea5d346d8e..54840ec445 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -133,6 +133,7 @@ struct mlx5dr_cmd_stc_modify_attr {
 		struct {
 			uint16_t vport_num;
 			uint16_t esw_owner_vhca_id;
+			uint8_t eswitch_owner_vhca_id_valid;
 		} vport;
 		struct {
 			struct mlx5dr_pool_chunk ste;
-- 
2.39.3

[PATCH 04/10] net/mlx5/hws: fix memory leak in modify header free

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

When creating action from type MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2
we use modify-header object, we support few of that type at the same
time over this action depends on the number of headers.
Now when destroying the modify-header object we run over the
number_of_patterns, this variable was not set in the creation of that
action.

Fixes: 3a6c50215c07 ("net/mlx5/hws: support multi-pattern")
Cc: valex@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_action.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c
index 03c3683f71..b90f18df8a 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -1820,6 +1820,7 @@ mlx5dr_action_handle_tunnel_l3_to_l2(struct mlx5dr_action *action,
 
 		action[i].modify_header.max_num_of_actions = num_of_actions;
 		action[i].modify_header.num_of_actions = num_of_actions;
+		action[i].modify_header.num_of_patterns = num_of_hdrs;
 		action[i].modify_header.arg_obj = arg_obj;
 		action[i].modify_header.pat_obj = pat_obj;
 		action[i].modify_header.require_reparse =
-- 
2.39.3

[PATCH 05/10] net/mlx5/hws: strictly range templates check fix

[Itamar Gozlan]

Using range and non range templates is not allowed, and in HWS there is a
check that enforce that limitation with constantly check that, in a loop,
if the current template defined as range, the last one
should also be defined as range.
But, in the case where there are two templates in the following order:
(1) template with range, and (2) template without range.
The existing checks will not cover this case.
This commit fixes that hole by maintain the invariant that if a template
without a range exist, all the previous match template are also.

Fixes: 9732ffe13bd6 ("net/mlx5/hws: add range definer creation")
Cc: valex@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Itamar Gozlan <igozlan@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 9ebda9267d..51a3f7be4b 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -4041,15 +4041,18 @@ mlx5dr_definer_matcher_range_init(struct mlx5dr_context *ctx,
 
 	/* Create optional range definers */
 	for (i = 0; i < matcher->num_of_mt; i++) {
-		if (!mt[i].fcr_sz)
-			continue;
-
 		/* All must use range if requested */
-		if (i && !mt[i - 1].range_definer) {
+		bool is_range = !!mt[i].fcr_sz;
+		bool has_range = matcher->flags & MLX5DR_MATCHER_FLAGS_RANGE_DEFINER;
+
+		if (i && ((is_range && !has_range) || (!is_range && has_range))) {
 			DR_LOG(ERR, "Using range and non range templates is not allowed");
 			goto free_definers;
 		}
 
+		if (!mt[i].fcr_sz)
+			continue;
+
 		matcher->flags |= MLX5DR_MATCHER_FLAGS_RANGE_DEFINER;
 		/* Create definer without fcr binding, already binded */
 		mt[i].range_definer = mlx5dr_definer_alloc(ctx,
-- 
2.39.3

[PATCH 06/10] net/mlx5/hws: fix deletion of action vport

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

No more ignoring this action while destroying it.

Fixes: f8c8a6d8440d ("net/mlx5/hws: add action object")
Cc: erezsh@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_action.c | 4 ++++
 drivers/net/mlx5/hws/mlx5dr_cmd.c    | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c
index b90f18df8a..0d90280a7d 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -2968,6 +2968,7 @@ static void mlx5dr_action_destroy_hws(struct mlx5dr_action *action)
 	case MLX5DR_ACTION_TYP_ASO_CT:
 	case MLX5DR_ACTION_TYP_PUSH_VLAN:
 	case MLX5DR_ACTION_TYP_REMOVE_HEADER:
+	case MLX5DR_ACTION_TYP_VPORT:
 		mlx5dr_action_destroy_stcs(action);
 		break;
 	case MLX5DR_ACTION_TYP_DEST_ROOT:
@@ -3027,6 +3028,9 @@ static void mlx5dr_action_destroy_hws(struct mlx5dr_action *action)
 		break;
 	case MLX5DR_ACTION_TYP_LAST:
 		break;
+	default:
+		DR_LOG(ERR, "Not supported action type: %d", action->type);
+		assert(false);
 	}
 }
 
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index 72fc9e3d91..a4f778a8a4 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -1033,7 +1033,8 @@ int mlx5dr_cmd_generate_wqe(struct ibv_context *ctx,
 
 	ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 	if (ret) {
-		DR_LOG(ERR, "Failed to write GTA WQE using FW");
+		DR_LOG(ERR, "Failed to write GTA WQE using FW (syndrome: %#x)",
+		       mlx5dr_cmd_get_syndrome(out));
 		rte_errno = errno;
 		return rte_errno;
 	}
-- 
2.39.3

[PATCH 07/10] net/mlx5/hws: fix incorrect port ID on root item convert

[Itamar Gozlan]

From: Alex Vesker <valex@nvidia.com>

When calling item convert function we need to pass the port_id
in the attributes. This value should be passed not only for cases
that match on PORT related items, to resolve we will always pass it.

Fixes: 572fe9ef2f46 ("net/mlx5/hws: fix port ID for root table")
Cc: erezsh@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Alex Vesker <valex@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_matcher.c | 20 +++++---------------
 drivers/net/mlx5/hws/mlx5dr_rule.c    | 22 ++++++----------------
 2 files changed, 11 insertions(+), 31 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c
index 6a939eb031..dfa2cd435c 100644
--- a/drivers/net/mlx5/hws/mlx5dr_matcher.c
+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c
@@ -1231,7 +1231,6 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher)
 	struct mlx5dv_flow_match_parameters *mask;
 	struct mlx5_flow_attr flow_attr = {0};
 	struct rte_flow_error rte_error;
-	struct rte_flow_item *item;
 	uint8_t match_criteria;
 	int ret;
 
@@ -1260,20 +1259,11 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher)
 		return rte_errno;
 	}
 
-	/* We need the port id in case of matching representor */
-	item = matcher->mt[0].items;
-	while (item->type != RTE_FLOW_ITEM_TYPE_END) {
-		if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR ||
-		    item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) {
-			ret = flow_hw_get_port_id_from_ctx(ctx, &flow_attr.port_id);
-			if (ret) {
-				DR_LOG(ERR, "Failed to get port id for dev %s",
-				       ctx->ibv_ctx->device->name);
-				rte_errno = EINVAL;
-				return rte_errno;
-			}
-		}
-		++item;
+	ret = flow_hw_get_port_id_from_ctx(ctx, &flow_attr.port_id);
+	if (ret) {
+		DR_LOG(ERR, "Failed to get port id for dev %s", ctx->ibv_ctx->device->name);
+		rte_errno = EINVAL;
+		return rte_errno;
 	}
 
 	mask = simple_calloc(1, MLX5_ST_SZ_BYTES(fte_match_param) +
diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c
index 06d8e66f63..1edb7eac74 100644
--- a/drivers/net/mlx5/hws/mlx5dr_rule.c
+++ b/drivers/net/mlx5/hws/mlx5dr_rule.c
@@ -694,29 +694,19 @@ int mlx5dr_rule_create_root_no_comp(struct mlx5dr_rule *rule,
 				    struct mlx5dr_rule_action rule_actions[])
 {
 	struct mlx5dv_flow_matcher *dv_matcher = rule->matcher->dv_matcher;
+	struct mlx5dr_context *ctx = rule->matcher->tbl->ctx;
 	struct mlx5dv_flow_match_parameters *value;
 	struct mlx5_flow_attr flow_attr = {0};
 	struct mlx5dv_flow_action_attr *attr;
-	const struct rte_flow_item *cur_item;
 	struct rte_flow_error error;
 	uint8_t match_criteria;
 	int ret;
 
-	/* We need the port id in case of matching representor */
-	cur_item = items;
-	while (cur_item->type != RTE_FLOW_ITEM_TYPE_END) {
-		if (cur_item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR ||
-		    cur_item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) {
-			ret = flow_hw_get_port_id_from_ctx(rule->matcher->tbl->ctx,
-							   &flow_attr.port_id);
-			if (ret) {
-				DR_LOG(ERR, "Failed to get port id for dev %s",
-				       rule->matcher->tbl->ctx->ibv_ctx->device->name);
-				rte_errno = EINVAL;
-				return rte_errno;
-			}
-		}
-		++cur_item;
+	ret = flow_hw_get_port_id_from_ctx(ctx, &flow_attr.port_id);
+	if (ret) {
+		DR_LOG(ERR, "Failed to get port id for dev %s", ctx->ibv_ctx->device->name);
+		rte_errno = EINVAL;
+		return rte_errno;
 	}
 
 	attr = simple_calloc(num_actions, sizeof(*attr));
-- 
2.39.3

[PATCH 08/10] net/mlx5/hws: take out not needed variable

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

Removing a redundant variable.
Was there from day 1, not in use.

Fixes: f8c8a6d8440d ("net/mlx5/hws: add action object")
Cc: erezsh@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_pat_arg.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_pat_arg.h b/drivers/net/mlx5/hws/mlx5dr_pat_arg.h
index bbe313102f..c4e0cbc843 100644
--- a/drivers/net/mlx5/hws/mlx5dr_pat_arg.h
+++ b/drivers/net/mlx5/hws/mlx5dr_pat_arg.h
@@ -30,7 +30,6 @@ struct mlx5dr_pattern_cache {
 struct mlx5dr_pattern_cache_item {
 	struct {
 		struct mlx5dr_devx_obj *pattern_obj;
-		struct dr_icm_chunk *chunk;
 		uint8_t *data;
 		uint16_t num_of_actions;
 	} mh_data;
-- 
2.39.3

[PATCH 09/10] net/mlx5/hws: fix NAT64 csum issue

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

Due to HW limitation we got two csum's that were not correct, udp and
ip, both of them were not calculated correctly by the HW.
By adding the next W/A we allow the HW to collect it well:
Separate the protocol field and zero all the addresses before fixed the
UDP csum.
We saw that the IP csum by the HW didn't take the ipv4 version as part
of the csum because the way it was inserted into the packet, in order to
solve that we added a prefix that takes into account the real csum for
the ip version and from that point the HW calculating the csum correctly.

Fixes: 06d969a8c5b8 ("net/mlx5/hws: support NAT64 flow action")
Cc: erezsh@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_action.c | 136 ++++++++++++++++++++++-----
 drivers/net/mlx5/hws/mlx5dr_action.h |  15 ++-
 2 files changed, 123 insertions(+), 28 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c
index 0d90280a7d..8d3d0033e5 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -249,6 +249,62 @@ static void mlx5dr_action_put_shared_stc(struct mlx5dr_action *action,
 		mlx5dr_action_put_shared_stc_nic(ctx, stc_type, MLX5DR_TABLE_TYPE_FDB);
 }
 
+static void
+mlx5dr_action_create_nat64_zero_all_addr(uint8_t **action_ptr, bool is_v4_to_v6)
+{
+	if (is_v4_to_v6) {
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV4);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV4);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+	} else {
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_127_96);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_95_64);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_63_32);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_31_0);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_127_96);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_95_64);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_63_32);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_31_0);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+	}
+}
+
 static struct mlx5dr_action *
 mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx,
 				      struct mlx5dr_action_nat64_attr *attr,
@@ -329,17 +385,7 @@ mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx,
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
 	/* set sip and dip to 0, in order to have new csum */
-	if (is_v4_to_v6) {
-		MLX5_SET(set_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
-		MLX5_SET(set_action_in, action_ptr, field, MLX5_MODI_OUT_SIPV4);
-		MLX5_SET(set_action_in, action_ptr, data, 0);
-		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
-
-		MLX5_SET(set_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
-		MLX5_SET(set_action_in, action_ptr, field, MLX5_MODI_OUT_DIPV4);
-		MLX5_SET(set_action_in, action_ptr, data, 0);
-		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
-	}
+	mlx5dr_action_create_nat64_zero_all_addr(&action_ptr, is_v4_to_v6);
 
 	pat[0].data = modify_action_data;
 	pat[0].sz = (action_ptr - (uint8_t *)modify_action_data);
@@ -383,9 +429,14 @@ mlx5dr_action_create_nat64_repalce_state(struct mlx5dr_context *ctx,
 		memcpy(address_prefix, nat64_well_known_pref,
 		       MLX5DR_ACTION_NAT64_HEADER_MINUS_ONE * sizeof(uint32_t));
 	} else {
+		/* In order to fix HW csum issue, make the prefix ready */
+		uint32_t ipv4_pref[] = {0x0, 0xffba0000, 0x0, 0x0, 0x0};
+
 		header_size_in_dw = MLX5DR_ACTION_NAT64_IPV4_HEADER;
 		ip_ver = MLX5DR_ACTION_NAT64_IPV4_VER;
 		eth_type = RTE_ETHER_TYPE_IPV4;
+		memcpy(address_prefix, ipv4_pref,
+		       MLX5DR_ACTION_NAT64_IPV4_HEADER * sizeof(uint32_t));
 	}
 
 	memset(modify_action_data, 0, sizeof(modify_action_data));
@@ -441,6 +492,46 @@ mlx5dr_action_create_nat64_repalce_state(struct mlx5dr_context *ctx,
 	return action;
 }
 
+static struct mlx5dr_action *
+mlx5dr_action_create_nat64_copy_proto_state(struct mlx5dr_context *ctx,
+					    struct mlx5dr_action_nat64_attr *attr,
+					    uint32_t flags)
+{
+	__be64 modify_action_data[MLX5DR_ACTION_NAT64_MAX_MODIFY_ACTIONS];
+	struct mlx5dr_action_mh_pattern pat[2];
+	struct mlx5dr_action *action;
+	uint8_t *action_ptr;
+
+	memset(modify_action_data, 0, sizeof(modify_action_data));
+	action_ptr = (uint8_t *)modify_action_data;
+
+	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
+	MLX5_SET(copy_action_in, action_ptr, src_field,
+		 attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
+	MLX5_SET(copy_action_in, action_ptr, dst_field,
+		 MLX5_MODI_OUT_IP_PROTOCOL);
+	MLX5_SET(copy_action_in, action_ptr, src_offset, 16);
+	MLX5_SET(copy_action_in, action_ptr, dst_offset, 0);
+	MLX5_SET(copy_action_in, action_ptr, length, 8);
+	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
+	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+	pat[0].data = modify_action_data;
+	pat[0].sz = action_ptr - (uint8_t *)modify_action_data;
+
+	action = mlx5dr_action_create_modify_header_reparse(ctx, 1, pat, 0, flags,
+							    MLX5DR_ACTION_STC_REPARSE_ON);
+	if (!action) {
+		DR_LOG(ERR, "Failed to create action: action_sz: %zu, flags: 0x%x\n",
+		       pat[0].sz, flags);
+		return NULL;
+	}
+
+	return action;
+}
+
 static struct mlx5dr_action *
 mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 					   struct mlx5dr_action_nat64_attr *attr,
@@ -490,16 +581,6 @@ mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
-	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
-	MLX5_SET(copy_action_in, action_ptr, src_field,
-		 attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
-	MLX5_SET(copy_action_in, action_ptr, dst_field,
-		 MLX5_MODI_OUT_IP_PROTOCOL);
-	MLX5_SET(copy_action_in, action_ptr, src_offset, 16);
-	MLX5_SET(copy_action_in, action_ptr, dst_offset, 0);
-	MLX5_SET(copy_action_in, action_ptr, length, 8);
-	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
-
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
@@ -2051,7 +2132,7 @@ mlx5dr_action_create_modify_header_hws(struct mlx5dr_action *action,
 	return rte_errno;
 }
 
-static struct mlx5dr_action *
+struct mlx5dr_action *
 mlx5dr_action_create_modify_header_reparse(struct mlx5dr_context *ctx,
 					   uint8_t num_of_patterns,
 					   struct mlx5dr_action_mh_pattern *patterns,
@@ -2927,17 +3008,24 @@ mlx5dr_action_create_nat64(struct mlx5dr_context *ctx,
 		DR_LOG(ERR, "Nat64 failed creating replace state");
 		goto free_copy;
 	}
+	action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL] =
+		mlx5dr_action_create_nat64_copy_proto_state(ctx, attr, flags);
+	if (!action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL]) {
+		DR_LOG(ERR, "Nat64 failed creating copy protocol state");
+		goto free_replace;
+	}
 
 	action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPYBACK] =
 		mlx5dr_action_create_nat64_copy_back_state(ctx, attr, flags);
 	if (!action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPYBACK]) {
 		DR_LOG(ERR, "Nat64 failed creating copyback state");
-		goto free_replace;
+		goto free_copy_proto;
 	}
 
 	return action;
 
-
+free_copy_proto:
+	mlx5dr_action_destroy(action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL]);
 free_replace:
 	mlx5dr_action_destroy(action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_REPLACE]);
 free_copy:
diff --git a/drivers/net/mlx5/hws/mlx5dr_action.h b/drivers/net/mlx5/hws/mlx5dr_action.h
index 57e059a572..faea6bb1f4 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.h
+++ b/drivers/net/mlx5/hws/mlx5dr_action.h
@@ -11,9 +11,6 @@
 /* Max number of internal subactions of ipv6_ext */
 #define MLX5DR_ACTION_IPV6_EXT_MAX_SA 4
 
-/* Number of MH in NAT64 */
-#define MLX5DR_ACTION_NAT64_STAGES 3
-
 enum mlx5dr_action_stc_idx {
 	MLX5DR_ACTION_STC_IDX_CTRL = 0,
 	MLX5DR_ACTION_STC_IDX_HIT = 1,
@@ -88,7 +85,10 @@ enum {
 enum mlx5dr_action_nat64_stages {
 	MLX5DR_ACTION_NAT64_STAGE_COPY = 0,
 	MLX5DR_ACTION_NAT64_STAGE_REPLACE = 1,
-	MLX5DR_ACTION_NAT64_STAGE_COPYBACK = 2,
+	MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL = 2,
+	MLX5DR_ACTION_NAT64_STAGE_COPYBACK = 3,
+	/* Number of MH in NAT64 */
+	MLX5DR_ACTION_NAT64_STAGES = 4,
 };
 
 /* Registers for keeping data from stage to stage */
@@ -256,6 +256,13 @@ int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx,
 void mlx5dr_action_free_single_stc(struct mlx5dr_context *ctx,
 				   uint32_t table_type,
 				   struct mlx5dr_pool_chunk *stc);
+struct mlx5dr_action *
+mlx5dr_action_create_modify_header_reparse(struct mlx5dr_context *ctx,
+					   uint8_t num_of_patterns,
+					   struct mlx5dr_action_mh_pattern *patterns,
+					   uint32_t log_bulk_size,
+					   uint32_t flags, uint32_t reparse);
+
 
 static inline void
 mlx5dr_action_setter_default_single(struct mlx5dr_actions_apply_data *apply,
-- 
2.39.3

[PATCH 10/10] net/mlx5/hws: fix NA64 copy TOS field instead of TTL

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

We don't have enough registers to copy TTL and TOS, so we will set TTL
to be the default value (64) and will copy TOS.

Fixes: 06d969a8c5b8 ("net/mlx5/hws: support NAT64 flow action")
Cc: erezsh@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_action.c | 66 +++++++++++++++++++++++-----
 drivers/net/mlx5/hws/mlx5dr_action.h |  2 +
 2 files changed, 56 insertions(+), 12 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c
index 8d3d0033e5..8f6be37818 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -315,21 +315,27 @@ mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx,
 	struct mlx5dr_action *action;
 	uint32_t packet_len_field;
 	uint8_t *action_ptr;
-	uint32_t ttl_field;
+	uint32_t tos_field;
+	uint32_t tos_size;
 	uint32_t src_addr;
 	uint32_t dst_addr;
 	bool is_v4_to_v6;
+	uint32_t ecn;
 
 	is_v4_to_v6 = attr->flags & MLX5DR_ACTION_NAT64_V4_TO_V6;
 
 	if (is_v4_to_v6) {
 		packet_len_field = MLX5_MODI_OUT_IPV4_TOTAL_LEN;
-		ttl_field = MLX5_MODI_OUT_IPV4_TTL;
+		tos_field = MLX5_MODI_OUT_IP_DSCP;
+		tos_size = 6;
+		ecn = MLX5_MODI_OUT_IP_ECN;
 		src_addr = MLX5_MODI_OUT_SIPV4;
 		dst_addr = MLX5_MODI_OUT_DIPV4;
 	} else {
 		packet_len_field = MLX5_MODI_OUT_IPV6_PAYLOAD_LEN;
-		ttl_field = MLX5_MODI_OUT_IPV6_HOPLIMIT;
+		tos_field = MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS;
+		tos_size = 8;
+		ecn = 0;
 		src_addr = MLX5_MODI_OUT_SIPV6_31_0;
 		dst_addr = MLX5_MODI_OUT_DIPV6_31_0;
 	}
@@ -352,7 +358,7 @@ mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx,
 	}
 
 	/* | 8 bit - 8 bit     - 16 bit     |
-	 * | ttl   - protocol  - packet-len |
+	 * | TOS   - protocol  - packet-len |
 	 */
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
 	MLX5_SET(copy_action_in, action_ptr, src_field, packet_len_field);
@@ -377,12 +383,25 @@ mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx,
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
-	MLX5_SET(copy_action_in, action_ptr, src_field, ttl_field);
+	MLX5_SET(copy_action_in, action_ptr, src_field, tos_field);
 	MLX5_SET(copy_action_in, action_ptr, dst_field,
 		 attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
 	MLX5_SET(copy_action_in, action_ptr, dst_offset, 24);
-	MLX5_SET(copy_action_in, action_ptr, length, 8);
+	MLX5_SET(copy_action_in, action_ptr, length, tos_size);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+	/* in ipv4 TOS = {dscp (6bits) - ecn (2bits) }*/
+	if (ecn) {
+		MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
+		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
+		MLX5_SET(copy_action_in, action_ptr, src_field, ecn);
+		MLX5_SET(copy_action_in, action_ptr, dst_field,
+			attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
+		MLX5_SET(copy_action_in, action_ptr, dst_offset, 24 + tos_size);
+		MLX5_SET(copy_action_in, action_ptr, length, MLX5DR_ACTION_NAT64_ECN_SIZE);
+		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+	}
 
 	/* set sip and dip to 0, in order to have new csum */
 	mlx5dr_action_create_nat64_zero_all_addr(&action_ptr, is_v4_to_v6);
@@ -543,10 +562,13 @@ mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 	uint32_t packet_len_field;
 	uint32_t packet_len_add;
 	uint8_t *action_ptr;
+	uint32_t tos_field;
 	uint32_t ttl_field;
+	uint32_t tos_size;
 	uint32_t src_addr;
 	uint32_t dst_addr;
 	bool is_v4_to_v6;
+	uint32_t ecn;
 
 	is_v4_to_v6 = attr->flags & MLX5DR_ACTION_NAT64_V4_TO_V6;
 
@@ -557,6 +579,9 @@ mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 		ttl_field = MLX5_MODI_OUT_IPV6_HOPLIMIT;
 		src_addr = MLX5_MODI_OUT_SIPV6_31_0;
 		dst_addr = MLX5_MODI_OUT_DIPV6_31_0;
+		tos_field = MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS;
+		tos_size = 8;
+		ecn = 0;
 	} else {
 		packet_len_field = MLX5_MODI_OUT_IPV4_TOTAL_LEN;
 		/* ipv4 len is including 20 bytes of the header, so add 20 over ipv6 len */
@@ -564,6 +589,9 @@ mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 		ttl_field = MLX5_MODI_OUT_IPV4_TTL;
 		src_addr = MLX5_MODI_OUT_SIPV4;
 		dst_addr = MLX5_MODI_OUT_DIPV4;
+		tos_field = MLX5_MODI_OUT_IP_DSCP;
+		tos_size = 6;
+		ecn = MLX5_MODI_OUT_IP_ECN;
 	}
 
 	memset(modify_action_data, 0, sizeof(modify_action_data));
@@ -578,20 +606,34 @@ mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 	MLX5_SET(copy_action_in, action_ptr, length, 16);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
-	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
-	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
-
-	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
+	MLX5_SET(set_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+	MLX5_SET(set_action_in, action_ptr, field, ttl_field);
+	MLX5_SET(set_action_in, action_ptr, length, 8);
+	MLX5_SET(set_action_in, action_ptr, data, MLX5DR_ACTION_NAT64_TTL_DEFAULT_VAL);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
+	/* copy TOS */
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
 	MLX5_SET(copy_action_in, action_ptr, src_field,
 		 attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
-	MLX5_SET(copy_action_in, action_ptr, dst_field, ttl_field);
+	MLX5_SET(copy_action_in, action_ptr, dst_field, tos_field);
 	MLX5_SET(copy_action_in, action_ptr, src_offset, 24);
-	MLX5_SET(copy_action_in, action_ptr, length, 8);
+	MLX5_SET(copy_action_in, action_ptr, length, tos_size);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
+	if (ecn) {
+		MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
+		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
+		MLX5_SET(copy_action_in, action_ptr, src_field,
+			attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
+		MLX5_SET(copy_action_in, action_ptr, dst_field, ecn);
+		MLX5_SET(copy_action_in, action_ptr, src_offset, 24 + tos_size);
+		MLX5_SET(copy_action_in, action_ptr, length, MLX5DR_ACTION_NAT64_ECN_SIZE);
+		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+	}
+
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
diff --git a/drivers/net/mlx5/hws/mlx5dr_action.h b/drivers/net/mlx5/hws/mlx5dr_action.h
index faea6bb1f4..ba4ce55228 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.h
+++ b/drivers/net/mlx5/hws/mlx5dr_action.h
@@ -79,6 +79,8 @@ enum {
 	MLX5DR_ACTION_NAT64_IPV4_HEADER = 5,
 	MLX5DR_ACTION_NAT64_IPV6_VER = 0x60000000,
 	MLX5DR_ACTION_NAT64_IPV4_VER = 0x45000000,
+	MLX5DR_ACTION_NAT64_TTL_DEFAULT_VAL = 64,
+	MLX5DR_ACTION_NAT64_ECN_SIZE = 2,
 };
 
 /* 3 stages for the nat64 action */
-- 
2.39.3

[PATCH 0/8] HW steering team updates

[Itamar Gozlan]

This patch series contains 8 commits from the HW steering team,
addressing
various improvements and fixes in the DPDK project.

This is the second version of this submission. The previous version
erroneously included two unnecessary commits, which have been removed in
this iteration.

Alex Vesker (1):
  net/mlx5/hws: fix incorrect port ID on root item convert

Erez Shitrit (6):
  net/mlx5/hws: set eswitch owner vhc ID valid accordingly
  net/mlx5/hws: fix memory leak in modify header free
  net/mlx5/hws: fix deletion of action vport
  net/mlx5/hws: take out not needed variable
  net/mlx5/hws: fix NAT64 csum issue
  net/mlx5/hws: fix NA64 copy TOS field instead of TTL

Itamar Gozlan (1):
  net/mlx5/hws: strictly range templates check fix

 drivers/net/mlx5/hws/mlx5dr_action.c  | 213 ++++++++++++++++++++++----
 drivers/net/mlx5/hws/mlx5dr_action.h  |  17 +-
 drivers/net/mlx5/hws/mlx5dr_cmd.c     |   6 +-
 drivers/net/mlx5/hws/mlx5dr_cmd.h     |   1 +
 drivers/net/mlx5/hws/mlx5dr_definer.c |  11 +-
 drivers/net/mlx5/hws/mlx5dr_matcher.c |  20 +--
 drivers/net/mlx5/hws/mlx5dr_pat_arg.h |   1 -
 drivers/net/mlx5/hws/mlx5dr_rule.c    |  22 +--
 8 files changed, 216 insertions(+), 75 deletions(-)

-- 
2.39.3

[PATCH 1/8] net/mlx5/hws: set eswitch owner vhc ID valid accordingly

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

eswitch_owner_vhca_id_valid value should be set to 1 only on
merged-eswitch device.

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_action.c | 12 ++++++++++++
 drivers/net/mlx5/hws/mlx5dr_cmd.c    |  3 ++-
 drivers/net/mlx5/hws/mlx5dr_cmd.h    |  1 +
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c
index 90f2f17bd0..03c3683f71 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -680,6 +680,8 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx,
 			fixup_stc_attr->stc_offset = stc_attr->stc_offset;
 			fixup_stc_attr->vport.esw_owner_vhca_id = ctx->caps->vhca_id;
 			fixup_stc_attr->vport.vport_num = ctx->caps->eswitch_manager_vport_number;
+			fixup_stc_attr->vport.eswitch_owner_vhca_id_valid =
+				ctx->caps->merged_eswitch;
 			use_fixup = true;
 		}
 		break;
@@ -700,6 +702,8 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx,
 			fixup_stc_attr->stc_offset = stc_attr->stc_offset;
 			fixup_stc_attr->vport.vport_num = 0;
 			fixup_stc_attr->vport.esw_owner_vhca_id = stc_attr->vport.esw_owner_vhca_id;
+			fixup_stc_attr->vport.eswitch_owner_vhca_id_valid =
+				ctx->caps->merged_eswitch;
 		}
 		use_fixup = true;
 		break;
@@ -1429,6 +1433,14 @@ static int mlx5dr_action_create_dest_vport_hws(struct mlx5dr_context *ctx,
 	action->vport.vport_num = vport_caps.vport_num;
 	action->vport.esw_owner_vhca_id = vport_caps.esw_owner_vhca_id;
 
+	if (!ctx->caps->merged_eswitch &&
+	    action->vport.esw_owner_vhca_id != ctx->caps->vhca_id) {
+		DR_LOG(ERR, "Not merged-eswitch (%d), not allowed to send to other vhca_id (%d)",
+		       ctx->caps->vhca_id, action->vport.esw_owner_vhca_id);
+		rte_errno = ENOTSUP;
+		return rte_errno;
+	}
+
 	ret = mlx5dr_action_create_stcs(action, NULL);
 	if (ret) {
 		DR_LOG(ERR, "Failed creating stc for port %d", ib_port_num);
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index 666d678b42..72fc9e3d91 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -515,7 +515,8 @@ mlx5dr_cmd_stc_modify_set_stc_param(struct mlx5dr_cmd_stc_modify_attr *stc_attr,
 			 stc_attr->vport.vport_num);
 		MLX5_SET(stc_ste_param_vport, stc_param, eswitch_owner_vhca_id,
 			 stc_attr->vport.esw_owner_vhca_id);
-		MLX5_SET(stc_ste_param_vport, stc_param, eswitch_owner_vhca_id_valid, 1);
+		MLX5_SET(stc_ste_param_vport, stc_param, eswitch_owner_vhca_id_valid,
+			 stc_attr->vport.eswitch_owner_vhca_id_valid);
 		break;
 	case MLX5_IFC_STC_ACTION_TYPE_DROP:
 	case MLX5_IFC_STC_ACTION_TYPE_NOP:
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index ea5d346d8e..54840ec445 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -133,6 +133,7 @@ struct mlx5dr_cmd_stc_modify_attr {
 		struct {
 			uint16_t vport_num;
 			uint16_t esw_owner_vhca_id;
+			uint8_t eswitch_owner_vhca_id_valid;
 		} vport;
 		struct {
 			struct mlx5dr_pool_chunk ste;
-- 
2.39.3

[PATCH 2/8] net/mlx5/hws: fix memory leak in modify header free

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

When creating action from type MLX5DR_ACTION_TYP_REFORMAT_TNL_L3_TO_L2
we use modify-header object, we support few of that type at the same
time over this action depends on the number of headers.
Now when destroying the modify-header object we run over the
number_of_patterns, this variable was not set in the creation of that
action.

Fixes: 3a6c50215c07 ("net/mlx5/hws: support multi-pattern")
Cc: valex@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_action.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c
index 03c3683f71..b90f18df8a 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -1820,6 +1820,7 @@ mlx5dr_action_handle_tunnel_l3_to_l2(struct mlx5dr_action *action,
 
 		action[i].modify_header.max_num_of_actions = num_of_actions;
 		action[i].modify_header.num_of_actions = num_of_actions;
+		action[i].modify_header.num_of_patterns = num_of_hdrs;
 		action[i].modify_header.arg_obj = arg_obj;
 		action[i].modify_header.pat_obj = pat_obj;
 		action[i].modify_header.require_reparse =
-- 
2.39.3

[PATCH 3/8] net/mlx5/hws: strictly range templates check fix

[Itamar Gozlan]

Using range and non range templates is not allowed, and in HWS there is a
check that enforce that limitation with constantly check that, in a loop,
if the current template defined as range, the last one
should also be defined as range.
But, in the case where there are two templates in the following order:
(1) template with range, and (2) template without range.
The existing checks will not cover this case.
This commit fixes that hole by maintain the invariant that if a template
without a range exist, all the previous match template are also.

Fixes: 9732ffe13bd6 ("net/mlx5/hws: add range definer creation")
Cc: valex@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Itamar Gozlan <igozlan@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 9ebda9267d..51a3f7be4b 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -4041,15 +4041,18 @@ mlx5dr_definer_matcher_range_init(struct mlx5dr_context *ctx,
 
 	/* Create optional range definers */
 	for (i = 0; i < matcher->num_of_mt; i++) {
-		if (!mt[i].fcr_sz)
-			continue;
-
 		/* All must use range if requested */
-		if (i && !mt[i - 1].range_definer) {
+		bool is_range = !!mt[i].fcr_sz;
+		bool has_range = matcher->flags & MLX5DR_MATCHER_FLAGS_RANGE_DEFINER;
+
+		if (i && ((is_range && !has_range) || (!is_range && has_range))) {
 			DR_LOG(ERR, "Using range and non range templates is not allowed");
 			goto free_definers;
 		}
 
+		if (!mt[i].fcr_sz)
+			continue;
+
 		matcher->flags |= MLX5DR_MATCHER_FLAGS_RANGE_DEFINER;
 		/* Create definer without fcr binding, already binded */
 		mt[i].range_definer = mlx5dr_definer_alloc(ctx,
-- 
2.39.3

[PATCH 4/8] net/mlx5/hws: fix deletion of action vport

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

No more ignoring this action while destroying it.

Fixes: f8c8a6d8440d ("net/mlx5/hws: add action object")
Cc: erezsh@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_action.c | 4 ++++
 drivers/net/mlx5/hws/mlx5dr_cmd.c    | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c
index b90f18df8a..0d90280a7d 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -2968,6 +2968,7 @@ static void mlx5dr_action_destroy_hws(struct mlx5dr_action *action)
 	case MLX5DR_ACTION_TYP_ASO_CT:
 	case MLX5DR_ACTION_TYP_PUSH_VLAN:
 	case MLX5DR_ACTION_TYP_REMOVE_HEADER:
+	case MLX5DR_ACTION_TYP_VPORT:
 		mlx5dr_action_destroy_stcs(action);
 		break;
 	case MLX5DR_ACTION_TYP_DEST_ROOT:
@@ -3027,6 +3028,9 @@ static void mlx5dr_action_destroy_hws(struct mlx5dr_action *action)
 		break;
 	case MLX5DR_ACTION_TYP_LAST:
 		break;
+	default:
+		DR_LOG(ERR, "Not supported action type: %d", action->type);
+		assert(false);
 	}
 }
 
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index 72fc9e3d91..a4f778a8a4 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -1033,7 +1033,8 @@ int mlx5dr_cmd_generate_wqe(struct ibv_context *ctx,
 
 	ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 	if (ret) {
-		DR_LOG(ERR, "Failed to write GTA WQE using FW");
+		DR_LOG(ERR, "Failed to write GTA WQE using FW (syndrome: %#x)",
+		       mlx5dr_cmd_get_syndrome(out));
 		rte_errno = errno;
 		return rte_errno;
 	}
-- 
2.39.3

[PATCH 5/8] net/mlx5/hws: fix incorrect port ID on root item convert

[Itamar Gozlan]

From: Alex Vesker <valex@nvidia.com>

When calling item convert function we need to pass the port_id
in the attributes. This value should be passed not only for cases
that match on PORT related items, to resolve we will always pass it.

Fixes: 572fe9ef2f46 ("net/mlx5/hws: fix port ID for root table")
Cc: erezsh@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Alex Vesker <valex@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_matcher.c | 20 +++++---------------
 drivers/net/mlx5/hws/mlx5dr_rule.c    | 22 ++++++----------------
 2 files changed, 11 insertions(+), 31 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c
index 6a939eb031..dfa2cd435c 100644
--- a/drivers/net/mlx5/hws/mlx5dr_matcher.c
+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c
@@ -1231,7 +1231,6 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher)
 	struct mlx5dv_flow_match_parameters *mask;
 	struct mlx5_flow_attr flow_attr = {0};
 	struct rte_flow_error rte_error;
-	struct rte_flow_item *item;
 	uint8_t match_criteria;
 	int ret;
 
@@ -1260,20 +1259,11 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher)
 		return rte_errno;
 	}
 
-	/* We need the port id in case of matching representor */
-	item = matcher->mt[0].items;
-	while (item->type != RTE_FLOW_ITEM_TYPE_END) {
-		if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR ||
-		    item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) {
-			ret = flow_hw_get_port_id_from_ctx(ctx, &flow_attr.port_id);
-			if (ret) {
-				DR_LOG(ERR, "Failed to get port id for dev %s",
-				       ctx->ibv_ctx->device->name);
-				rte_errno = EINVAL;
-				return rte_errno;
-			}
-		}
-		++item;
+	ret = flow_hw_get_port_id_from_ctx(ctx, &flow_attr.port_id);
+	if (ret) {
+		DR_LOG(ERR, "Failed to get port id for dev %s", ctx->ibv_ctx->device->name);
+		rte_errno = EINVAL;
+		return rte_errno;
 	}
 
 	mask = simple_calloc(1, MLX5_ST_SZ_BYTES(fte_match_param) +
diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c
index 06d8e66f63..1edb7eac74 100644
--- a/drivers/net/mlx5/hws/mlx5dr_rule.c
+++ b/drivers/net/mlx5/hws/mlx5dr_rule.c
@@ -694,29 +694,19 @@ int mlx5dr_rule_create_root_no_comp(struct mlx5dr_rule *rule,
 				    struct mlx5dr_rule_action rule_actions[])
 {
 	struct mlx5dv_flow_matcher *dv_matcher = rule->matcher->dv_matcher;
+	struct mlx5dr_context *ctx = rule->matcher->tbl->ctx;
 	struct mlx5dv_flow_match_parameters *value;
 	struct mlx5_flow_attr flow_attr = {0};
 	struct mlx5dv_flow_action_attr *attr;
-	const struct rte_flow_item *cur_item;
 	struct rte_flow_error error;
 	uint8_t match_criteria;
 	int ret;
 
-	/* We need the port id in case of matching representor */
-	cur_item = items;
-	while (cur_item->type != RTE_FLOW_ITEM_TYPE_END) {
-		if (cur_item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR ||
-		    cur_item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) {
-			ret = flow_hw_get_port_id_from_ctx(rule->matcher->tbl->ctx,
-							   &flow_attr.port_id);
-			if (ret) {
-				DR_LOG(ERR, "Failed to get port id for dev %s",
-				       rule->matcher->tbl->ctx->ibv_ctx->device->name);
-				rte_errno = EINVAL;
-				return rte_errno;
-			}
-		}
-		++cur_item;
+	ret = flow_hw_get_port_id_from_ctx(ctx, &flow_attr.port_id);
+	if (ret) {
+		DR_LOG(ERR, "Failed to get port id for dev %s", ctx->ibv_ctx->device->name);
+		rte_errno = EINVAL;
+		return rte_errno;
 	}
 
 	attr = simple_calloc(num_actions, sizeof(*attr));
-- 
2.39.3

[PATCH 6/8] net/mlx5/hws: take out not needed variable

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

Removing a redundant variable.
Was there from day 1, not in use.

Fixes: f8c8a6d8440d ("net/mlx5/hws: add action object")
Cc: erezsh@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_pat_arg.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_pat_arg.h b/drivers/net/mlx5/hws/mlx5dr_pat_arg.h
index bbe313102f..c4e0cbc843 100644
--- a/drivers/net/mlx5/hws/mlx5dr_pat_arg.h
+++ b/drivers/net/mlx5/hws/mlx5dr_pat_arg.h
@@ -30,7 +30,6 @@ struct mlx5dr_pattern_cache {
 struct mlx5dr_pattern_cache_item {
 	struct {
 		struct mlx5dr_devx_obj *pattern_obj;
-		struct dr_icm_chunk *chunk;
 		uint8_t *data;
 		uint16_t num_of_actions;
 	} mh_data;
-- 
2.39.3

[PATCH 7/8] net/mlx5/hws: fix NAT64 csum issue

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

Due to HW limitation we got two csum's that were not correct, udp and
ip, both of them were not calculated correctly by the HW.
By adding the next W/A we allow the HW to collect it well:
Separate the protocol field and zero all the addresses before fixed the
UDP csum.
We saw that the IP csum by the HW didn't take the ipv4 version as part
of the csum because the way it was inserted into the packet, in order to
solve that we added a prefix that takes into account the real csum for
the ip version and from that point the HW calculating the csum correctly.

Fixes: 06d969a8c5b8 ("net/mlx5/hws: support NAT64 flow action")
Cc: erezsh@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_action.c | 136 ++++++++++++++++++++++-----
 drivers/net/mlx5/hws/mlx5dr_action.h |  15 ++-
 2 files changed, 123 insertions(+), 28 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c
index 0d90280a7d..8d3d0033e5 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -249,6 +249,62 @@ static void mlx5dr_action_put_shared_stc(struct mlx5dr_action *action,
 		mlx5dr_action_put_shared_stc_nic(ctx, stc_type, MLX5DR_TABLE_TYPE_FDB);
 }
 
+static void
+mlx5dr_action_create_nat64_zero_all_addr(uint8_t **action_ptr, bool is_v4_to_v6)
+{
+	if (is_v4_to_v6) {
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV4);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV4);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+	} else {
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_127_96);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_95_64);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_63_32);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_SIPV6_31_0);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_127_96);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_95_64);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_63_32);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(set_action_in, *action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+		MLX5_SET(set_action_in, *action_ptr, field, MLX5_MODI_OUT_DIPV6_31_0);
+		MLX5_SET(set_action_in, *action_ptr, data, 0);
+		*action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+	}
+}
+
 static struct mlx5dr_action *
 mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx,
 				      struct mlx5dr_action_nat64_attr *attr,
@@ -329,17 +385,7 @@ mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx,
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
 	/* set sip and dip to 0, in order to have new csum */
-	if (is_v4_to_v6) {
-		MLX5_SET(set_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
-		MLX5_SET(set_action_in, action_ptr, field, MLX5_MODI_OUT_SIPV4);
-		MLX5_SET(set_action_in, action_ptr, data, 0);
-		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
-
-		MLX5_SET(set_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
-		MLX5_SET(set_action_in, action_ptr, field, MLX5_MODI_OUT_DIPV4);
-		MLX5_SET(set_action_in, action_ptr, data, 0);
-		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
-	}
+	mlx5dr_action_create_nat64_zero_all_addr(&action_ptr, is_v4_to_v6);
 
 	pat[0].data = modify_action_data;
 	pat[0].sz = (action_ptr - (uint8_t *)modify_action_data);
@@ -383,9 +429,14 @@ mlx5dr_action_create_nat64_repalce_state(struct mlx5dr_context *ctx,
 		memcpy(address_prefix, nat64_well_known_pref,
 		       MLX5DR_ACTION_NAT64_HEADER_MINUS_ONE * sizeof(uint32_t));
 	} else {
+		/* In order to fix HW csum issue, make the prefix ready */
+		uint32_t ipv4_pref[] = {0x0, 0xffba0000, 0x0, 0x0, 0x0};
+
 		header_size_in_dw = MLX5DR_ACTION_NAT64_IPV4_HEADER;
 		ip_ver = MLX5DR_ACTION_NAT64_IPV4_VER;
 		eth_type = RTE_ETHER_TYPE_IPV4;
+		memcpy(address_prefix, ipv4_pref,
+		       MLX5DR_ACTION_NAT64_IPV4_HEADER * sizeof(uint32_t));
 	}
 
 	memset(modify_action_data, 0, sizeof(modify_action_data));
@@ -441,6 +492,46 @@ mlx5dr_action_create_nat64_repalce_state(struct mlx5dr_context *ctx,
 	return action;
 }
 
+static struct mlx5dr_action *
+mlx5dr_action_create_nat64_copy_proto_state(struct mlx5dr_context *ctx,
+					    struct mlx5dr_action_nat64_attr *attr,
+					    uint32_t flags)
+{
+	__be64 modify_action_data[MLX5DR_ACTION_NAT64_MAX_MODIFY_ACTIONS];
+	struct mlx5dr_action_mh_pattern pat[2];
+	struct mlx5dr_action *action;
+	uint8_t *action_ptr;
+
+	memset(modify_action_data, 0, sizeof(modify_action_data));
+	action_ptr = (uint8_t *)modify_action_data;
+
+	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
+	MLX5_SET(copy_action_in, action_ptr, src_field,
+		 attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
+	MLX5_SET(copy_action_in, action_ptr, dst_field,
+		 MLX5_MODI_OUT_IP_PROTOCOL);
+	MLX5_SET(copy_action_in, action_ptr, src_offset, 16);
+	MLX5_SET(copy_action_in, action_ptr, dst_offset, 0);
+	MLX5_SET(copy_action_in, action_ptr, length, 8);
+	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
+	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+	pat[0].data = modify_action_data;
+	pat[0].sz = action_ptr - (uint8_t *)modify_action_data;
+
+	action = mlx5dr_action_create_modify_header_reparse(ctx, 1, pat, 0, flags,
+							    MLX5DR_ACTION_STC_REPARSE_ON);
+	if (!action) {
+		DR_LOG(ERR, "Failed to create action: action_sz: %zu, flags: 0x%x\n",
+		       pat[0].sz, flags);
+		return NULL;
+	}
+
+	return action;
+}
+
 static struct mlx5dr_action *
 mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 					   struct mlx5dr_action_nat64_attr *attr,
@@ -490,16 +581,6 @@ mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
-	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
-	MLX5_SET(copy_action_in, action_ptr, src_field,
-		 attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
-	MLX5_SET(copy_action_in, action_ptr, dst_field,
-		 MLX5_MODI_OUT_IP_PROTOCOL);
-	MLX5_SET(copy_action_in, action_ptr, src_offset, 16);
-	MLX5_SET(copy_action_in, action_ptr, dst_offset, 0);
-	MLX5_SET(copy_action_in, action_ptr, length, 8);
-	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
-
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
@@ -2051,7 +2132,7 @@ mlx5dr_action_create_modify_header_hws(struct mlx5dr_action *action,
 	return rte_errno;
 }
 
-static struct mlx5dr_action *
+struct mlx5dr_action *
 mlx5dr_action_create_modify_header_reparse(struct mlx5dr_context *ctx,
 					   uint8_t num_of_patterns,
 					   struct mlx5dr_action_mh_pattern *patterns,
@@ -2927,17 +3008,24 @@ mlx5dr_action_create_nat64(struct mlx5dr_context *ctx,
 		DR_LOG(ERR, "Nat64 failed creating replace state");
 		goto free_copy;
 	}
+	action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL] =
+		mlx5dr_action_create_nat64_copy_proto_state(ctx, attr, flags);
+	if (!action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL]) {
+		DR_LOG(ERR, "Nat64 failed creating copy protocol state");
+		goto free_replace;
+	}
 
 	action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPYBACK] =
 		mlx5dr_action_create_nat64_copy_back_state(ctx, attr, flags);
 	if (!action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPYBACK]) {
 		DR_LOG(ERR, "Nat64 failed creating copyback state");
-		goto free_replace;
+		goto free_copy_proto;
 	}
 
 	return action;
 
-
+free_copy_proto:
+	mlx5dr_action_destroy(action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL]);
 free_replace:
 	mlx5dr_action_destroy(action->nat64.stages[MLX5DR_ACTION_NAT64_STAGE_REPLACE]);
 free_copy:
diff --git a/drivers/net/mlx5/hws/mlx5dr_action.h b/drivers/net/mlx5/hws/mlx5dr_action.h
index 57e059a572..faea6bb1f4 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.h
+++ b/drivers/net/mlx5/hws/mlx5dr_action.h
@@ -11,9 +11,6 @@
 /* Max number of internal subactions of ipv6_ext */
 #define MLX5DR_ACTION_IPV6_EXT_MAX_SA 4
 
-/* Number of MH in NAT64 */
-#define MLX5DR_ACTION_NAT64_STAGES 3
-
 enum mlx5dr_action_stc_idx {
 	MLX5DR_ACTION_STC_IDX_CTRL = 0,
 	MLX5DR_ACTION_STC_IDX_HIT = 1,
@@ -88,7 +85,10 @@ enum {
 enum mlx5dr_action_nat64_stages {
 	MLX5DR_ACTION_NAT64_STAGE_COPY = 0,
 	MLX5DR_ACTION_NAT64_STAGE_REPLACE = 1,
-	MLX5DR_ACTION_NAT64_STAGE_COPYBACK = 2,
+	MLX5DR_ACTION_NAT64_STAGE_COPY_PROTOCOL = 2,
+	MLX5DR_ACTION_NAT64_STAGE_COPYBACK = 3,
+	/* Number of MH in NAT64 */
+	MLX5DR_ACTION_NAT64_STAGES = 4,
 };
 
 /* Registers for keeping data from stage to stage */
@@ -256,6 +256,13 @@ int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx,
 void mlx5dr_action_free_single_stc(struct mlx5dr_context *ctx,
 				   uint32_t table_type,
 				   struct mlx5dr_pool_chunk *stc);
+struct mlx5dr_action *
+mlx5dr_action_create_modify_header_reparse(struct mlx5dr_context *ctx,
+					   uint8_t num_of_patterns,
+					   struct mlx5dr_action_mh_pattern *patterns,
+					   uint32_t log_bulk_size,
+					   uint32_t flags, uint32_t reparse);
+
 
 static inline void
 mlx5dr_action_setter_default_single(struct mlx5dr_actions_apply_data *apply,
-- 
2.39.3

[PATCH 8/8] net/mlx5/hws: fix NA64 copy TOS field instead of TTL

[Itamar Gozlan]

From: Erez Shitrit <erezsh@nvidia.com>

We don't have enough registers to copy TTL and TOS, so we will set TTL
to be the default value (64) and will copy TOS.

Fixes: 06d969a8c5b8 ("net/mlx5/hws: support NAT64 flow action")
Cc: erezsh@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_action.c | 66 +++++++++++++++++++++++-----
 drivers/net/mlx5/hws/mlx5dr_action.h |  2 +
 2 files changed, 56 insertions(+), 12 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c
index 8d3d0033e5..8f6be37818 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.c
+++ b/drivers/net/mlx5/hws/mlx5dr_action.c
@@ -315,21 +315,27 @@ mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx,
 	struct mlx5dr_action *action;
 	uint32_t packet_len_field;
 	uint8_t *action_ptr;
-	uint32_t ttl_field;
+	uint32_t tos_field;
+	uint32_t tos_size;
 	uint32_t src_addr;
 	uint32_t dst_addr;
 	bool is_v4_to_v6;
+	uint32_t ecn;
 
 	is_v4_to_v6 = attr->flags & MLX5DR_ACTION_NAT64_V4_TO_V6;
 
 	if (is_v4_to_v6) {
 		packet_len_field = MLX5_MODI_OUT_IPV4_TOTAL_LEN;
-		ttl_field = MLX5_MODI_OUT_IPV4_TTL;
+		tos_field = MLX5_MODI_OUT_IP_DSCP;
+		tos_size = 6;
+		ecn = MLX5_MODI_OUT_IP_ECN;
 		src_addr = MLX5_MODI_OUT_SIPV4;
 		dst_addr = MLX5_MODI_OUT_DIPV4;
 	} else {
 		packet_len_field = MLX5_MODI_OUT_IPV6_PAYLOAD_LEN;
-		ttl_field = MLX5_MODI_OUT_IPV6_HOPLIMIT;
+		tos_field = MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS;
+		tos_size = 8;
+		ecn = 0;
 		src_addr = MLX5_MODI_OUT_SIPV6_31_0;
 		dst_addr = MLX5_MODI_OUT_DIPV6_31_0;
 	}
@@ -352,7 +358,7 @@ mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx,
 	}
 
 	/* | 8 bit - 8 bit     - 16 bit     |
-	 * | ttl   - protocol  - packet-len |
+	 * | TOS   - protocol  - packet-len |
 	 */
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
 	MLX5_SET(copy_action_in, action_ptr, src_field, packet_len_field);
@@ -377,12 +383,25 @@ mlx5dr_action_create_nat64_copy_state(struct mlx5dr_context *ctx,
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
-	MLX5_SET(copy_action_in, action_ptr, src_field, ttl_field);
+	MLX5_SET(copy_action_in, action_ptr, src_field, tos_field);
 	MLX5_SET(copy_action_in, action_ptr, dst_field,
 		 attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
 	MLX5_SET(copy_action_in, action_ptr, dst_offset, 24);
-	MLX5_SET(copy_action_in, action_ptr, length, 8);
+	MLX5_SET(copy_action_in, action_ptr, length, tos_size);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+	/* in ipv4 TOS = {dscp (6bits) - ecn (2bits) }*/
+	if (ecn) {
+		MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
+		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
+		MLX5_SET(copy_action_in, action_ptr, src_field, ecn);
+		MLX5_SET(copy_action_in, action_ptr, dst_field,
+			attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
+		MLX5_SET(copy_action_in, action_ptr, dst_offset, 24 + tos_size);
+		MLX5_SET(copy_action_in, action_ptr, length, MLX5DR_ACTION_NAT64_ECN_SIZE);
+		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+	}
 
 	/* set sip and dip to 0, in order to have new csum */
 	mlx5dr_action_create_nat64_zero_all_addr(&action_ptr, is_v4_to_v6);
@@ -543,10 +562,13 @@ mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 	uint32_t packet_len_field;
 	uint32_t packet_len_add;
 	uint8_t *action_ptr;
+	uint32_t tos_field;
 	uint32_t ttl_field;
+	uint32_t tos_size;
 	uint32_t src_addr;
 	uint32_t dst_addr;
 	bool is_v4_to_v6;
+	uint32_t ecn;
 
 	is_v4_to_v6 = attr->flags & MLX5DR_ACTION_NAT64_V4_TO_V6;
 
@@ -557,6 +579,9 @@ mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 		ttl_field = MLX5_MODI_OUT_IPV6_HOPLIMIT;
 		src_addr = MLX5_MODI_OUT_SIPV6_31_0;
 		dst_addr = MLX5_MODI_OUT_DIPV6_31_0;
+		tos_field = MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS;
+		tos_size = 8;
+		ecn = 0;
 	} else {
 		packet_len_field = MLX5_MODI_OUT_IPV4_TOTAL_LEN;
 		/* ipv4 len is including 20 bytes of the header, so add 20 over ipv6 len */
@@ -564,6 +589,9 @@ mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 		ttl_field = MLX5_MODI_OUT_IPV4_TTL;
 		src_addr = MLX5_MODI_OUT_SIPV4;
 		dst_addr = MLX5_MODI_OUT_DIPV4;
+		tos_field = MLX5_MODI_OUT_IP_DSCP;
+		tos_size = 6;
+		ecn = MLX5_MODI_OUT_IP_ECN;
 	}
 
 	memset(modify_action_data, 0, sizeof(modify_action_data));
@@ -578,20 +606,34 @@ mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
 	MLX5_SET(copy_action_in, action_ptr, length, 16);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
-	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
-	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
-
-	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
+	MLX5_SET(set_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_SET);
+	MLX5_SET(set_action_in, action_ptr, field, ttl_field);
+	MLX5_SET(set_action_in, action_ptr, length, 8);
+	MLX5_SET(set_action_in, action_ptr, data, MLX5DR_ACTION_NAT64_TTL_DEFAULT_VAL);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
+	/* copy TOS */
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
 	MLX5_SET(copy_action_in, action_ptr, src_field,
 		 attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
-	MLX5_SET(copy_action_in, action_ptr, dst_field, ttl_field);
+	MLX5_SET(copy_action_in, action_ptr, dst_field, tos_field);
 	MLX5_SET(copy_action_in, action_ptr, src_offset, 24);
-	MLX5_SET(copy_action_in, action_ptr, length, 8);
+	MLX5_SET(copy_action_in, action_ptr, length, tos_size);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
+	if (ecn) {
+		MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
+		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+
+		MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_COPY);
+		MLX5_SET(copy_action_in, action_ptr, src_field,
+			attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
+		MLX5_SET(copy_action_in, action_ptr, dst_field, ecn);
+		MLX5_SET(copy_action_in, action_ptr, src_offset, 24 + tos_size);
+		MLX5_SET(copy_action_in, action_ptr, length, MLX5DR_ACTION_NAT64_ECN_SIZE);
+		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
+	}
+
 	MLX5_SET(copy_action_in, action_ptr, action_type, MLX5_MODIFICATION_TYPE_NOP);
 	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
 
diff --git a/drivers/net/mlx5/hws/mlx5dr_action.h b/drivers/net/mlx5/hws/mlx5dr_action.h
index faea6bb1f4..ba4ce55228 100644
--- a/drivers/net/mlx5/hws/mlx5dr_action.h
+++ b/drivers/net/mlx5/hws/mlx5dr_action.h
@@ -79,6 +79,8 @@ enum {
 	MLX5DR_ACTION_NAT64_IPV4_HEADER = 5,
 	MLX5DR_ACTION_NAT64_IPV6_VER = 0x60000000,
 	MLX5DR_ACTION_NAT64_IPV4_VER = 0x45000000,
+	MLX5DR_ACTION_NAT64_TTL_DEFAULT_VAL = 64,
+	MLX5DR_ACTION_NAT64_ECN_SIZE = 2,
 };
 
 /* 3 stages for the nat64 action */
-- 
2.39.3

RE: [PATCH 8/8] net/mlx5/hws: fix NA64 copy TOS field instead of TTL

[Bing Zhao]

Hi Itamar & Erez,

Typo: NA64 -> NAT64

BR. Bing

> -----Original Message-----
> From: Itamar Gozlan <igozlan@nvidia.com>
> Sent: Tuesday, July 9, 2024 8:31 PM
> To: Itamar Gozlan <igozlan@nvidia.com>; Erez Shitrit <erezsh@nvidia.com>;
> Hamdan Agbariya <hamdani@nvidia.com>; Yevgeny Kliteynik
> <kliteyn@nvidia.com>; Alex Vesker <valex@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; NBU-Contact-Thomas Monjalon (EXTERNAL)
> <thomas@monjalon.net>; Suanming Mou <suanmingm@nvidia.com>; Dariusz
> Sosnowski <dsosnowski@nvidia.com>; Bing Zhao <bingz@nvidia.com>; Ori Kam
> <orika@nvidia.com>; Matan Azrad <matan@nvidia.com>
> Cc: dev@dpdk.org; stable@dpdk.org
> Subject: [PATCH 8/8] net/mlx5/hws: fix NA64 copy TOS field instead of TTL
> 
> From: Erez Shitrit <erezsh@nvidia.com>
> 
> We don't have enough registers to copy TTL and TOS, so we will set TTL to
> be the default value (64) and will copy TOS.
> 
> Fixes: 06d969a8c5b8 ("net/mlx5/hws: support NAT64 flow action")
> Cc: erezsh@nvidia.com
> Cc: stable@dpdk.org
> 
> Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
> ---
>  drivers/net/mlx5/hws/mlx5dr_action.c | 66 +++++++++++++++++++++++-----
> drivers/net/mlx5/hws/mlx5dr_action.h |  2 +
>  2 files changed, 56 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c
> b/drivers/net/mlx5/hws/mlx5dr_action.c
> index 8d3d0033e5..8f6be37818 100644
> --- a/drivers/net/mlx5/hws/mlx5dr_action.c
> +++ b/drivers/net/mlx5/hws/mlx5dr_action.c
> @@ -315,21 +315,27 @@ mlx5dr_action_create_nat64_copy_state(struct
> mlx5dr_context *ctx,
>  	struct mlx5dr_action *action;
>  	uint32_t packet_len_field;
>  	uint8_t *action_ptr;
> -	uint32_t ttl_field;
> +	uint32_t tos_field;
> +	uint32_t tos_size;
>  	uint32_t src_addr;
>  	uint32_t dst_addr;
>  	bool is_v4_to_v6;
> +	uint32_t ecn;
> 
>  	is_v4_to_v6 = attr->flags & MLX5DR_ACTION_NAT64_V4_TO_V6;
> 
>  	if (is_v4_to_v6) {
>  		packet_len_field = MLX5_MODI_OUT_IPV4_TOTAL_LEN;
> -		ttl_field = MLX5_MODI_OUT_IPV4_TTL;
> +		tos_field = MLX5_MODI_OUT_IP_DSCP;
> +		tos_size = 6;
> +		ecn = MLX5_MODI_OUT_IP_ECN;
>  		src_addr = MLX5_MODI_OUT_SIPV4;
>  		dst_addr = MLX5_MODI_OUT_DIPV4;
>  	} else {
>  		packet_len_field = MLX5_MODI_OUT_IPV6_PAYLOAD_LEN;
> -		ttl_field = MLX5_MODI_OUT_IPV6_HOPLIMIT;
> +		tos_field = MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS;
> +		tos_size = 8;
> +		ecn = 0;
>  		src_addr = MLX5_MODI_OUT_SIPV6_31_0;
>  		dst_addr = MLX5_MODI_OUT_DIPV6_31_0;
>  	}
> @@ -352,7 +358,7 @@ mlx5dr_action_create_nat64_copy_state(struct
> mlx5dr_context *ctx,
>  	}
> 
>  	/* | 8 bit - 8 bit     - 16 bit     |
> -	 * | ttl   - protocol  - packet-len |
> +	 * | TOS   - protocol  - packet-len |
>  	 */
>  	MLX5_SET(copy_action_in, action_ptr, action_type,
> MLX5_MODIFICATION_TYPE_COPY);
>  	MLX5_SET(copy_action_in, action_ptr, src_field, packet_len_field);
> @@ -377,12 +383,25 @@ mlx5dr_action_create_nat64_copy_state(struct
> mlx5dr_context *ctx,
>  	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
> 
>  	MLX5_SET(copy_action_in, action_ptr, action_type,
> MLX5_MODIFICATION_TYPE_COPY);
> -	MLX5_SET(copy_action_in, action_ptr, src_field, ttl_field);
> +	MLX5_SET(copy_action_in, action_ptr, src_field, tos_field);
>  	MLX5_SET(copy_action_in, action_ptr, dst_field,
>  		 attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
>  	MLX5_SET(copy_action_in, action_ptr, dst_offset, 24);
> -	MLX5_SET(copy_action_in, action_ptr, length, 8);
> +	MLX5_SET(copy_action_in, action_ptr, length, tos_size);
>  	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
> +	/* in ipv4 TOS = {dscp (6bits) - ecn (2bits) }*/
> +	if (ecn) {
> +		MLX5_SET(copy_action_in, action_ptr, action_type,
> MLX5_MODIFICATION_TYPE_NOP);
> +		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
> +
> +		MLX5_SET(copy_action_in, action_ptr, action_type,
> MLX5_MODIFICATION_TYPE_COPY);
> +		MLX5_SET(copy_action_in, action_ptr, src_field, ecn);
> +		MLX5_SET(copy_action_in, action_ptr, dst_field,
> +			attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
> +		MLX5_SET(copy_action_in, action_ptr, dst_offset, 24 +
> tos_size);
> +		MLX5_SET(copy_action_in, action_ptr, length,
> MLX5DR_ACTION_NAT64_ECN_SIZE);
> +		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
> +	}
> 
>  	/* set sip and dip to 0, in order to have new csum */
>  	mlx5dr_action_create_nat64_zero_all_addr(&action_ptr, is_v4_to_v6);
> @@ -543,10 +562,13 @@ mlx5dr_action_create_nat64_copy_back_state(struct
> mlx5dr_context *ctx,
>  	uint32_t packet_len_field;
>  	uint32_t packet_len_add;
>  	uint8_t *action_ptr;
> +	uint32_t tos_field;
>  	uint32_t ttl_field;
> +	uint32_t tos_size;
>  	uint32_t src_addr;
>  	uint32_t dst_addr;
>  	bool is_v4_to_v6;
> +	uint32_t ecn;
> 
>  	is_v4_to_v6 = attr->flags & MLX5DR_ACTION_NAT64_V4_TO_V6;
> 
> @@ -557,6 +579,9 @@ mlx5dr_action_create_nat64_copy_back_state(struct
> mlx5dr_context *ctx,
>  		ttl_field = MLX5_MODI_OUT_IPV6_HOPLIMIT;
>  		src_addr = MLX5_MODI_OUT_SIPV6_31_0;
>  		dst_addr = MLX5_MODI_OUT_DIPV6_31_0;
> +		tos_field = MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS;
> +		tos_size = 8;
> +		ecn = 0;
>  	} else {
>  		packet_len_field = MLX5_MODI_OUT_IPV4_TOTAL_LEN;
>  		/* ipv4 len is including 20 bytes of the header, so add 20
> over ipv6 len */ @@ -564,6 +589,9 @@
> mlx5dr_action_create_nat64_copy_back_state(struct mlx5dr_context *ctx,
>  		ttl_field = MLX5_MODI_OUT_IPV4_TTL;
>  		src_addr = MLX5_MODI_OUT_SIPV4;
>  		dst_addr = MLX5_MODI_OUT_DIPV4;
> +		tos_field = MLX5_MODI_OUT_IP_DSCP;
> +		tos_size = 6;
> +		ecn = MLX5_MODI_OUT_IP_ECN;
>  	}
> 
>  	memset(modify_action_data, 0, sizeof(modify_action_data)); @@ -
> 578,20 +606,34 @@ mlx5dr_action_create_nat64_copy_back_state(struct
> mlx5dr_context *ctx,
>  	MLX5_SET(copy_action_in, action_ptr, length, 16);
>  	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
> 
> -	MLX5_SET(copy_action_in, action_ptr, action_type,
> MLX5_MODIFICATION_TYPE_NOP);
> -	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
> -
> -	MLX5_SET(copy_action_in, action_ptr, action_type,
> MLX5_MODIFICATION_TYPE_NOP);
> +	MLX5_SET(set_action_in, action_ptr, action_type,
> MLX5_MODIFICATION_TYPE_SET);
> +	MLX5_SET(set_action_in, action_ptr, field, ttl_field);
> +	MLX5_SET(set_action_in, action_ptr, length, 8);
> +	MLX5_SET(set_action_in, action_ptr, data,
> +MLX5DR_ACTION_NAT64_TTL_DEFAULT_VAL);
>  	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
> 
> +	/* copy TOS */
>  	MLX5_SET(copy_action_in, action_ptr, action_type,
> MLX5_MODIFICATION_TYPE_COPY);
>  	MLX5_SET(copy_action_in, action_ptr, src_field,
>  		 attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
> -	MLX5_SET(copy_action_in, action_ptr, dst_field, ttl_field);
> +	MLX5_SET(copy_action_in, action_ptr, dst_field, tos_field);
>  	MLX5_SET(copy_action_in, action_ptr, src_offset, 24);
> -	MLX5_SET(copy_action_in, action_ptr, length, 8);
> +	MLX5_SET(copy_action_in, action_ptr, length, tos_size);
>  	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
> 
> +	if (ecn) {
> +		MLX5_SET(copy_action_in, action_ptr, action_type,
> MLX5_MODIFICATION_TYPE_NOP);
> +		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
> +
> +		MLX5_SET(copy_action_in, action_ptr, action_type,
> MLX5_MODIFICATION_TYPE_COPY);
> +		MLX5_SET(copy_action_in, action_ptr, src_field,
> +			attr->registers[MLX5DR_ACTION_NAT64_REG_CONTROL]);
> +		MLX5_SET(copy_action_in, action_ptr, dst_field, ecn);
> +		MLX5_SET(copy_action_in, action_ptr, src_offset, 24 +
> tos_size);
> +		MLX5_SET(copy_action_in, action_ptr, length,
> MLX5DR_ACTION_NAT64_ECN_SIZE);
> +		action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
> +	}
> +
>  	MLX5_SET(copy_action_in, action_ptr, action_type,
> MLX5_MODIFICATION_TYPE_NOP);
>  	action_ptr += MLX5DR_ACTION_DOUBLE_SIZE;
> 
> diff --git a/drivers/net/mlx5/hws/mlx5dr_action.h
> b/drivers/net/mlx5/hws/mlx5dr_action.h
> index faea6bb1f4..ba4ce55228 100644
> --- a/drivers/net/mlx5/hws/mlx5dr_action.h
> +++ b/drivers/net/mlx5/hws/mlx5dr_action.h
> @@ -79,6 +79,8 @@ enum {
>  	MLX5DR_ACTION_NAT64_IPV4_HEADER = 5,
>  	MLX5DR_ACTION_NAT64_IPV6_VER = 0x60000000,
>  	MLX5DR_ACTION_NAT64_IPV4_VER = 0x45000000,
> +	MLX5DR_ACTION_NAT64_TTL_DEFAULT_VAL = 64,
> +	MLX5DR_ACTION_NAT64_ECN_SIZE = 2,
>  };
> 
>  /* 3 stages for the nat64 action */
> --
> 2.39.3

Re: [PATCH 0/8] HW steering team updates

[Raslan Darawsheh]

Hi  Itamar,

From: Itamar Gozlan <igozlan@nvidia.com>
Sent: Tuesday, July 9, 2024 3:30 PM
To: Itamar Gozlan; Erez Shitrit; Hamdan Agbariya; Yevgeny Kliteynik; Alex Vesker; Slava Ovsiienko; NBU-Contact-Thomas Monjalon (EXTERNAL); Suanming Mou
Cc: dev@dpdk.org; Ori Kam
Subject: [PATCH 0/8] HW steering team updates

This patch series contains 8 commits from the HW steering team,
addressing
various improvements and fixes in the DPDK project.

This is the second version of this submission. The previous version
erroneously included two unnecessary commits, which have been removed in
this iteration.

Alex Vesker (1):
  net/mlx5/hws: fix incorrect port ID on root item convert

Erez Shitrit (6):
  net/mlx5/hws: set eswitch owner vhc ID valid accordingly
  net/mlx5/hws: fix memory leak in modify header free
  net/mlx5/hws: fix deletion of action vport
  net/mlx5/hws: take out not needed variable
  net/mlx5/hws: fix NAT64 csum issue
  net/mlx5/hws: fix NA64 copy TOS field instead of TTL

Itamar Gozlan (1):
  net/mlx5/hws: strictly range templates check fix

 drivers/net/mlx5/hws/mlx5dr_action.c  | 213 ++++++++++++++++++++++----
 drivers/net/mlx5/hws/mlx5dr_action.h  |  17 +-
 drivers/net/mlx5/hws/mlx5dr_cmd.c     |   6 +-
 drivers/net/mlx5/hws/mlx5dr_cmd.h     |   1 +
 drivers/net/mlx5/hws/mlx5dr_definer.c |  11 +-
 drivers/net/mlx5/hws/mlx5dr_matcher.c |  20 +--
 drivers/net/mlx5/hws/mlx5dr_pat_arg.h |   1 -
 drivers/net/mlx5/hws/mlx5dr_rule.c    |  22 +--
 8 files changed, 216 insertions(+), 75 deletions(-)

--
2.39.3


Series applied to next-net-mlx,

Kindest regards
Raslan Darawsheh