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Tue, 9 Jul 2024 05:31:21 -0700 From: Itamar Gozlan To: , , , , , , , , Dariusz Sosnowski , Bing Zhao , Ori Kam , Matan Azrad CC: , Subject: [PATCH 3/8] net/mlx5/hws: strictly range templates check fix Date: Tue, 9 Jul 2024 15:30:58 +0300 Message-ID: <20240709123103.2101902-4-igozlan@nvidia.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240709123103.2101902-1-igozlan@nvidia.com> References: <20240707102532.2045942-10-igozlan@nvidia.com> <20240709123103.2101902-1-igozlan@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055DE:EE_|DS0PR12MB8788:EE_ X-MS-Office365-Filtering-Correlation-Id: 9fd7de52-f55e-42ad-1b04-08dca013200d X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|36860700013|82310400026|921020; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2024 12:31:58.0289 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fd7de52-f55e-42ad-1b04-08dca013200d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DE.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8788 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Using range and non range templates is not allowed, and in HWS there is a check that enforce that limitation with constantly check that, in a loop, if the current template defined as range, the last one should also be defined as range. But, in the case where there are two templates in the following order: (1) template with range, and (2) template without range. The existing checks will not cover this case. This commit fixes that hole by maintain the invariant that if a template without a range exist, all the previous match template are also. Fixes: 9732ffe13bd6 ("net/mlx5/hws: add range definer creation") Cc: valex@nvidia.com Cc: stable@dpdk.org Signed-off-by: Itamar Gozlan Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr_definer.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 9ebda9267d..51a3f7be4b 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -4041,15 +4041,18 @@ mlx5dr_definer_matcher_range_init(struct mlx5dr_context *ctx, /* Create optional range definers */ for (i = 0; i < matcher->num_of_mt; i++) { - if (!mt[i].fcr_sz) - continue; - /* All must use range if requested */ - if (i && !mt[i - 1].range_definer) { + bool is_range = !!mt[i].fcr_sz; + bool has_range = matcher->flags & MLX5DR_MATCHER_FLAGS_RANGE_DEFINER; + + if (i && ((is_range && !has_range) || (!is_range && has_range))) { DR_LOG(ERR, "Using range and non range templates is not allowed"); goto free_definers; } + if (!mt[i].fcr_sz) + continue; + matcher->flags |= MLX5DR_MATCHER_FLAGS_RANGE_DEFINER; /* Create definer without fcr binding, already binded */ mt[i].range_definer = mlx5dr_definer_alloc(ctx, -- 2.39.3