From: Serhii Iliushyk <sil-plv@napatech.com>
To: dev@dpdk.org
Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com,
andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com
Subject: [PATCH v8 15/21] net/ntnic: add link management skeleton
Date: Fri, 12 Jul 2024 17:47:25 +0200 [thread overview]
Message-ID: <20240712154737.1339646-15-sil-plv@napatech.com> (raw)
In-Reply-To: <20240712154737.1339646-1-sil-plv@napatech.com>
Add functionality to read and control the link-state of the ntnic.
Note that must functions are not implemented yet.
Adds the following eth_dev_ops:
- dev_set_link_up
- dev_set_link_down
- link_update
- mac_addr_add
- mac_addr_set
- set_mc_addr_list
- promiscuous_enable
Signed-off-by: Serhii Iliushyk <sil-plv@napatech.com>
---
v5
* Fix Typo/Spelling
v6
* if_index was replaced with n_intf_no
* MAC addr assignment approach was reworked
v7
* Add relate features to documentation - INI and RST files
---
doc/guides/nics/features/ntnic.ini | 3 +
doc/guides/nics/ntnic.rst | 5 +
drivers/net/ntnic/adapter/nt4ga_adapter.c | 6 +
drivers/net/ntnic/include/nt4ga_adapter.h | 5 +-
drivers/net/ntnic/include/nt4ga_link.h | 84 +++++++
drivers/net/ntnic/include/ntos_drv.h | 15 ++
drivers/net/ntnic/link_mgmt/nt4ga_link.c | 176 ++++++++++++++
drivers/net/ntnic/meson.build | 1 +
drivers/net/ntnic/ntnic_ethdev.c | 283 +++++++++++++++++++++-
drivers/net/ntnic/ntnic_mod_reg.c | 14 ++
drivers/net/ntnic/ntnic_mod_reg.h | 50 +++-
drivers/net/ntnic/ntutil/nt_util.c | 131 ++++++++++
drivers/net/ntnic/ntutil/nt_util.h | 11 +
13 files changed, 780 insertions(+), 4 deletions(-)
create mode 100644 drivers/net/ntnic/include/nt4ga_link.h
create mode 100644 drivers/net/ntnic/link_mgmt/nt4ga_link.c
diff --git a/doc/guides/nics/features/ntnic.ini b/doc/guides/nics/features/ntnic.ini
index 03f4d5aac8..0a74817fcf 100644
--- a/doc/guides/nics/features/ntnic.ini
+++ b/doc/guides/nics/features/ntnic.ini
@@ -5,5 +5,8 @@
;
[Features]
FW version = Y
+Speed capabilities = Y
+Unicast MAC filter = Y
+Multicast MAC filter = Y
Linux = Y
x86-64 = Y
diff --git a/doc/guides/nics/ntnic.rst b/doc/guides/nics/ntnic.rst
index 43caf3151d..25c74730fe 100644
--- a/doc/guides/nics/ntnic.rst
+++ b/doc/guides/nics/ntnic.rst
@@ -33,6 +33,11 @@ Features
--------
- FW version
+- Speed capabilities
+- Link status (Link update only)
+- Unicast MAC filter
+- Multicast MAC filter
+- Promiscuous mode (Enable only. The device always run promiscuous mode)
Limitations
~~~~~~~~~~~
diff --git a/drivers/net/ntnic/adapter/nt4ga_adapter.c b/drivers/net/ntnic/adapter/nt4ga_adapter.c
index bdad2b1e21..e29fda7fbb 100644
--- a/drivers/net/ntnic/adapter/nt4ga_adapter.c
+++ b/drivers/net/ntnic/adapter/nt4ga_adapter.c
@@ -124,8 +124,14 @@ static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info)
assert(n_phy_ports >= 1);
{
+ int i;
assert(fpga_info->n_fpga_prod_id > 0);
+ for (i = 0; i < NUM_ADAPTER_PORTS_MAX; i++) {
+ /* Disable all ports. Must be enabled later */
+ p_adapter_info->nt4ga_link.port_action[i].port_disable = true;
+ }
+
switch (fpga_info->n_fpga_prod_id) {
/* NT200A01: 2x100G (Xilinx) */
case 9563: /* NT200A02 (Cap) */
diff --git a/drivers/net/ntnic/include/nt4ga_adapter.h b/drivers/net/ntnic/include/nt4ga_adapter.h
index 2c72583caf..ed14936b38 100644
--- a/drivers/net/ntnic/include/nt4ga_adapter.h
+++ b/drivers/net/ntnic/include/nt4ga_adapter.h
@@ -6,7 +6,8 @@
#ifndef _NT4GA_ADAPTER_H_
#define _NT4GA_ADAPTER_H_
-#include "ntos_drv.h"
+#include "nt4ga_link.h"
+
typedef struct hw_info_s {
/* pciids */
uint16_t pci_vendor_id;
@@ -23,6 +24,8 @@ typedef struct hw_info_s {
} hw_info_t;
typedef struct adapter_info_s {
+ struct nt4ga_link_s nt4ga_link;
+
struct hw_info_s hw_info;
struct fpga_info_s fpga_info;
diff --git a/drivers/net/ntnic/include/nt4ga_link.h b/drivers/net/ntnic/include/nt4ga_link.h
new file mode 100644
index 0000000000..849261ce3a
--- /dev/null
+++ b/drivers/net/ntnic/include/nt4ga_link.h
@@ -0,0 +1,84 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef NT4GA_LINK_H_
+#define NT4GA_LINK_H_
+
+#include "ntos_drv.h"
+
+enum nt_link_state_e {
+ NT_LINK_STATE_UNKNOWN = 0, /* The link state has not been read yet */
+ NT_LINK_STATE_DOWN = 1, /* The link state is DOWN */
+ NT_LINK_STATE_UP = 2, /* The link state is UP */
+ NT_LINK_STATE_ERROR = 3 /* The link state could not be read */
+};
+
+typedef enum nt_link_state_e nt_link_state_t, *nt_link_state_p;
+
+enum nt_link_duplex_e {
+ NT_LINK_DUPLEX_UNKNOWN = 0,
+ NT_LINK_DUPLEX_HALF = 0x01, /* Half duplex */
+ NT_LINK_DUPLEX_FULL = 0x02, /* Full duplex */
+};
+
+typedef enum nt_link_duplex_e nt_link_duplex_t;
+
+enum nt_link_loopback_e {
+ NT_LINK_LOOPBACK_OFF = 0,
+ NT_LINK_LOOPBACK_HOST = 0x01, /* Host loopback mode */
+ NT_LINK_LOOPBACK_LINE = 0x02, /* Line loopback mode */
+};
+
+enum nt_link_auto_neg_e {
+ NT_LINK_AUTONEG_NA = 0,
+ NT_LINK_AUTONEG_MANUAL = 0x01,
+ NT_LINK_AUTONEG_OFF = NT_LINK_AUTONEG_MANUAL, /* Auto negotiation OFF */
+ NT_LINK_AUTONEG_AUTO = 0x02,
+ NT_LINK_AUTONEG_ON = NT_LINK_AUTONEG_AUTO, /* Auto negotiation ON */
+};
+
+typedef struct link_state_s {
+ bool link_disabled;
+ bool link_up;
+ enum nt_link_state_e link_state;
+ enum nt_link_state_e link_state_latched;
+} link_state_t;
+
+enum nt_link_speed_e {
+ NT_LINK_SPEED_UNKNOWN = 0,
+ NT_LINK_SPEED_10M = 0x01, /* 10 Mbps */
+ NT_LINK_SPEED_100M = 0x02, /* 100 Mbps */
+ NT_LINK_SPEED_1G = 0x04,/* 1 Gbps (Autoneg only) */
+ NT_LINK_SPEED_10G = 0x08, /* 10 Gbps (Autoneg only) */
+ NT_LINK_SPEED_40G = 0x10, /* 40 Gbps (Autoneg only) */
+ NT_LINK_SPEED_100G = 0x20, /* 100 Gbps (Autoneg only) */
+ NT_LINK_SPEED_50G = 0x40, /* 50 Gbps (Autoneg only) */
+ NT_LINK_SPEED_25G = 0x80, /* 25 Gbps (Autoneg only) */
+ NT_LINK_SPEED_END /* always keep this entry as the last in enum */
+};
+typedef enum nt_link_speed_e nt_link_speed_t;
+
+typedef struct link_info_s {
+ enum nt_link_speed_e link_speed;
+ enum nt_link_duplex_e link_duplex;
+ enum nt_link_auto_neg_e link_auto_neg;
+} link_info_t;
+
+typedef struct port_action_s {
+ bool port_disable;
+ enum nt_link_speed_e port_speed;
+ enum nt_link_duplex_e port_duplex;
+ uint32_t port_lpbk_mode;
+} port_action_t;
+
+typedef struct nt4ga_link_s {
+ link_state_t link_state[NUM_ADAPTER_PORTS_MAX];
+ link_info_t link_info[NUM_ADAPTER_PORTS_MAX];
+ port_action_t port_action[NUM_ADAPTER_PORTS_MAX];
+ uint32_t speed_capa;
+ bool variables_initialized;
+} nt4ga_link_t;
+
+#endif /* NT4GA_LINK_H_ */
diff --git a/drivers/net/ntnic/include/ntos_drv.h b/drivers/net/ntnic/include/ntos_drv.h
index e3d8ffb91c..43fac61257 100644
--- a/drivers/net/ntnic/include/ntos_drv.h
+++ b/drivers/net/ntnic/include/ntos_drv.h
@@ -25,9 +25,24 @@ struct pmd_internals {
const struct rte_pci_device *pci_dev;
char name[20];
int n_intf_no;
+ int lpbk_mode;
+ uint8_t ts_multiplier;
+ uint16_t min_tx_pkt_size;
+ uint16_t max_tx_pkt_size;
+ unsigned int nb_rx_queues;
+ unsigned int nb_tx_queues;
uint32_t port;
uint32_t port_id;
+ /* Offset of the VF from the PF */
+ uint8_t vf_offset;
+ nt_meta_port_type_t type;
+ /* if a virtual port type - the vhid */
+ int vhid;
struct drv_s *p_drv;
+ /* Ethernet (MAC) addresses. Element number zero denotes default address. */
+ struct rte_ether_addr eth_addrs[NUM_MAC_ADDRS_PER_PORT];
+ /* Multicast ethernet (MAC) addresses. */
+ struct rte_ether_addr mc_addrs[NUM_MULTICAST_ADDRS_PER_PORT];
struct pmd_internals *next;
};
diff --git a/drivers/net/ntnic/link_mgmt/nt4ga_link.c b/drivers/net/ntnic/link_mgmt/nt4ga_link.c
new file mode 100644
index 0000000000..ad23046aae
--- /dev/null
+++ b/drivers/net/ntnic/link_mgmt/nt4ga_link.c
@@ -0,0 +1,176 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <inttypes.h>
+
+#include "ntlog.h"
+#include "ntnic_mod_reg.h"
+
+#include "nt4ga_link.h"
+
+/*
+ * port: speed capabilities
+ * This is actually an adapter capability mapped onto every port
+ */
+static uint32_t nt4ga_port_get_link_speed_capabilities(struct adapter_info_s *p, int port)
+{
+ (void)p;
+ (void)port;
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ const uint32_t nt_link_speed_capa = p_link->speed_capa;
+ return nt_link_speed_capa;
+}
+
+/*
+ * port: link mode
+ */
+static void nt4ga_port_set_adm_state(struct adapter_info_s *p, int port, bool adm_state)
+{
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ p_link->port_action[port].port_disable = !adm_state;
+}
+
+static bool nt4ga_port_get_adm_state(struct adapter_info_s *p, int port)
+{
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ const bool adm_state = !p_link->port_action[port].port_disable;
+ return adm_state;
+}
+
+/*
+ * port: link status
+ */
+static void nt4ga_port_set_link_status(struct adapter_info_s *p, int port, bool link_status)
+{
+ /* Setting link state/status is (currently) the same as controlling the port adm state */
+ nt4ga_port_set_adm_state(p, port, link_status);
+}
+
+static bool nt4ga_port_get_link_status(struct adapter_info_s *p, int port)
+{
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ bool status = p_link->link_state[port].link_up;
+ return status;
+}
+
+/*
+ * port: link speed
+ */
+static void nt4ga_port_set_link_speed(struct adapter_info_s *p, int port, nt_link_speed_t speed)
+{
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ p_link->port_action[port].port_speed = speed;
+ p_link->link_info[port].link_speed = speed;
+}
+
+static nt_link_speed_t nt4ga_port_get_link_speed(struct adapter_info_s *p, int port)
+{
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ nt_link_speed_t speed = p_link->link_info[port].link_speed;
+ return speed;
+}
+
+/*
+ * port: link autoneg
+ * Currently not fully supported by link code
+ */
+static void nt4ga_port_set_link_autoneg(struct adapter_info_s *p, int port, bool autoneg)
+{
+ (void)p;
+ (void)port;
+ (void)autoneg;
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ (void)p_link;
+}
+
+static bool nt4ga_port_get_link_autoneg(struct adapter_info_s *p, int port)
+{
+ (void)p;
+ (void)port;
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ (void)p_link;
+ return true;
+}
+
+/*
+ * port: link duplex
+ * Currently not fully supported by link code
+ */
+static void nt4ga_port_set_link_duplex(struct adapter_info_s *p, int port, nt_link_duplex_t duplex)
+{
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ p_link->port_action[port].port_duplex = duplex;
+}
+
+static nt_link_duplex_t nt4ga_port_get_link_duplex(struct adapter_info_s *p, int port)
+{
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ nt_link_duplex_t duplex = p_link->link_info[port].link_duplex;
+ return duplex;
+}
+
+/*
+ * port: loopback mode
+ */
+static void nt4ga_port_set_loopback_mode(struct adapter_info_s *p, int port, uint32_t mode)
+{
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ p_link->port_action[port].port_lpbk_mode = mode;
+}
+
+static uint32_t nt4ga_port_get_loopback_mode(struct adapter_info_s *p, int port)
+{
+ nt4ga_link_t *const p_link = &p->nt4ga_link;
+ return p_link->port_action[port].port_lpbk_mode;
+}
+
+
+static const struct port_ops ops = {
+ /*
+ * port:s link mode
+ */
+ .set_adm_state = nt4ga_port_set_adm_state,
+ .get_adm_state = nt4ga_port_get_adm_state,
+
+ /*
+ * port:s link status
+ */
+ .set_link_status = nt4ga_port_set_link_status,
+ .get_link_status = nt4ga_port_get_link_status,
+
+ /*
+ * port: link autoneg
+ */
+ .set_link_autoneg = nt4ga_port_set_link_autoneg,
+ .get_link_autoneg = nt4ga_port_get_link_autoneg,
+
+ /*
+ * port: link speed
+ */
+ .set_link_speed = nt4ga_port_set_link_speed,
+ .get_link_speed = nt4ga_port_get_link_speed,
+
+ /*
+ * port: link duplex
+ */
+ .set_link_duplex = nt4ga_port_set_link_duplex,
+ .get_link_duplex = nt4ga_port_get_link_duplex,
+
+ /*
+ * port: loopback mode
+ */
+ .set_loopback_mode = nt4ga_port_set_loopback_mode,
+ .get_loopback_mode = nt4ga_port_get_loopback_mode,
+
+ .get_link_speed_capabilities = nt4ga_port_get_link_speed_capabilities,
+};
+
+void port_init(void)
+{
+ register_port_ops(&ops);
+}
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 987768cb92..001c75963e 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -22,6 +22,7 @@ includes = [
# all sources
sources = files(
'adapter/nt4ga_adapter.c',
+ 'link_mgmt/nt4ga_link.c',
'nthw/supported/nthw_fpga_9563_055_039_0000.c',
'nthw/supported/nthw_fpga_instances.c',
'nthw/supported/nthw_fpga_mod_str_map.c',
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index 488c88c782..c53f0dd108 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -23,6 +23,9 @@
#include "ntnic_mod_reg.h"
#include "nt_util.h"
+#define HW_MAX_PKT_LEN (10000)
+#define MAX_MTU (HW_MAX_PKT_LEN - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN)
+
#define EXCEPTION_PATH_HID 0
static const struct rte_pci_id nthw_pci_id_map[] = {
@@ -90,13 +93,134 @@ get_pdrv_from_pci(struct rte_pci_addr addr)
return p_drv;
}
+static int
+eth_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete __rte_unused)
+{
+ const struct port_ops *port_ops = get_port_ops();
+
+ if (port_ops == NULL) {
+ NT_LOG(ERR, NTNIC, "Link management module uninitialized\n");
+ return -1;
+ }
+
+ struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+
+ const int n_intf_no = internals->n_intf_no;
+ struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info;
+
+ if (eth_dev->data->dev_started) {
+ const bool port_link_status = port_ops->get_link_status(p_adapter_info, n_intf_no);
+ eth_dev->data->dev_link.link_status =
+ port_link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
+
+ nt_link_speed_t port_link_speed =
+ port_ops->get_link_speed(p_adapter_info, n_intf_no);
+ eth_dev->data->dev_link.link_speed =
+ nt_link_speed_to_eth_speed_num(port_link_speed);
+
+ nt_link_duplex_t nt_link_duplex =
+ port_ops->get_link_duplex(p_adapter_info, n_intf_no);
+ eth_dev->data->dev_link.link_duplex = nt_link_duplex_to_eth_duplex(nt_link_duplex);
+
+ } else {
+ eth_dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN;
+ eth_dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
+ eth_dev->data->dev_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+ }
+
+ return 0;
+}
+
static int
eth_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *dev_info)
{
+ const struct port_ops *port_ops = get_port_ops();
+
+ if (port_ops == NULL) {
+ NT_LOG(ERR, NTNIC, "Link management module uninitialized\n");
+ return -1;
+ }
+
struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+ const int n_intf_no = internals->n_intf_no;
+ struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info;
+
dev_info->if_index = internals->n_intf_no;
dev_info->driver_name = internals->name;
+ dev_info->max_mac_addrs = NUM_MAC_ADDRS_PER_PORT;
+ dev_info->max_rx_pktlen = HW_MAX_PKT_LEN;
+ dev_info->max_mtu = MAX_MTU;
+
+ if (internals->p_drv) {
+ dev_info->max_rx_queues = internals->nb_rx_queues;
+ dev_info->max_tx_queues = internals->nb_tx_queues;
+
+ dev_info->min_rx_bufsize = 64;
+
+ const uint32_t nt_port_speed_capa =
+ port_ops->get_link_speed_capabilities(p_adapter_info, n_intf_no);
+ dev_info->speed_capa = nt_link_speed_capa_to_eth_speed_capa(nt_port_speed_capa);
+ }
+
+ return 0;
+}
+
+static int
+eth_mac_addr_add(struct rte_eth_dev *eth_dev,
+ struct rte_ether_addr *mac_addr,
+ uint32_t index,
+ uint32_t vmdq __rte_unused)
+{
+ struct rte_ether_addr *const eth_addrs = eth_dev->data->mac_addrs;
+
+ assert(index < NUM_MAC_ADDRS_PER_PORT);
+
+ if (index >= NUM_MAC_ADDRS_PER_PORT) {
+ const struct pmd_internals *const internals =
+ (struct pmd_internals *)eth_dev->data->dev_private;
+ NT_LOG_DBGX(DEBUG, NTNIC, "Port %i: illegal index %u (>= %u)\n",
+ internals->n_intf_no, index, NUM_MAC_ADDRS_PER_PORT);
+ return -1;
+ }
+
+ eth_addrs[index] = *mac_addr;
+
+ return 0;
+}
+
+static int
+eth_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
+{
+ struct rte_ether_addr *const eth_addrs = dev->data->mac_addrs;
+
+ eth_addrs[0U] = *mac_addr;
+
+ return 0;
+}
+
+static int
+eth_set_mc_addr_list(struct rte_eth_dev *eth_dev,
+ struct rte_ether_addr *mc_addr_set,
+ uint32_t nb_mc_addr)
+{
+ struct pmd_internals *const internals = (struct pmd_internals *)eth_dev->data->dev_private;
+ struct rte_ether_addr *const mc_addrs = internals->mc_addrs;
+ size_t i;
+
+ if (nb_mc_addr >= NUM_MULTICAST_ADDRS_PER_PORT) {
+ NT_LOG_DBGX(DEBUG, NTNIC,
+ "Port %i: too many multicast addresses %u (>= %u)\n",
+ internals->n_intf_no, nb_mc_addr, NUM_MULTICAST_ADDRS_PER_PORT);
+ return -1;
+ }
+
+ for (i = 0U; i < NUM_MULTICAST_ADDRS_PER_PORT; i++)
+ if (i < nb_mc_addr)
+ mc_addrs[i] = mc_addr_set[i];
+
+ else
+ (void)memset(&mc_addrs[i], 0, sizeof(mc_addrs[i]));
return 0;
}
@@ -114,10 +238,59 @@ eth_dev_configure(struct rte_eth_dev *eth_dev)
static int
eth_dev_start(struct rte_eth_dev *eth_dev)
{
+ const struct port_ops *port_ops = get_port_ops();
+
+ if (port_ops == NULL) {
+ NT_LOG(ERR, NTNIC, "Link management module uninitialized\n");
+ return -1;
+ }
+
struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+ const int n_intf_no = internals->n_intf_no;
+ struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info;
+
NT_LOG_DBGX(DEBUG, NTNIC, "Port %u\n", internals->n_intf_no);
+ if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE) {
+ eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP;
+
+ } else {
+ /* Enable the port */
+ port_ops->set_adm_state(p_adapter_info, internals->n_intf_no, true);
+
+ /*
+ * wait for link on port
+ * If application starts sending too soon before FPGA port is ready, garbage is
+ * produced
+ */
+ int loop = 0;
+
+ while (port_ops->get_link_status(p_adapter_info, n_intf_no) == RTE_ETH_LINK_DOWN) {
+ /* break out after 5 sec */
+ if (++loop >= 50) {
+ NT_LOG_DBGX(DEBUG, NTNIC,
+ "TIMEOUT No link on port %i (5sec timeout)\n",
+ internals->n_intf_no);
+ break;
+ }
+
+ nt_os_wait_usec(100 * 1000);
+ }
+
+ if (internals->lpbk_mode) {
+ if (internals->lpbk_mode & 1 << 0) {
+ port_ops->set_loopback_mode(p_adapter_info, n_intf_no,
+ NT_LINK_LOOPBACK_HOST);
+ }
+
+ if (internals->lpbk_mode & 1 << 1) {
+ port_ops->set_loopback_mode(p_adapter_info, n_intf_no,
+ NT_LINK_LOOPBACK_LINE);
+ }
+ }
+ }
+
return 0;
}
@@ -126,13 +299,65 @@ eth_dev_stop(struct rte_eth_dev *eth_dev)
{
struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
- NT_LOG_DBGX(DEBUG, NTNIC, "Port %u, %u\n",
- internals->n_intf_no, internals->n_intf_no);
+ NT_LOG_DBGX(DEBUG, NTNIC, "Port %u, type %u\n",
+ internals->n_intf_no, internals->type);
eth_dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN;
return 0;
}
+static int
+eth_dev_set_link_up(struct rte_eth_dev *eth_dev)
+{
+ const struct port_ops *port_ops = get_port_ops();
+
+ if (port_ops == NULL) {
+ NT_LOG(ERR, NTNIC, "Link management module uninitialized\n");
+ return -1;
+ }
+
+ struct pmd_internals *const internals = (struct pmd_internals *)eth_dev->data->dev_private;
+
+ struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info;
+ const int port = internals->n_intf_no;
+
+ if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE)
+ return 0;
+
+ assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX);
+ assert(port == internals->n_intf_no);
+
+ port_ops->set_adm_state(p_adapter_info, port, true);
+
+ return 0;
+}
+
+static int
+eth_dev_set_link_down(struct rte_eth_dev *eth_dev)
+{
+ const struct port_ops *port_ops = get_port_ops();
+
+ if (port_ops == NULL) {
+ NT_LOG(ERR, NTNIC, "Link management module uninitialized\n");
+ return -1;
+ }
+
+ struct pmd_internals *const internals = (struct pmd_internals *)eth_dev->data->dev_private;
+
+ struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info;
+ const int port = internals->n_intf_no;
+
+ if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE)
+ return 0;
+
+ assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX);
+ assert(port == internals->n_intf_no);
+
+ port_ops->set_link_status(p_adapter_info, port, false);
+
+ return 0;
+}
+
static void
drv_deinit(struct drv_s *p_drv)
{
@@ -184,6 +409,9 @@ eth_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, size_t fw_size
{
struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private;
+ if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE)
+ return 0;
+
fpga_info_t *fpga_info = &internals->p_drv->ntdrv.adapter_info.fpga_info;
const int length = snprintf(fw_version, fw_size, "%03d-%04d-%02d-%02d",
fpga_info->n_fpga_type_id, fpga_info->n_fpga_prod_id,
@@ -199,19 +427,39 @@ eth_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, size_t fw_size
}
}
+static int
+promiscuous_enable(struct rte_eth_dev __rte_unused(*dev))
+{
+ NT_LOG(DBG, NTHW, "The device always run promiscuous mode.");
+ return 0;
+}
+
static struct eth_dev_ops nthw_eth_dev_ops = {
.dev_configure = eth_dev_configure,
.dev_start = eth_dev_start,
.dev_stop = eth_dev_stop,
+ .dev_set_link_up = eth_dev_set_link_up,
+ .dev_set_link_down = eth_dev_set_link_down,
.dev_close = eth_dev_close,
+ .link_update = eth_link_update,
.dev_infos_get = eth_dev_infos_get,
.fw_version_get = eth_fw_version_get,
+ .mac_addr_add = eth_mac_addr_add,
+ .mac_addr_set = eth_mac_addr_set,
+ .set_mc_addr_list = eth_set_mc_addr_list,
+ .promiscuous_enable = promiscuous_enable,
};
static int
nthw_pci_dev_init(struct rte_pci_device *pci_dev)
{
nt_vfio_init();
+ const struct port_ops *port_ops = get_port_ops();
+
+ if (port_ops == NULL) {
+ NT_LOG(ERR, NTNIC, "Link management module uninitialized\n");
+ return -1;
+ }
const struct adapter_ops *adapter_ops = get_adapter_ops();
@@ -229,6 +477,8 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev)
uint32_t nb_rx_queues = 1;
uint32_t nb_tx_queues = 1;
int n_phy_ports;
+ struct port_link_speed pls_mbps[NUM_ADAPTER_PORTS_MAX] = { 0 };
+ int num_port_speeds = 0;
NT_LOG_DBGX(DEBUG, NTNIC, "Dev %s PF #%i Init : %02x:%02x:%i\n", pci_dev->name,
pci_dev->addr.function, pci_dev->addr.bus, pci_dev->addr.devid,
pci_dev->addr.function);
@@ -291,6 +541,12 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev)
p_nt_drv->b_shutdown = false;
p_nt_drv->adapter_info.pb_shutdown = &p_nt_drv->b_shutdown;
+ for (int i = 0; i < num_port_speeds; ++i) {
+ struct adapter_info_s *p_adapter_info = &p_nt_drv->adapter_info;
+ nt_link_speed_t link_speed = convert_link_speed(pls_mbps[i].link_speed);
+ port_ops->set_link_speed(p_adapter_info, i, link_speed);
+ }
+
/* store context */
store_pdrv(p_drv);
@@ -355,6 +611,13 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev)
internals->pci_dev = pci_dev;
internals->n_intf_no = n_intf_no;
+ internals->min_tx_pkt_size = 64;
+ internals->max_tx_pkt_size = 10000;
+ internals->type = PORT_TYPE_PHYSICAL;
+ internals->vhid = -1;
+ internals->nb_rx_queues = nb_rx_queues;
+ internals->nb_tx_queues = nb_tx_queues;
+
/* Setup queue_ids */
if (nb_rx_queues > 1) {
@@ -369,6 +632,18 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev)
0 /*port*/, nb_tx_queues);
}
+ /* Set MAC address (but only if the MAC address is permitted) */
+ if (n_intf_no < fpga_info->nthw_hw_info.vpd_info.mn_mac_addr_count) {
+ const uint64_t mac =
+ fpga_info->nthw_hw_info.vpd_info.mn_mac_addr_value + n_intf_no;
+ internals->eth_addrs[0].addr_bytes[0] = (mac >> 40) & 0xFFu;
+ internals->eth_addrs[0].addr_bytes[1] = (mac >> 32) & 0xFFu;
+ internals->eth_addrs[0].addr_bytes[2] = (mac >> 24) & 0xFFu;
+ internals->eth_addrs[0].addr_bytes[3] = (mac >> 16) & 0xFFu;
+ internals->eth_addrs[0].addr_bytes[4] = (mac >> 8) & 0xFFu;
+ internals->eth_addrs[0].addr_bytes[5] = (mac >> 0) & 0xFFu;
+ }
+
eth_dev = rte_eth_dev_allocate(name);
if (!eth_dev) {
@@ -383,6 +658,10 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev)
/* connect structs */
internals->p_drv = p_drv;
eth_dev->data->dev_private = internals;
+ eth_dev->data->mac_addrs = rte_malloc(NULL,
+ NUM_MAC_ADDRS_PER_PORT * sizeof(struct rte_ether_addr), 0);
+ rte_memcpy(ð_dev->data->mac_addrs[0],
+ &internals->eth_addrs[0], RTE_ETHER_ADDR_LEN);
internals->port_id = eth_dev->data->port_id;
diff --git a/drivers/net/ntnic/ntnic_mod_reg.c b/drivers/net/ntnic/ntnic_mod_reg.c
index 3f03299a83..b79929c696 100644
--- a/drivers/net/ntnic/ntnic_mod_reg.c
+++ b/drivers/net/ntnic/ntnic_mod_reg.c
@@ -5,6 +5,20 @@
#include "ntnic_mod_reg.h"
+static const struct port_ops *port_ops;
+
+void register_port_ops(const struct port_ops *ops)
+{
+ port_ops = ops;
+}
+
+const struct port_ops *get_port_ops(void)
+{
+ if (port_ops == NULL)
+ port_init();
+ return port_ops;
+}
+
static const struct adapter_ops *adapter_ops;
void register_adapter_ops(const struct adapter_ops *ops)
diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h
index 45f5632981..8d1971a9c4 100644
--- a/drivers/net/ntnic/ntnic_mod_reg.h
+++ b/drivers/net/ntnic/ntnic_mod_reg.h
@@ -12,7 +12,55 @@
#include "nthw_drv.h"
#include "nt4ga_adapter.h"
#include "ntnic_nthw_fpga_rst_nt200a0x.h"
-#include "ntos_drv.h"
+
+struct port_ops {
+ /*
+ * port:s link mode
+ */
+ void (*set_adm_state)(struct adapter_info_s *p, int port, bool adm_state);
+ bool (*get_adm_state)(struct adapter_info_s *p, int port);
+
+ /*
+ * port:s link status
+ */
+ void (*set_link_status)(struct adapter_info_s *p, int port, bool status);
+ bool (*get_link_status)(struct adapter_info_s *p, int port);
+
+ /*
+ * port: link autoneg
+ */
+ void (*set_link_autoneg)(struct adapter_info_s *p, int port, bool autoneg);
+ bool (*get_link_autoneg)(struct adapter_info_s *p, int port);
+
+ /*
+ * port: link speed
+ */
+ void (*set_link_speed)(struct adapter_info_s *p, int port, nt_link_speed_t speed);
+ nt_link_speed_t (*get_link_speed)(struct adapter_info_s *p, int port);
+
+ /*
+ * port: link duplex
+ */
+ void (*set_link_duplex)(struct adapter_info_s *p, int port, nt_link_duplex_t duplex);
+ nt_link_duplex_t (*get_link_duplex)(struct adapter_info_s *p, int port);
+
+ /*
+ * port: loopback mode
+ */
+ void (*set_loopback_mode)(struct adapter_info_s *p, int port, uint32_t mode);
+ uint32_t (*get_loopback_mode)(struct adapter_info_s *p, int port);
+
+ uint32_t (*get_link_speed_capabilities)(struct adapter_info_s *p, int port);
+
+ /*
+ * port: tx power
+ */
+ int (*tx_power)(struct adapter_info_s *p, int port, bool disable);
+};
+
+void register_port_ops(const struct port_ops *ops);
+const struct port_ops *get_port_ops(void);
+void port_init(void);
struct adapter_ops {
int (*init)(struct adapter_info_s *p_adapter_info);
diff --git a/drivers/net/ntnic/ntutil/nt_util.c b/drivers/net/ntnic/ntutil/nt_util.c
index 53c39ef112..9904e3df3b 100644
--- a/drivers/net/ntnic/ntutil/nt_util.c
+++ b/drivers/net/ntnic/ntutil/nt_util.c
@@ -96,3 +96,134 @@ void nt_dma_free(struct nt_dma_s *vfio_addr)
rte_free((void *)(vfio_addr->addr));
rte_free(vfio_addr);
}
+
+/* NOTE: please note the difference between RTE_ETH_SPEED_NUM_xxx and RTE_ETH_LINK_SPEED_xxx */
+int nt_link_speed_to_eth_speed_num(enum nt_link_speed_e nt_link_speed)
+{
+ int eth_speed_num = RTE_ETH_SPEED_NUM_NONE;
+
+ switch (nt_link_speed) {
+ case NT_LINK_SPEED_10M:
+ eth_speed_num = RTE_ETH_SPEED_NUM_10M;
+ break;
+
+ case NT_LINK_SPEED_100M:
+ eth_speed_num = RTE_ETH_SPEED_NUM_100M;
+ break;
+
+ case NT_LINK_SPEED_1G:
+ eth_speed_num = RTE_ETH_SPEED_NUM_1G;
+ break;
+
+ case NT_LINK_SPEED_10G:
+ eth_speed_num = RTE_ETH_SPEED_NUM_10G;
+ break;
+
+ case NT_LINK_SPEED_25G:
+ eth_speed_num = RTE_ETH_SPEED_NUM_25G;
+ break;
+
+ case NT_LINK_SPEED_40G:
+ eth_speed_num = RTE_ETH_SPEED_NUM_40G;
+ break;
+
+ case NT_LINK_SPEED_50G:
+ eth_speed_num = RTE_ETH_SPEED_NUM_50G;
+ break;
+
+ case NT_LINK_SPEED_100G:
+ eth_speed_num = RTE_ETH_SPEED_NUM_100G;
+ break;
+
+ default:
+ eth_speed_num = RTE_ETH_SPEED_NUM_NONE;
+ break;
+ }
+
+ return eth_speed_num;
+}
+
+uint32_t nt_link_speed_capa_to_eth_speed_capa(int nt_link_speed_capa)
+{
+ uint32_t eth_speed_capa = 0;
+
+ if (nt_link_speed_capa & NT_LINK_SPEED_10M)
+ eth_speed_capa |= RTE_ETH_LINK_SPEED_10M;
+
+ if (nt_link_speed_capa & NT_LINK_SPEED_100M)
+ eth_speed_capa |= RTE_ETH_LINK_SPEED_100M;
+
+ if (nt_link_speed_capa & NT_LINK_SPEED_1G)
+ eth_speed_capa |= RTE_ETH_LINK_SPEED_1G;
+
+ if (nt_link_speed_capa & NT_LINK_SPEED_10G)
+ eth_speed_capa |= RTE_ETH_LINK_SPEED_10G;
+
+ if (nt_link_speed_capa & NT_LINK_SPEED_25G)
+ eth_speed_capa |= RTE_ETH_LINK_SPEED_25G;
+
+ if (nt_link_speed_capa & NT_LINK_SPEED_40G)
+ eth_speed_capa |= RTE_ETH_LINK_SPEED_40G;
+
+ if (nt_link_speed_capa & NT_LINK_SPEED_50G)
+ eth_speed_capa |= RTE_ETH_LINK_SPEED_50G;
+
+ if (nt_link_speed_capa & NT_LINK_SPEED_100G)
+ eth_speed_capa |= RTE_ETH_LINK_SPEED_100G;
+
+ return eth_speed_capa;
+}
+
+/* Converts link speed provided in Mbps to NT specific definitions.*/
+nt_link_speed_t convert_link_speed(int link_speed_mbps)
+{
+ switch (link_speed_mbps) {
+ case 10:
+ return NT_LINK_SPEED_10M;
+
+ case 100:
+ return NT_LINK_SPEED_100M;
+
+ case 1000:
+ return NT_LINK_SPEED_1G;
+
+ case 10000:
+ return NT_LINK_SPEED_10G;
+
+ case 40000:
+ return NT_LINK_SPEED_40G;
+
+ case 100000:
+ return NT_LINK_SPEED_100G;
+
+ case 50000:
+ return NT_LINK_SPEED_50G;
+
+ case 25000:
+ return NT_LINK_SPEED_25G;
+
+ default:
+ return NT_LINK_SPEED_UNKNOWN;
+ }
+}
+
+int nt_link_duplex_to_eth_duplex(enum nt_link_duplex_e nt_link_duplex)
+{
+ int eth_link_duplex = 0;
+
+ switch (nt_link_duplex) {
+ case NT_LINK_DUPLEX_FULL:
+ eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+ break;
+
+ case NT_LINK_DUPLEX_HALF:
+ eth_link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
+ break;
+
+ case NT_LINK_DUPLEX_UNKNOWN: /* fall-through */
+ default:
+ break;
+ }
+
+ return eth_link_duplex;
+}
diff --git a/drivers/net/ntnic/ntutil/nt_util.h b/drivers/net/ntnic/ntutil/nt_util.h
index 6dfd7428e1..ea91181a06 100644
--- a/drivers/net/ntnic/ntutil/nt_util.h
+++ b/drivers/net/ntnic/ntutil/nt_util.h
@@ -7,6 +7,7 @@
#define NTOSS_SYSTEM_NT_UTIL_H
#include <stdint.h>
+#include "nt4ga_link.h"
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(arr) RTE_DIM(arr)
@@ -30,6 +31,11 @@ struct nt_dma_s {
uint64_t size;
};
+struct port_link_speed {
+ int port_id;
+ int link_speed;
+};
+
struct nt_dma_s *nt_dma_alloc(uint64_t size, uint64_t align, int numa);
void nt_dma_free(struct nt_dma_s *vfio_addr);
@@ -40,4 +46,9 @@ struct nt_util_vfio_impl {
void nt_util_vfio_init(struct nt_util_vfio_impl *impl);
+int nt_link_speed_to_eth_speed_num(enum nt_link_speed_e nt_link_speed);
+uint32_t nt_link_speed_capa_to_eth_speed_capa(int nt_link_speed_capa);
+nt_link_speed_t convert_link_speed(int link_speed_mbps);
+int nt_link_duplex_to_eth_duplex(enum nt_link_duplex_e nt_link_duplex);
+
#endif /* NTOSS_SYSTEM_NT_UTIL_H */
--
2.45.0
next prev parent reply other threads:[~2024-07-12 15:49 UTC|newest]
Thread overview: 238+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-30 14:48 [PATCH v1 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
2024-05-30 14:48 ` [PATCH v1 02/17] net/ntnic: add core platform functionality Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 03/17] net/ntnic: add interfaces for " Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 04/17] net/ntnic: add FPGA model implementation Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 05/17] net/ntnic: add NTNIC adapter interfaces Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 06/17] net/ntnic: add interfaces for PMD driver modules Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 07/17] net/ntnic: add API " Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 08/17] net/ntnic: add interfaces for flow API engine Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 09/17] net/ntnic: add VFIO module Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 10/17] net/ntnic: add Logs and utilities implementation Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 11/17] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 12/17] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 13/17] net/ntnic: add adapter initialization Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 14/17] net/ntnic: add adapter initialization API Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 15/17] net/ntnic: add link management module Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 16/17] net/ntnic: add link 100G module Serhii Iliushyk
2024-05-30 14:49 ` [PATCH v1 17/17] net/ntnic: add NIM module Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 02/17] net/ntnic: add core platform functionality Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 03/17] net/ntnic: add interfaces for " Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 04/17] net/ntnic: add FPGA model implementation Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 05/17] net/ntnic: add NTNIC adapter interfaces Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 06/17] net/ntnic: add interfaces for PMD driver modules Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 07/17] net/ntnic: add API " Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 08/17] net/ntnic: add interfaces for flow API engine Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 09/17] net/ntnic: add VFIO module Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 10/17] net/ntnic: add Logs and utilities implementation Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 11/17] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 12/17] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 13/17] net/ntnic: add adapter initialization Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 14/17] net/ntnic: add adapter initialization API Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 15/17] net/ntnic: add link management module Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 16/17] net/ntnic: add link 100G module Serhii Iliushyk
2024-05-31 15:47 ` [PATCH v2 17/17] net/ntnic: add NIM module Serhii Iliushyk
2024-06-03 16:17 ` [PATCH v3 01/17] net/ntnic: Add registers for NapaTech SmartNiC Serhii Iliushyk
2024-06-03 16:17 ` [PATCH v3 02/17] net/ntnic: add core platform functionality Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 03/17] net/ntnic: add interfaces for " Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 04/17] net/ntnic: add FPGA model implementation Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 05/17] net/ntnic: add NTNIC adapter interfaces Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 06/17] net/ntnic: add interfaces for PMD driver modules Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 07/17] net/ntnic: add API " Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 08/17] net/ntnic: add interfaces for flow API engine Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 09/17] net/ntnic: add VFIO module Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 10/17] net/ntnic: add Logs and utilities implementation Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 11/17] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 12/17] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 13/17] net/ntnic: add adapter initialization Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 14/17] net/ntnic: add adapter initialization API Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 15/17] net/ntnic: add link management module Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 16/17] net/ntnic: add link 100G module Serhii Iliushyk
2024-06-03 16:18 ` [PATCH v3 17/17] net/ntnic: add NIM module Serhii Iliushyk
2024-06-04 10:29 ` [PATCH v3 01/17] net/ntnic: Add registers for NapaTech SmartNiC Mykola Kostenok
2024-06-07 13:03 ` Serhii Iliushyk
2024-06-12 8:50 ` Ferruh Yigit
2024-06-12 8:55 ` Ferruh Yigit
2024-06-26 19:55 ` [PATCH v4 01/23] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 02/23] net/ntnic: add logging implementation Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 03/23] net/ntnic: add minimal initialization for PCI device Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 04/23] net/ntnic: add NT utilities implementation Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 05/23] net/ntnic: add VFIO module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 06/23] net/ntnic: add NT NIC driver dependencies Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 07/23] net/ntnic: add core platform functionality Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 08/23] net/ntnic: add adapter initialization Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 09/23] net/ntnic: add registers and FPGA model for NapaTech NIC Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 10/23] net/ntnic: add core platform functionality Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 11/23] net/ntnic: add FPGA initialization functionality Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 12/23] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 13/23] net/ntnic: add reset module for " Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 14/23] net/ntnic: add clock profiles " Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 15/23] net/ntnic: add MAC and packet features Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 16/23] net/ntnic: add link management module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 17/23] net/ntnic: add link 100G module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 18/23] net/ntnic: add NIM module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 19/23] net/ntnic: add QSFP support Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 20/23] net/ntnic: add QSFP28 support Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 21/23] net/ntnic: add GPIO PHY module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 22/23] net/ntnic: add MAC PCS register interface module Serhii Iliushyk
2024-06-26 19:55 ` [PATCH v4 23/23] net/ntnic: add GMF (Generic MAC Feeder) module Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 01/23] net/ntnic: add ethdev and makes PMD available Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 02/23] net/ntnic: add logging implementation Serhii Iliushyk
2024-07-04 22:43 ` Ferruh Yigit
2024-06-27 7:38 ` [PATCH v5 03/23] net/ntnic: add minimal initialization for PCI device Serhii Iliushyk
2024-07-04 22:44 ` Ferruh Yigit
2024-07-10 14:30 ` Serhii Iliushyk
2024-07-10 14:58 ` Ferruh Yigit
2024-06-27 7:38 ` [PATCH v5 04/23] net/ntnic: add NT utilities implementation Serhii Iliushyk
2024-07-04 22:44 ` Ferruh Yigit
2024-06-27 7:38 ` [PATCH v5 05/23] net/ntnic: add VFIO module Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 06/23] net/ntnic: add NT NIC driver dependencies Serhii Iliushyk
2024-07-04 22:46 ` Ferruh Yigit
2024-06-27 7:38 ` [PATCH v5 07/23] net/ntnic: add core platform functionality Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 08/23] net/ntnic: add adapter initialization Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 09/23] net/ntnic: add registers and FPGA model for NapaTech NIC Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 10/23] net/ntnic: add core platform functionality Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 11/23] net/ntnic: add FPGA initialization functionality Serhii Iliushyk
2024-07-04 22:46 ` Ferruh Yigit
2024-06-27 7:38 ` [PATCH v5 12/23] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 13/23] net/ntnic: add reset module for " Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 14/23] net/ntnic: add clock profiles " Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 15/23] net/ntnic: add MAC and packet features Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 16/23] net/ntnic: add link management module Serhii Iliushyk
2024-07-04 22:47 ` Ferruh Yigit
2024-06-27 7:38 ` [PATCH v5 17/23] net/ntnic: add link 100G module Serhii Iliushyk
2024-06-27 7:38 ` [PATCH v5 18/23] net/ntnic: add NIM module Serhii Iliushyk
2024-06-27 7:39 ` [PATCH v5 19/23] net/ntnic: add QSFP support Serhii Iliushyk
2024-06-27 7:39 ` [PATCH v5 20/23] net/ntnic: add QSFP28 support Serhii Iliushyk
2024-06-27 7:39 ` [PATCH v5 21/23] net/ntnic: add GPIO PHY module Serhii Iliushyk
2024-06-27 7:39 ` [PATCH v5 22/23] net/ntnic: add MAC PCS register interface module Serhii Iliushyk
2024-06-27 7:39 ` [PATCH v5 23/23] net/ntnic: add GMF (Generic MAC Feeder) module Serhii Iliushyk
2024-07-04 22:50 ` Ferruh Yigit
2024-07-04 22:43 ` [PATCH v5 01/23] net/ntnic: add ethdev and makes PMD available Ferruh Yigit
2024-07-11 12:07 ` [PATCH v6 01/21] " Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 02/21] net/ntnic: add logging implementation Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 03/21] net/ntnic: add minimal initialization for PCI device Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 04/21] net/ntnic: add NT utilities implementation Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 05/21] net/ntnic: add VFIO module Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 06/21] net/ntnic: add basic eth dev ops to ntnic Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 07/21] net/ntnic: add core platform structures Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 08/21] net/ntnic: add adapter initialization Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 09/21] net/ntnic: add registers and FPGA model for NapaTech NIC Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 10/21] net/ntnic: add FPGA modules for initialization Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 11/21] net/ntnic: add FPGA initialization functionality Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 12/21] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 13/21] net/ntnic: add startup and reset sequence for NT200A0X Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 14/21] net/ntnic: add clock profile for the NT200A0X smartNIC Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 15/21] net/ntnic: add link management skeleton Serhii Iliushyk
[not found] ` <9f13294e-4169-483c-bee4-8ea4c2db8070@amd.com>
2024-07-11 16:51 ` Ferruh Yigit
2024-07-11 12:07 ` [PATCH v6 16/21] net/ntnic: add link 100G module ops Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 17/21] net/ntnic: add generic NIM and I2C modules Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 18/21] net/ntnic: add QSFP support Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 19/21] net/ntnic: add QSFP28 support Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 20/21] net/ntnic: add GPIO communication for NIMs Serhii Iliushyk
2024-07-11 12:07 ` [PATCH v6 21/21] net/ntnic: add physical layer control module Serhii Iliushyk
[not found] ` <3f90331f-9ba9-4590-b83f-dd33f25c92a0@amd.com>
2024-07-11 16:53 ` [PATCH v6 01/21] net/ntnic: add ethdev and makes PMD available Ferruh Yigit
[not found] ` <0bfefc75-c57e-4510-9c9f-15f8fb277718@amd.com>
2024-07-11 16:54 ` Ferruh Yigit
2024-07-12 9:48 ` [PATCH v7 " Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 02/21] net/ntnic: add logging implementation Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 03/21] net/ntnic: add minimal initialization for PCI device Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 04/21] net/ntnic: add NT utilities implementation Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 05/21] net/ntnic: add VFIO module Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 06/21] net/ntnic: add basic eth dev ops to ntnic Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 07/21] net/ntnic: add core platform structures Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 08/21] net/ntnic: add adapter initialization Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 09/21] net/ntnic: add registers and FPGA model for NapaTech NIC Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 10/21] net/ntnic: add FPGA modules for initialization Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 11/21] net/ntnic: add FPGA initialization functionality Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 12/21] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 13/21] net/ntnic: add startup and reset sequence for NT200A0X Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 14/21] net/ntnic: add clock profile for the NT200A0X smartNIC Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 15/21] net/ntnic: add link management skeleton Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 16/21] net/ntnic: add link 100G module ops Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 17/21] net/ntnic: add generic NIM and I2C modules Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 18/21] net/ntnic: add QSFP support Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 19/21] net/ntnic: add QSFP28 support Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 20/21] net/ntnic: add GPIO communication for NIMs Serhii Iliushyk
2024-07-12 9:48 ` [PATCH v7 21/21] net/ntnic: add physical layer control module Serhii Iliushyk
2024-07-12 13:54 ` [PATCH v7 01/21] net/ntnic: add ethdev and makes PMD available Patrick Robb
2024-07-13 2:45 ` zhoumin
2024-07-15 15:39 ` Patrick Robb
2024-07-16 2:36 ` zhoumin
2024-07-17 13:44 ` Patrick Robb
2024-07-19 7:54 ` Ferruh Yigit
2024-07-12 15:47 ` [PATCH v8 " Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 02/21] net/ntnic: add logging implementation Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 03/21] net/ntnic: add minimal initialization for PCI device Serhii Iliushyk
2024-07-13 0:16 ` Ferruh Yigit
2024-07-12 15:47 ` [PATCH v8 04/21] net/ntnic: add NT utilities implementation Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 05/21] net/ntnic: add VFIO module Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 06/21] net/ntnic: add basic eth dev ops to ntnic Serhii Iliushyk
2024-07-13 0:17 ` Ferruh Yigit
2024-07-12 15:47 ` [PATCH v8 07/21] net/ntnic: add core platform structures Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 08/21] net/ntnic: add adapter initialization Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 09/21] net/ntnic: add registers and FPGA model for NapaTech NIC Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 10/21] net/ntnic: add FPGA modules for initialization Serhii Iliushyk
2024-07-13 0:18 ` Ferruh Yigit
2024-07-12 15:47 ` [PATCH v8 11/21] net/ntnic: add FPGA initialization functionality Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 12/21] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 13/21] net/ntnic: add startup and reset sequence for NT200A0X Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 14/21] net/ntnic: add clock profile for the NT200A0X smartNIC Serhii Iliushyk
2024-07-12 15:47 ` Serhii Iliushyk [this message]
2024-07-12 15:47 ` [PATCH v8 16/21] net/ntnic: add link 100G module ops Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 17/21] net/ntnic: add generic NIM and I2C modules Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 18/21] net/ntnic: add QSFP support Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 19/21] net/ntnic: add QSFP28 support Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 20/21] net/ntnic: add GPIO communication for NIMs Serhii Iliushyk
2024-07-12 15:47 ` [PATCH v8 21/21] net/ntnic: add physical layer control module Serhii Iliushyk
2024-07-13 0:15 ` [PATCH v8 01/21] net/ntnic: add ethdev and makes PMD available Ferruh Yigit
2024-07-13 0:21 ` Ferruh Yigit
2024-07-16 12:01 ` [PATCH v9 " Serhii Iliushyk
2024-07-16 12:01 ` [PATCH v9 02/21] net/ntnic: add logging implementation Serhii Iliushyk
2024-07-16 12:01 ` [PATCH v9 03/21] net/ntnic: add minimal initialization for PCI device Serhii Iliushyk
2024-07-16 12:01 ` [PATCH v9 04/21] net/ntnic: add NT utilities implementation Serhii Iliushyk
2024-07-16 12:01 ` [PATCH v9 05/21] net/ntnic: add VFIO module Serhii Iliushyk
2024-07-16 12:01 ` [PATCH v9 06/21] net/ntnic: add basic eth dev ops to ntnic Serhii Iliushyk
2024-07-16 12:01 ` [PATCH v9 07/21] net/ntnic: add core platform structures Serhii Iliushyk
2024-07-16 12:01 ` [PATCH v9 08/21] net/ntnic: add adapter initialization Serhii Iliushyk
2024-07-16 12:01 ` [PATCH v9 09/21] net/ntnic: add registers and FPGA model for NapaTech NIC Serhii Iliushyk
2024-07-16 17:33 ` Ferruh Yigit
2024-07-16 12:01 ` [PATCH v9 10/21] net/ntnic: add FPGA modules for initialization Serhii Iliushyk
2024-07-16 12:02 ` [PATCH v9 11/21] net/ntnic: add FPGA initialization functionality Serhii Iliushyk
2024-07-16 12:02 ` [PATCH v9 12/21] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-07-16 12:02 ` [PATCH v9 13/21] net/ntnic: add startup and reset sequence for NT200A0X Serhii Iliushyk
2024-07-16 12:02 ` [PATCH v9 14/21] net/ntnic: add clock profile for the NT200A0X smartNIC Serhii Iliushyk
2024-07-16 17:33 ` Ferruh Yigit
2024-07-16 12:02 ` [PATCH v9 15/21] net/ntnic: add link management skeleton Serhii Iliushyk
2024-07-16 12:02 ` [PATCH v9 16/21] net/ntnic: add link 100G module ops Serhii Iliushyk
2024-07-16 12:02 ` [PATCH v9 17/21] net/ntnic: add generic NIM and I2C modules Serhii Iliushyk
2024-07-16 12:02 ` [PATCH v9 18/21] net/ntnic: add QSFP support Serhii Iliushyk
2024-07-16 12:02 ` [PATCH v9 19/21] net/ntnic: add QSFP28 support Serhii Iliushyk
2024-07-16 12:02 ` [PATCH v9 20/21] net/ntnic: add GPIO communication for NIMs Serhii Iliushyk
2024-07-16 12:02 ` [PATCH v9 21/21] net/ntnic: add physical layer control module Serhii Iliushyk
2024-07-16 17:33 ` Ferruh Yigit
2024-07-16 17:33 ` [PATCH v9 01/21] net/ntnic: add ethdev and makes PMD available Ferruh Yigit
2024-07-17 13:32 ` [PATCH v10 " Serhii Iliushyk
2024-07-17 13:32 ` [PATCH v10 02/21] net/ntnic: add logging implementation Serhii Iliushyk
2024-07-17 13:32 ` [PATCH v10 03/21] net/ntnic: add minimal initialization for PCI device Serhii Iliushyk
2024-07-17 13:32 ` [PATCH v10 04/21] net/ntnic: add utilities implementation Serhii Iliushyk
2024-07-17 13:32 ` [PATCH v10 05/21] net/ntnic: add VFIO module Serhii Iliushyk
2024-07-17 13:32 ` [PATCH v10 06/21] net/ntnic: add basic eth dev ops Serhii Iliushyk
2024-07-17 13:32 ` [PATCH v10 07/21] net/ntnic: add core platform structures Serhii Iliushyk
2024-07-17 13:32 ` [PATCH v10 08/21] net/ntnic: add adapter initialization Serhii Iliushyk
2024-07-17 13:32 ` [PATCH v10 09/21] net/ntnic: add registers and FPGA model Serhii Iliushyk
2024-07-17 13:32 ` [PATCH v10 10/21] net/ntnic: add FPGA modules for initialization Serhii Iliushyk
2024-07-17 13:32 ` [PATCH v10 11/21] net/ntnic: add FPGA initialization functionality Serhii Iliushyk
2024-07-17 13:32 ` [PATCH v10 12/21] net/ntnic: add support of the NT200A0X smartNIC Serhii Iliushyk
2024-07-17 13:33 ` [PATCH v10 13/21] net/ntnic: add startup and reset sequence for NT200A0X Serhii Iliushyk
2024-07-17 13:33 ` [PATCH v10 14/21] net/ntnic: add clock profile for the NT200A0X smartNIC Serhii Iliushyk
2024-07-17 13:33 ` [PATCH v10 15/21] net/ntnic: add link management skeleton Serhii Iliushyk
2024-07-18 21:42 ` Ferruh Yigit
2024-07-17 13:33 ` [PATCH v10 16/21] net/ntnic: add link 100G module ops Serhii Iliushyk
2024-07-17 13:33 ` [PATCH v10 17/21] net/ntnic: add generic NIM and I2C modules Serhii Iliushyk
2024-07-17 13:33 ` [PATCH v10 18/21] net/ntnic: add QSFP support Serhii Iliushyk
2024-07-17 13:33 ` [PATCH v10 19/21] net/ntnic: add QSFP28 support Serhii Iliushyk
2024-07-17 13:33 ` [PATCH v10 20/21] net/ntnic: add GPIO communication for NIMs Serhii Iliushyk
2024-07-17 13:33 ` [PATCH v10 21/21] net/ntnic: add physical layer control module Serhii Iliushyk
2024-07-18 21:43 ` [PATCH v10 01/21] net/ntnic: add ethdev and makes PMD available Ferruh Yigit
2024-07-23 7:49 ` Ferruh Yigit
2024-07-23 9:32 ` Thomas Monjalon
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