From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0602845683; Mon, 22 Jul 2024 18:42:33 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A951940FDE; Mon, 22 Jul 2024 18:40:23 +0200 (CEST) Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazon11011054.outbound.protection.outlook.com [52.101.65.54]) by mails.dpdk.org (Postfix) with ESMTP id 05C4740E4D for ; Mon, 22 Jul 2024 18:40:21 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=yDQOyx2FO/G5rOaXn0Ialnu+9curyK5rDBdhS1trUZP9/Hlmbo5LRwFMRzDiAkB7J0T4a51d3zlcM32MGdxozbnX1CahZBwDtwHpCu9dvoWAcq16XKGQGwWy2ZYFr+pqufc0ISGOiKABpwsdw1FtyIYc4xGWjes++ZovXjqRPUfjBB4RGoXAV2vgUavwp6bUZr09opD457AaEPYoyzOFxMnFHP/HIxPqbME8hwdLZ5mb1DSU+FA8LS7tyMoknAInSwlYYKnswpQU0RHFoeaAxYmomCnbXICyI1+n59QiP7kUdOJcaETEfqaYbuqjuFnM0ltN1bmlMkHTaisjVSH6qA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Rqzyuk5Fbicw5Hl1uw2MoeRW223qHkDJa3BqN0M4WUM=; b=w5vfD9OwrzADMnR63inrhDdEkja8ZQ5B9DnoqE0Qg8hPY06bZFxpwgpJJQaY5kbC+E9NsZRpP3XBAfDLT2OB0dsbOTFmT24A/dM1WgAKuAd4IfUROOW5c09B5RNp30OH+L4ibTvmnLjWNvigBSrR8J0aeZStFiGfabBvNJRPH5NzGGcyWqKsI1zL1HQMtuc94F6BhSYHjFkZ3UszmlKcprJeKAhh8DpeYE5reKr0NUJKeg8t5kZHMA27VsaEJRiDJxCOG+Y73CUDkD91FlJQmiuhJCdFfv64yIjoIoOr7F0tW0ZCbugHSB8l4YBy6SylUY9vVUBjGNOlwR3UrGDW5w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Rqzyuk5Fbicw5Hl1uw2MoeRW223qHkDJa3BqN0M4WUM=; b=k0VaGFPS5LzKZSPw+QmxrMEqtIgQtEhTN8gQZ+qP9JrZ4pOsqPzpKCEsWKkWX/LNi9Fc/HFR8Ilx6MoD5yy6Ub4H+95XkN4RcCRtEqj0f+7IJnfqT7BLiax5e0bDUjnKsy1m2V5vuu2yFAB8WzTEzzoUBcIwV2hDkPrmEcUJOwI= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AS8SPR01MB0024.eurprd04.prod.outlook.com (2603:10a6:20b:3d0::24) by PA1PR04MB10652.eurprd04.prod.outlook.com (2603:10a6:102:491::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7784.16; Mon, 22 Jul 2024 16:40:20 +0000 Received: from AS8SPR01MB0024.eurprd04.prod.outlook.com ([fe80::c634:479e:8f8a:a325]) by AS8SPR01MB0024.eurprd04.prod.outlook.com ([fe80::c634:479e:8f8a:a325%7]) with mapi id 15.20.7784.017; Mon, 22 Jul 2024 16:40:19 +0000 From: Gagandeep Singh To: dev@dpdk.org, Sachin Saxena Subject: [v3 19/30] dma/dpaa: data path optimization Date: Mon, 22 Jul 2024 22:09:19 +0530 Message-Id: <20240722163930.2171568-20-g.singh@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240722163930.2171568-1-g.singh@nxp.com> References: <20240722115843.1830105-1-g.singh@nxp.com> <20240722163930.2171568-1-g.singh@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SG3P274CA0014.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:be::26) To AS8SPR01MB0024.eurprd04.prod.outlook.com (2603:10a6:20b:3d0::24) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8SPR01MB0024:EE_|PA1PR04MB10652:EE_ X-MS-Office365-Filtering-Correlation-Id: 49a9e873-e6e9-4894-398d-08dcaa6cf967 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|366016|52116014|376014|1800799024|38350700014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ALac9r4a+NNvRgIOHPxHGVjKMPPZCTJPV/7oBvDKCCPSrIjbpAvzpOVOrq/4?= =?us-ascii?Q?qE8ysESqqG3y4qXZlvetbtHoltzjy2fBtp8SlUqAQIJUUkUYveSaEahVASem?= =?us-ascii?Q?sxV0IvwmHnKUfXoz8thfZx9kY97Tyv8P/tbTAAxQ59GHIC0mltYpFT/b1Bec?= =?us-ascii?Q?AGQLQTu9Qtlbn6teZGZGgWbin2pLf7hjrRGqHLs3CPYrlRmY5QIGqd0ML0ig?= =?us-ascii?Q?Hm2wgjHab/IFR9TsfSWkLmNcgaZ1QpR02xzFfAwQ+NEG7mRvZUNM5EVesmrj?= =?us-ascii?Q?9v9wA2/JezUCK1E5kSebdNQK4oCCS4PLePJ11xKBSGo1vJuPWSLrn5X6+BC5?= =?us-ascii?Q?XDTYpWJZ9hF7DgAnkejFxYftabnkMVUDmLaZ9aJHhOw+RoGm0NgMJiNS88BP?= =?us-ascii?Q?ntEdfF4XnCRavRJXyHJFzOrMFDU51p/uRZQGnubtAiZLCoo2ycVQWgC2fxtf?= =?us-ascii?Q?xlE2GsQyxVUTCa7Ap0i5muOVdB6NphojoptvQ9dgn3qrIKKZ8Lz6ptsPnM2f?= =?us-ascii?Q?1riu0U4+FCYDOXcAf0Nd3O5dtny+vGr/YhlX26LgLmWhvh2llzO1Wl0AyLtP?= =?us-ascii?Q?NpcD84HEY/N/vgDa9QDrlHtmAPdA293wRbzdBpH9cET6nBVZEOQDPPejQjpy?= =?us-ascii?Q?I5oABFJECnNzFJdv/NJ+zeVimN8WirqswrKUlvujgycMUJNXYA/p+8/8jsxZ?= =?us-ascii?Q?1l5trU9IGgBUpNRKB0vwtdKY0w8P7nJ6cTwkdhK89DDLtUQLSyim2zns435d?= =?us-ascii?Q?9jznFMWbdPzlYSAZ1CwK1idIcPjRqxcxjMzX4LYSkaVeKCkm00NHDwxXoxGi?= =?us-ascii?Q?6GMaX4GmpEfZd1Fqgv0YLKK3DcFmCYgUKBsj/cGclL3k21zJCCYz26/hbW7b?= =?us-ascii?Q?zLz0S7XK01otgW7ZeGe6diSd8w0OmRR8JYqbnwcyb2ILxEB5QYqiTki433vT?= =?us-ascii?Q?ECCsDi+rRmDQhh52gX/DIRbKfGEEyBziOU/D41dhY+fKqnhBtEz5px6bCMbe?= =?us-ascii?Q?SVMWdOuZPu9p/cs5QxxXc7ApvHOsSvGuevmCkGX8cwy31oHRWGbZ8xwQ+7z1?= =?us-ascii?Q?7pJV5qiout18J1zWmpaW0ERWDv63tshA70JCGmNukFyG7D/a70E+VQlSOLJM?= =?us-ascii?Q?qE/9BxyAO0i2qnNoEWy0yWsqOoonenJCFt2CC8+lmS0A0Ssrd3LFlbzItamo?= =?us-ascii?Q?dYh0pwlR/y6xPRnjnwSkvEdrLDhoUmgakCkzOVgDEA5sidTDFGp/Zthttdtv?= =?us-ascii?Q?jFBDclgq18jiS+55CMli9JCWwdQjSxeRX44rCXSroZxscNbley5CleGNL3wA?= =?us-ascii?Q?Haoz8V1efcp5iULyM7OgeXqEaslNN3HL8aXu519B8FM+sCdztULN1Qu8Bfl5?= =?us-ascii?Q?UFp+W4iLRHIl2Ji8UXUCx17/+3RVYSF5vc0WH6oQqc6MY4PdYg=3D=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AS8SPR01MB0024.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(366016)(52116014)(376014)(1800799024)(38350700014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?YqdQJAq2uI/6TzoqjZlFS7kqLVaRO5Wfl5vevjQ3UmpjbnDtRBEbSbPl03Ge?= =?us-ascii?Q?oNATJhvqu7lh8QEQO62akt+WX5k3f0z0T4f76WGMFC1e/V7zcTjhPmH3ZZqG?= =?us-ascii?Q?YcyOkIXctNu4W5rD9AvCxwkf80daegwdaUVTcl16qkHFpRwPBE1WM+FfKsNc?= =?us-ascii?Q?4mjER2wWvLHNW3T/co542KZd/95qVv8q8Z5yTa41KFEYAOGB7Kw8w3TxeZDd?= =?us-ascii?Q?ebFw/mFGm9sf8VnIRqEQRLu6W636fiit0BI46462TcxrCCH9r2BkYtVeyhm1?= =?us-ascii?Q?LCJJ2T1POeOrVzcnPP8563IcNR/sz/du2BfepLkl7+/2gtHJCVVmzThDCs1e?= =?us-ascii?Q?UxkQo3eXjQ1kTefo4uXI2TejctE0lNCMOCj5wvdy2fSSnLdyShznoFXNIB7H?= =?us-ascii?Q?oyJgxjlMX7IMUZNhKmQYL8YUSKdeY5wCAbN8P2kKfQyqXOs1Y/PA/WxJIYky?= =?us-ascii?Q?67hjfKZH/nmRre+YVk+uFZEze7QTGweK1FdiVPJf9Nvw7rtqx5wfXIUrvE2W?= =?us-ascii?Q?v+KifYBQn16I/fvM0zQkIWa7sn+0vaY3DVhFa+LKck2zXrzlk9zTa6oFC06o?= =?us-ascii?Q?0pBqrrvs2OduE58/QZRd1wo/yGtJlgnuVS1PE0bqZ3o0Gv8h0QDB477j3inI?= =?us-ascii?Q?mrXc9o/SdIUj7dVYL+cTc5uPmVJDeQQlLS3UFMoFFisui8kDz9x8xALfwANY?= =?us-ascii?Q?61zL6Y4vRFp54Sm5Mdj7pMZcq1/2hLRk/qsvr1ubtHGVtkgNCC+GCUSpJcTQ?= =?us-ascii?Q?9zLWL5V6Erf8F4ekZvXY/Bio6vry30Tzc0v14j6mrxi4jRxQmLU7meBuHG/q?= =?us-ascii?Q?kk65REWbyQozGFnEo+x7BrrMXbv+vPFa5+r2X/Qmb9q+BlI6P42oyJgERvUl?= =?us-ascii?Q?iR6ix1Rt33tLdNNMo5N8M/LyAlw79+BnNF1qmJON7a3bHllKcroq8a13NG6a?= =?us-ascii?Q?fV8/CHml7dxwotqRdEkLu+p9wuDkzqmy3Up1qWeGSGtFyEbrKPcnEbKjtbWF?= =?us-ascii?Q?eREC9HiwVZB+3BsfhWbhQaJoeUURtOaBiBoHeX604sMttKxk18VHxftO8qN6?= =?us-ascii?Q?bNPY76c1upnyVbN3v3N/YkGD+L4XZH0QYgLiEzLOixTNBPZpvopMg8zIvcDS?= =?us-ascii?Q?UX/HWKR/HEtBisF4MvT5PuBSOYdzIg1YIPVtMzk93ewMqnNYIAMdAU6UpODf?= =?us-ascii?Q?8k2qhw5TrP9cUjFXM/BQdSSUW17smyj8kwCzrMkgtOshpeYIeQAUcOBY/4CQ?= =?us-ascii?Q?LOKj4pNhnlRzQHbtFtpKwBr4mBkx1m8o1wnBC3PJl04fwMByEaEnPW40cktV?= =?us-ascii?Q?t+xRlSb0yjDCsWny8NXGaQioXOH6v8ZLZXpfM3xxol947wgW/PL8JuoVX8Gs?= =?us-ascii?Q?nW8QkQJRylceStvESgeJd8m9Kp7ZbKvpReGMpvgVflA0Ww7upovs4Yy5vT/o?= =?us-ascii?Q?UFwnL+vvRm9R2EGbffPi3otsE9DoRo0WrlcCK4arwU1VVQziSoM9EclR0XJ4?= =?us-ascii?Q?OQLn49bWwYiWTuEjohtZDbQvEK/GfUP7yrq+hWhO7C9FVKuaAFXwIwuJqBsK?= =?us-ascii?Q?TcFZV2Xe+jZTimyQ6vOKR9JS2lpFvUwnmPMA7mDF?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 49a9e873-e6e9-4894-398d-08dcaa6cf967 X-MS-Exchange-CrossTenant-AuthSource: AS8SPR01MB0024.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jul 2024 16:40:19.8984 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +z7H2ZnV8LRGVCajFFVcx/f/N8XBUVzDWpRs9XV6FV1PTsFJYJWqwcB20CslJIjq X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA1PR04MB10652 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove unnessary status read before every send. Signed-off-by: Gagandeep Singh --- drivers/dma/dpaa/dpaa_qdma.c | 186 ++++++++++++++++++----------------- drivers/dma/dpaa/dpaa_qdma.h | 7 ++ 2 files changed, 101 insertions(+), 92 deletions(-) diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c index 8e8426b88d..4022ad6469 100644 --- a/drivers/dma/dpaa/dpaa_qdma.c +++ b/drivers/dma/dpaa/dpaa_qdma.c @@ -248,7 +248,8 @@ fsl_qdma_free_queue_resources(struct fsl_qdma_queue *queue) } static struct -fsl_qdma_queue *fsl_qdma_prep_status_queue(void) +fsl_qdma_queue *fsl_qdma_prep_status_queue(struct fsl_qdma_engine *fsl_qdma, + u32 id) { struct fsl_qdma_queue *status_head; unsigned int status_size; @@ -277,6 +278,8 @@ fsl_qdma_queue *fsl_qdma_prep_status_queue(void) sizeof(struct fsl_qdma_format)); status_head->n_cq = status_size; status_head->virt_head = status_head->cq; + status_head->queue_base = fsl_qdma->block_base + + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id); return status_head; } @@ -334,12 +337,9 @@ fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma) } static int -fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma, - void *block, int id, const uint16_t nb_cpls, +fsl_qdma_queue_transfer_complete(void *block, const uint16_t nb_cpls, enum rte_dma_status_code *status) { - struct fsl_qdma_queue *fsl_status = fsl_qdma->status[id]; - struct fsl_qdma_format *status_addr; u32 reg; int count = 0; @@ -348,16 +348,7 @@ fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma, if (reg & FSL_QDMA_BSQSR_QE_BE) return count; - status_addr = fsl_status->virt_head; - - reg = qdma_readl_be(block + FSL_QDMA_BSQMR); - reg |= FSL_QDMA_BSQMR_DI_BE; - - qdma_desc_addr_set64(status_addr, 0x0); - fsl_status->virt_head++; - if (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq) - fsl_status->virt_head = fsl_status->cq; - qdma_writel_be(reg, block + FSL_QDMA_BSQMR); + qdma_writel_be(FSL_QDMA_BSQMR_DI, block + FSL_QDMA_BSQMR); if (status != NULL) status[count] = RTE_DMA_STATUS_SUCCESSFUL; @@ -472,19 +463,37 @@ fsl_qdma_enqueue_desc(struct fsl_qdma_queue *fsl_queue, { void *block = fsl_queue->queue_base; struct fsl_qdma_format *csgf_src, *csgf_dest; - u32 reg; #ifdef RTE_DMA_DPAA_ERRATA_ERR050757 struct fsl_qdma_sdf *sdf; u32 cfg = 0; #endif +#ifdef CONFIG_RTE_DMA_DPAA_ERR_CHK + u32 reg; + /* retrieve and store the register value in big endian * to avoid bits swap */ reg = qdma_readl_be(block + FSL_QDMA_BCQSR(fsl_queue->id)); - if (reg & (FSL_QDMA_BCQSR_QF_XOFF_BE)) + if (reg & (FSL_QDMA_BCQSR_QF_XOFF_BE)) { + DPAA_QDMA_ERR("QDMA Engine is busy\n"); return -1; + } +#else + /* check whether critical watermark level reached, + * below check is valid for only single queue per block + */ + if ((fsl_queue->stats.submitted - fsl_queue->stats.completed) + >= QDMA_QUEUE_CR_WM) { + DPAA_QDMA_DEBUG("Queue is full, try dequeue first\n"); + return -1; + } +#endif + if (unlikely(fsl_queue->pending == fsl_queue->n_cq)) { + DPAA_QDMA_DEBUG("Queue is full, try dma submit first\n"); + return -1; + } csgf_src = (struct fsl_qdma_format *)fsl_queue->virt_addr[fsl_queue->ci] + QDMA_SGF_SRC_OFF; @@ -512,19 +521,14 @@ fsl_qdma_enqueue_desc(struct fsl_qdma_queue *fsl_queue, qdma_csgf_set_len(csgf_dest, len); /* This entry is the last entry. */ qdma_csgf_set_f(csgf_dest, len); - fsl_queue->virt_head++; fsl_queue->ci++; - if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq) { - fsl_queue->virt_head = fsl_queue->cq; + if (fsl_queue->ci == fsl_queue->n_cq) fsl_queue->ci = 0; - } - if (flags & RTE_DMA_OP_FLAG_SUBMIT) { - reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id)); - reg |= FSL_QDMA_BCQMR_EI_BE; - qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id)); + qdma_writel_be(FSL_QDMA_BCQMR_EI, + block + FSL_QDMA_BCQMR(fsl_queue->id)); fsl_queue->stats.submitted++; } else { fsl_queue->pending++; @@ -618,12 +622,9 @@ dpaa_qdma_submit(void *dev_private, uint16_t vchan) struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue[fsl_qdma->vchan_map[vchan]]; void *block = fsl_queue->queue_base; - u32 reg; while (fsl_queue->pending) { - reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id)); - reg |= FSL_QDMA_BCQMR_EI_BE; - qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id)); + qdma_writel_be(FSL_QDMA_BCQMR_EI, block + FSL_QDMA_BCQMR(fsl_queue->id)); fsl_queue->pending--; fsl_queue->stats.submitted++; } @@ -656,44 +657,43 @@ dpaa_qdma_dequeue_status(void *dev_private, uint16_t vchan, enum rte_dma_status_code *st) { struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private; - int id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES); - void *block; - int intr; - void *status = fsl_qdma->status_base; + int ret; struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue[fsl_qdma->vchan_map[vchan]]; + void *status = fsl_qdma->status_base; + int intr; - intr = qdma_readl_be(status + FSL_QDMA_DEDR); - if (intr) { - DPAA_QDMA_ERR("DMA transaction error! %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECFDW0R); - DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW0R %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECFDW1R); - DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW1R %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECFDW2R); - DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW2R %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECFDW3R); - DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW3R %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECFQIDR); - DPAA_QDMA_INFO("reg FSL_QDMA_DECFQIDR %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECBR); - DPAA_QDMA_INFO("reg FSL_QDMA_DECBR %x\n", intr); - qdma_writel(0xffffffff, - status + FSL_QDMA_DEDR); - intr = qdma_readl(status + FSL_QDMA_DEDR); - fsl_queue->stats.errors++; + ret = fsl_qdma_queue_transfer_complete(fsl_queue->queue_base, + nb_cpls, st); + if (!ret) { + intr = qdma_readl_be(status + FSL_QDMA_DEDR); + if (intr) { +#ifdef CONFIG_RTE_DMA_DPAA_ERR_CHK + DPAA_QDMA_ERR("DMA transaction error! %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW0R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW0R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW1R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW1R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW2R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW2R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW3R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW3R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFQIDR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFQIDR %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECBR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECBR %x\n", intr); +#endif + qdma_writel_be(0xbf, + status + FSL_QDMA_DEDR); + fsl_queue->stats.errors++; + } } - block = fsl_qdma->block_base + - FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id); - - intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls, - st); - fsl_queue->stats.completed += intr; + fsl_queue->stats.completed += ret; if (last_idx != NULL) *last_idx = (uint16_t)(fsl_queue->stats.completed - 1); - return intr; + return ret; } @@ -703,44 +703,46 @@ dpaa_qdma_dequeue(void *dev_private, uint16_t *last_idx, bool *has_error) { struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine *)dev_private; - int id = (int)((fsl_qdma->vchan_map[vchan]) / QDMA_QUEUES); - void *block; - int intr; - void *status = fsl_qdma->status_base; + int ret; struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue[fsl_qdma->vchan_map[vchan]]; +#ifdef CONFIG_RTE_DMA_DPAA_ERR_CHK + void *status = fsl_qdma->status_base; + int intr; +#endif - intr = qdma_readl_be(status + FSL_QDMA_DEDR); - if (intr) { - DPAA_QDMA_ERR("DMA transaction error! %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECFDW0R); - DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW0R %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECFDW1R); - DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW1R %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECFDW2R); - DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW2R %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECFDW3R); - DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW3R %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECFQIDR); - DPAA_QDMA_INFO("reg FSL_QDMA_DECFQIDR %x\n", intr); - intr = qdma_readl(status + FSL_QDMA_DECBR); - DPAA_QDMA_INFO("reg FSL_QDMA_DECBR %x\n", intr); - qdma_writel(0xffffffff, - status + FSL_QDMA_DEDR); - intr = qdma_readl(status + FSL_QDMA_DEDR); - *has_error = true; - fsl_queue->stats.errors++; + *has_error = false; + ret = fsl_qdma_queue_transfer_complete(fsl_queue->queue_base, + nb_cpls, NULL); +#ifdef CONFIG_RTE_DMA_DPAA_ERR_CHK + if (!ret) { + intr = qdma_readl_be(status + FSL_QDMA_DEDR); + if (intr) { + DPAA_QDMA_ERR("DMA transaction error! %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW0R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW0R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW1R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW1R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW2R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW2R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFDW3R); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFDW3R %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECFQIDR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECFQIDR %x\n", intr); + intr = qdma_readl(status + FSL_QDMA_DECBR); + DPAA_QDMA_INFO("reg FSL_QDMA_DECBR %x\n", intr); + qdma_writel_be(0xbf, + status + FSL_QDMA_DEDR); + intr = qdma_readl(status + FSL_QDMA_DEDR); + *has_error = true; + fsl_queue->stats.errors++; + } } - - block = fsl_qdma->block_base + - FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id); - - intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id, nb_cpls, - NULL); - fsl_queue->stats.completed += intr; +#endif + fsl_queue->stats.completed += ret; if (last_idx != NULL) *last_idx = (uint16_t)(fsl_queue->stats.completed - 1); - return intr; + return ret; } static int @@ -842,7 +844,7 @@ dpaa_qdma_init(struct rte_dma_dev *dmadev) } for (i = 0; i < fsl_qdma->num_blocks; i++) { - fsl_qdma->status[i] = fsl_qdma_prep_status_queue(); + fsl_qdma->status[i] = fsl_qdma_prep_status_queue(fsl_qdma, i); if (!fsl_qdma->status[i]) goto mem_free; j = 0; diff --git a/drivers/dma/dpaa/dpaa_qdma.h b/drivers/dma/dpaa/dpaa_qdma.h index 80366ce890..8a4517a70a 100644 --- a/drivers/dma/dpaa/dpaa_qdma.h +++ b/drivers/dma/dpaa/dpaa_qdma.h @@ -58,11 +58,17 @@ #define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20) #define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16) +/* Update the value appropriately whenever QDMA_QUEUE_SIZE + * changes. + */ +#define FSL_QDMA_BCQMR_EI 0x20c0 + #define FSL_QDMA_BCQSR_QF_XOFF_BE 0x1000100 #define FSL_QDMA_BSQMR_EN 0x80000000 #define FSL_QDMA_BSQMR_DI_BE 0x40 #define FSL_QDMA_BSQMR_CQ_SIZE(x) ((x) << 16) +#define FSL_QDMA_BSQMR_DI 0xc0 #define FSL_QDMA_BSQSR_QE_BE 0x200 @@ -110,6 +116,7 @@ #define QDMA_SGF_SRC_OFF 2 #define QDMA_SGF_DST_OFF 3 #define QDMA_DESC_OFF 1 +#define QDMA_QUEUE_CR_WM 32 #define QDMA_BIG_ENDIAN 1 #ifdef QDMA_BIG_ENDIAN -- 2.25.1