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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS2PEPF0000343F.mail.protection.outlook.com (10.167.18.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7784.11 via Frontend Transport; Tue, 23 Jul 2024 08:16:05 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 23 Jul 2024 01:15:47 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 23 Jul 2024 01:15:44 -0700 From: Bing Zhao To: , , , CC: , , , "Yevgeny Kliteynik" Subject: [PATCH 1/4] net/mlx5/hws: fix state detection of queue full in polling Date: Tue, 23 Jul 2024 11:15:19 +0300 Message-ID: <20240723081522.1087433-2-bingz@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240723081522.1087433-1-bingz@nvidia.com> References: <20240723081522.1087433-1-bingz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343F:EE_|IA0PR12MB7508:EE_ X-MS-Office365-Filtering-Correlation-Id: 96b6a5fb-8d04-4239-6b05-08dcaaefb32a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2024 08:16:05.8168 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96b6a5fb-8d04-4239-6b05-08dcaaefb32a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7508 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The sending queue (SQ) size of BWC API is not fixed and the same as that of other HWS rule insertion SQs. When checking the queue full state, the number of queue entries and the used entries should be used instead of the macro "MLX5DR_BWC_MATCHER_REHASH_QUEUE_SZ". Or else, when resizing the matcher and moving the rules, sometimes it would fail incorrectly. For example, once a hiccup of generating CQE happened, the polling of CQ exited directly without any retry. Then there was no enough room for the next rule to be moved. Using the correct state of a SQ will solve this issue, the polling of associative CQ will continue until a new CQE is generated. Fixes: 87026d2e6601 ("net/mlx5/hws: support backward-compatible API") Signed-off-by: Bing Zhao Reviewed-by: Yevgeny Kliteynik Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/hws/mlx5dr_bwc.c | 4 +++- drivers/net/mlx5/hws/mlx5dr_bwc.h | 1 - 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_bwc.c b/drivers/net/mlx5/hws/mlx5dr_bwc.c index e0b6390ed9..9233452118 100644 --- a/drivers/net/mlx5/hws/mlx5dr_bwc.c +++ b/drivers/net/mlx5/hws/mlx5dr_bwc.c @@ -181,10 +181,10 @@ mlx5dr_bwc_queue_poll(struct mlx5dr_context *ctx, uint32_t *pending_rules, bool drain) { - bool queue_full = *pending_rules == MLX5DR_BWC_MATCHER_REHASH_QUEUE_SZ; struct rte_flow_op_result comp[MLX5DR_BWC_MATCHER_REHASH_BURST_TH]; uint16_t burst_th = mlx5dr_bwc_get_burst_th(ctx, queue_id); bool got_comp = *pending_rules >= burst_th; + bool queue_full; int err = 0; int ret; int i; @@ -193,6 +193,8 @@ mlx5dr_bwc_queue_poll(struct mlx5dr_context *ctx, if (!got_comp && !drain) return 0; + /* The FULL state of a SQ is always a subcondition of the original 'got_comp'. */ + queue_full = mlx5dr_send_engine_full(&ctx->send_queue[queue_id]); while (queue_full || ((got_comp || drain) && *pending_rules)) { ret = mlx5dr_send_queue_poll(ctx, queue_id, comp, burst_th); if (unlikely(ret < 0)) { diff --git a/drivers/net/mlx5/hws/mlx5dr_bwc.h b/drivers/net/mlx5/hws/mlx5dr_bwc.h index 648443861b..8c3f721ac2 100644 --- a/drivers/net/mlx5/hws/mlx5dr_bwc.h +++ b/drivers/net/mlx5/hws/mlx5dr_bwc.h @@ -9,7 +9,6 @@ #define MLX5DR_BWC_MATCHER_SIZE_LOG_STEP 1 #define MLX5DR_BWC_MATCHER_REHASH_PERCENT_TH 70 #define MLX5DR_BWC_MATCHER_REHASH_BURST_TH 32 -#define MLX5DR_BWC_MATCHER_REHASH_QUEUE_SZ 256 #define MLX5DR_BWC_MATCHER_ATTACH_AT_NUM 255 struct mlx5dr_bwc_matcher { -- 2.34.1