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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2024 07:36:38.1830 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58aa8219-c20c-4af4-afcd-08dcabb35a60 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB50.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7081 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add actions order supported in mlx5 PMD when HW steering flow engine is used. This limitation existed since HW Steering flow engine was introduced. Fixes: 22681deead3e ("net/mlx5/hws: enable hardware steering") Cc: stable@dpdk.org Signed-off-by: Maayan Kashani Acked-by: Dariusz Sosnowski --- doc/guides/nics/mlx5.rst | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 43fc181d8dc..4c00bb7755c 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -251,6 +251,26 @@ Limitations IPv6 routing extension matching is not supported in flow template relaxed matching mode (see ``struct rte_flow_pattern_template_attr::relaxed_matching``). + - The supported actions order is as below:: + + MARK(a) + *_DECAP(b) + OF_POP_VLAN + COUNT | AGE + METER_MARK | CONNTRACK + OF_PUSH_VLAN + MODIFY_FIELD + *_ENCAP(c) + JUMP | DROP | RSS(a) | QUEUE(a) | REPRESENTED_PORT(d) + + a. Only supported on ingress. + b. Any decapsulation action, including the combination of RAW_ENCAP and RAW_DECAP actions + which results in L3 decapsulation. + Not supported on egress. + c. Any encapsulation action, including the combination of RAW_ENCAP and RAW_DECAP actions + which results in L3 encap. + d. Only in transfer (switchdev) mode. + - When using Verbs flow engine (``dv_flow_en`` = 0), flow pattern without any specific VLAN will match for VLAN packets as well: -- 2.21.0