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From: Vamsi Attunuru <vattunuru@marvell.com>
To: <fengchengwen@huawei.com>, <dev@dpdk.org>,
	<kevin.laatz@intel.com>, <bruce.richardson@intel.com>
Cc: <jerinj@marvell.com>, <anoobj@marvell.com>,
	Vamsi Attunuru <vattunuru@marvell.com>
Subject: [RFC] dmadev: add QoS capability
Date: Mon, 29 Jul 2024 04:55:58 -0700	[thread overview]
Message-ID: <20240729115558.263574-1-vattunuru@marvell.com> (raw)

Some DMA controllers support QoS at HW command queue level to
differentiate the performance on different HW queues based on
the priority configured. Patch adds required fields in dmadev
structures to get hardware supported priority levels and the
provision to configure the priority from the applications.

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
---
 lib/dmadev/rte_dmadev.c | 10 ++++++++++
 lib/dmadev/rte_dmadev.h | 19 +++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/lib/dmadev/rte_dmadev.c b/lib/dmadev/rte_dmadev.c
index 845727210f..9ff62efcb4 100644
--- a/lib/dmadev/rte_dmadev.c
+++ b/lib/dmadev/rte_dmadev.c
@@ -491,6 +491,16 @@ rte_dma_configure(int16_t dev_id, const struct rte_dma_conf *dev_conf)
 			"Device %d configure too many vchans", dev_id);
 		return -EINVAL;
 	}
+	if (dev_conf->priority &&
+	    !(dev_info.dev_capa & RTE_DMA_CAPA_QOS)) {
+		RTE_DMA_LOG(ERR, "Device %d don't support QoS", dev_id);
+		return -EINVAL;
+	}
+	if (dev_conf->priority >= dev_info.nb_priorities) {
+		RTE_DMA_LOG(ERR,
+			"Device %d configure invalid priority", dev_id);
+		return -EINVAL;
+	}
 	if (dev_conf->enable_silent &&
 	    !(dev_info.dev_capa & RTE_DMA_CAPA_SILENT)) {
 		RTE_DMA_LOG(ERR, "Device %d don't support silent", dev_id);
diff --git a/lib/dmadev/rte_dmadev.h b/lib/dmadev/rte_dmadev.h
index 5474a5281d..08db8ead0a 100644
--- a/lib/dmadev/rte_dmadev.h
+++ b/lib/dmadev/rte_dmadev.h
@@ -268,6 +268,16 @@ int16_t rte_dma_next_dev(int16_t start_dev_id);
 #define RTE_DMA_CAPA_OPS_COPY_SG	RTE_BIT64(33)
 /** Support fill operation. */
 #define RTE_DMA_CAPA_OPS_FILL		RTE_BIT64(34)
+/** Support QoS at DMA HW channel level
+ *
+ * If device supports QoS then application could configure priority to the
+ * DMA HW channel using 'priority' field in struct rte_dma_conf. Number of
+ * supported prioirty levels will be known from 'nb_priorities' field in
+ * struct rte_dma_info.
+ * DMA devices which support QoS at HW channel level can advertise this
+ * capability.
+ */
+#define RTE_DMA_CAPA_QOS		RTE_BIT64(35)
 /**@}*/
 
 /**
@@ -297,6 +307,8 @@ struct rte_dma_info {
 	int16_t numa_node;
 	/** Number of virtual DMA channel configured. */
 	uint16_t nb_vchans;
+	/** Number of priority levels supported by DMA HW channel. */
+	uint16_t nb_priorities;
 };
 
 /**
@@ -332,6 +344,13 @@ struct rte_dma_conf {
 	 * @see RTE_DMA_CAPA_SILENT
 	 */
 	bool enable_silent;
+	/* The prioirty of the DMA HW channel.
+	 * This value cannot be greater than or equal to the field 'nb_priorities'
+	 * of struct rte_dma_info which get from rte_dma_info_get().
+	 * Among the values between '0' and 'nb_priorities - 1', lowest value
+	 * indicates higher priority and vice-versa.
+	 */
+	uint16_t priority;
 };
 
 /**
-- 
2.25.1


             reply	other threads:[~2024-07-29 11:56 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-29 11:55 Vamsi Attunuru [this message]
2024-07-29 13:14 ` Morten Brørup
2024-07-29 13:27   ` Bruce Richardson
2024-07-29 13:53     ` Morten Brørup
2024-07-29 14:47       ` Vamsi Krishna Attunuru

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