From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EF9AF456E2; Mon, 29 Jul 2024 13:56:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 81AF540261; Mon, 29 Jul 2024 13:56:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7FE9B4021D for ; Mon, 29 Jul 2024 13:56:08 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46SN05Rg006593; Mon, 29 Jul 2024 04:56:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=pfpt0220; bh=DexPOAQEgOBGmt6CxNdE+J9 LhRscSHDgiOORFDn2Yc0=; b=Cy//UnmpR7AGQKDvxRE0orTXw23iDYYWRGRYeLr nCesTPcdwreEPKdAAnv1UrSCfPnQFnjaFUQ3ijL/twisOs2u4nY7kn/xASya0QqN 7socQc/aWEq8uCGJD7kaltJ4gMxEB2Cl1ZLhbOJnwBymSIhsYGA1fqOyXmTASb7l HgNc84cNtaOS55z7mktGDATNe451K0VXn8AYJkmCWn87sKljRX4UMz4VRpCQxZ/9 J8SjXLn6/h/f0svD+sfQ47Aewwzjos8RPtBsfvRFePrEuW+42Fe/e325eKvR2B1Y VGfAXS7eBsL6a89bBoAqjpxlJLnUctQkDjz4eC9nVgY+Oqw== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 40nmtwjy71-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 29 Jul 2024 04:56:07 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 29 Jul 2024 04:56:05 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 29 Jul 2024 04:56:05 -0700 Received: from localhost.localdomain (unknown [10.28.36.156]) by maili.marvell.com (Postfix) with ESMTP id 3F0D33F70C2; Mon, 29 Jul 2024 04:56:03 -0700 (PDT) From: Vamsi Attunuru To: , , , CC: , , Vamsi Attunuru Subject: [RFC] dmadev: add QoS capability Date: Mon, 29 Jul 2024 04:55:58 -0700 Message-ID: <20240729115558.263574-1-vattunuru@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: XtQBTs7sYawLD7vONN62vt7r7FNCogrO X-Proofpoint-ORIG-GUID: XtQBTs7sYawLD7vONN62vt7r7FNCogrO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-29_10,2024-07-26_01,2024-05-17_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some DMA controllers support QoS at HW command queue level to differentiate the performance on different HW queues based on the priority configured. Patch adds required fields in dmadev structures to get hardware supported priority levels and the provision to configure the priority from the applications. Signed-off-by: Vamsi Attunuru --- lib/dmadev/rte_dmadev.c | 10 ++++++++++ lib/dmadev/rte_dmadev.h | 19 +++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/lib/dmadev/rte_dmadev.c b/lib/dmadev/rte_dmadev.c index 845727210f..9ff62efcb4 100644 --- a/lib/dmadev/rte_dmadev.c +++ b/lib/dmadev/rte_dmadev.c @@ -491,6 +491,16 @@ rte_dma_configure(int16_t dev_id, const struct rte_dma_conf *dev_conf) "Device %d configure too many vchans", dev_id); return -EINVAL; } + if (dev_conf->priority && + !(dev_info.dev_capa & RTE_DMA_CAPA_QOS)) { + RTE_DMA_LOG(ERR, "Device %d don't support QoS", dev_id); + return -EINVAL; + } + if (dev_conf->priority >= dev_info.nb_priorities) { + RTE_DMA_LOG(ERR, + "Device %d configure invalid priority", dev_id); + return -EINVAL; + } if (dev_conf->enable_silent && !(dev_info.dev_capa & RTE_DMA_CAPA_SILENT)) { RTE_DMA_LOG(ERR, "Device %d don't support silent", dev_id); diff --git a/lib/dmadev/rte_dmadev.h b/lib/dmadev/rte_dmadev.h index 5474a5281d..08db8ead0a 100644 --- a/lib/dmadev/rte_dmadev.h +++ b/lib/dmadev/rte_dmadev.h @@ -268,6 +268,16 @@ int16_t rte_dma_next_dev(int16_t start_dev_id); #define RTE_DMA_CAPA_OPS_COPY_SG RTE_BIT64(33) /** Support fill operation. */ #define RTE_DMA_CAPA_OPS_FILL RTE_BIT64(34) +/** Support QoS at DMA HW channel level + * + * If device supports QoS then application could configure priority to the + * DMA HW channel using 'priority' field in struct rte_dma_conf. Number of + * supported prioirty levels will be known from 'nb_priorities' field in + * struct rte_dma_info. + * DMA devices which support QoS at HW channel level can advertise this + * capability. + */ +#define RTE_DMA_CAPA_QOS RTE_BIT64(35) /**@}*/ /** @@ -297,6 +307,8 @@ struct rte_dma_info { int16_t numa_node; /** Number of virtual DMA channel configured. */ uint16_t nb_vchans; + /** Number of priority levels supported by DMA HW channel. */ + uint16_t nb_priorities; }; /** @@ -332,6 +344,13 @@ struct rte_dma_conf { * @see RTE_DMA_CAPA_SILENT */ bool enable_silent; + /* The prioirty of the DMA HW channel. + * This value cannot be greater than or equal to the field 'nb_priorities' + * of struct rte_dma_info which get from rte_dma_info_get(). + * Among the values between '0' and 'nb_priorities - 1', lowest value + * indicates higher priority and vice-versa. + */ + uint16_t priority; }; /** -- 2.25.1