* [v1,2/5] raw/zxdh: add support for queue setup operation
2024-08-05 13:34 [v1,1/5] raw/zxdh: introduce zxdh raw device driver Yong Zhang
@ 2024-08-05 13:34 ` Yong Zhang
2024-08-05 13:34 ` [v1,3/5] raw/zxdh: add support for standard rawdev operations Yong Zhang
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Yong Zhang @ 2024-08-05 13:34 UTC (permalink / raw)
To: dev; +Cc: Yong Zhang
[-- Attachment #1.1.1: Type: text/plain, Size: 9770 bytes --]
Add queue initialization and release interface.
Signed-off-by: Yong Zhang <zhang.yong25@zte.com.cn>
---
drivers/raw/zxdh/zxdh_rawdev.c | 241 +++++++++++++++++++++++++++++++++
drivers/raw/zxdh/zxdh_rawdev.h | 19 +++
2 files changed, 260 insertions(+)
diff --git a/drivers/raw/zxdh/zxdh_rawdev.c b/drivers/raw/zxdh/zxdh_rawdev.c
index 43211dbbb7..5e42669bc7 100644
--- a/drivers/raw/zxdh/zxdh_rawdev.c
+++ b/drivers/raw/zxdh/zxdh_rawdev.c
@@ -36,14 +36,58 @@
#include "zxdh_rawdev.h"
+/*
+ * User define:
+ * ep_id-bit[15:12] vfunc_num-bit[11:4] func_num-bit[3:1] vfunc_active-bit0
+ * host ep_id:5~8 zf ep_id:9
+ */
+#define ZXDH_GDMA_ZF_USER 0x9000 /* ep4 pf0 */
+#define ZXDH_GDMA_PF_NUM_SHIFT 1
+#define ZXDH_GDMA_VF_NUM_SHIFT 4
+#define ZXDH_GDMA_EP_ID_SHIFT 12
+#define ZXDH_GDMA_VF_EN 1
+#define ZXDH_GDMA_EPID_OFFSET 5
+
/* Register offset */
#define ZXDH_GDMA_BASE_OFFSET 0x100000
+#define ZXDH_GDMA_EXT_ADDR_OFFSET 0x218
+#define ZXDH_GDMA_CONTROL_OFFSET 0x230
+#define ZXDH_GDMA_TC_CNT_OFFSET 0x23c
+#define ZXDH_GDMA_LLI_USER_OFFSET 0x228
+
+#define ZXDH_GDMA_CHAN_FORCE_CLOSE (1 << 31)
+
+/* TC count & Error interrupt status register */
+#define ZXDH_GDMA_SRC_LLI_ERR (1 << 16)
+#define ZXDH_GDMA_SRC_DATA_ERR (1 << 17)
+#define ZXDH_GDMA_DST_ADDR_ERR (1 << 18)
+#define ZXDH_GDMA_ERR_STATUS (1 << 19)
+#define ZXDH_GDMA_ERR_INTR_ENABLE (1 << 20)
+#define ZXDH_GDMA_TC_CNT_CLEAN (1)
#define ZXDH_GDMA_CHAN_SHIFT 0x80
+#define LOW32_MASK 0xffffffff
+#define LOW16_MASK 0xffff
+
+static int zxdh_gdma_queue_init(struct rte_rawdev *dev, uint16_t queue_id);
+static int zxdh_gdma_queue_free(struct rte_rawdev *dev, uint16_t queue_id);
char zxdh_gdma_driver_name[] = "rawdev_zxdh_gdma";
char dev_name[] = "zxdh_gdma";
+static inline struct zxdh_gdma_queue *
+zxdh_gdma_get_queue(struct rte_rawdev *dev, uint16_t queue_id)
+{
+ struct zxdh_gdma_rawdev *gdmadev = zxdh_gdma_rawdev_get_priv(dev);
+
+ if (queue_id >= ZXDH_GDMA_TOTAL_CHAN_NUM) {
+ ZXDH_PMD_LOG(ERR, "queue id %d is invalid", queue_id);
+ return NULL;
+ }
+
+ return &(gdmadev->vqs[queue_id]);
+}
+
uint
zxdh_gdma_read_reg(struct rte_rawdev *dev, uint16_t queue_id, uint offset)
{
@@ -67,9 +111,206 @@ zxdh_gdma_write_reg(struct rte_rawdev *dev, uint16_t queue_id, uint offset, uint
*(uint *)(gdmadev->base_addr + addr) = val;
}
+static int
+zxdh_gdma_rawdev_queue_setup(struct rte_rawdev *dev,
+ uint16_t queue_id,
+ rte_rawdev_obj_t queue_conf,
+ size_t conf_size)
+{
+ struct zxdh_gdma_rawdev *gdmadev = NULL;
+ struct zxdh_gdma_queue *queue = NULL;
+ struct zxdh_gdma_queue_config *qconfig = NULL;
+ struct zxdh_gdma_rbp *rbp = NULL;
+ uint16_t i = 0;
+ uint8_t is_txq = 0;
+ uint src_user = 0;
+ uint dst_user = 0;
+
+ if (dev == NULL)
+ return -EINVAL;
+
+ if ((queue_conf == NULL) || (conf_size != sizeof(struct zxdh_gdma_queue_config)))
+ return -EINVAL;
+
+ gdmadev = zxdh_gdma_rawdev_get_priv(dev);
+ qconfig = (struct zxdh_gdma_queue_config *)queue_conf;
+
+ for (i = 0; i < ZXDH_GDMA_TOTAL_CHAN_NUM; i++) {
+ if (gdmadev->vqs[i].enable == 0)
+ break;
+ }
+ if (i >= ZXDH_GDMA_TOTAL_CHAN_NUM) {
+ ZXDH_PMD_LOG(ERR, "Failed to setup queue, no avail queues");
+ return -1;
+ }
+ queue_id = i;
+ if (zxdh_gdma_queue_init(dev, queue_id) != 0) {
+ ZXDH_PMD_LOG(ERR, "Failed to init queue");
+ return -1;
+ }
+ queue = &(gdmadev->vqs[queue_id]);
+
+ rbp = qconfig->rbp;
+ if ((rbp->srbp != 0) && (rbp->drbp == 0)) {
+ is_txq = 0;
+ dst_user = ZXDH_GDMA_ZF_USER;
+ src_user = ((rbp->spfid << ZXDH_GDMA_PF_NUM_SHIFT) |
+ ((rbp->sportid + ZXDH_GDMA_EPID_OFFSET) << ZXDH_GDMA_EP_ID_SHIFT));
+
+ if (rbp->svfid != 0)
+ src_user |= (ZXDH_GDMA_VF_EN |
+ ((rbp->svfid - 1) << ZXDH_GDMA_VF_NUM_SHIFT));
+
+ ZXDH_PMD_LOG(DEBUG, "rxq->qidx:%d setup src_user(ep:%d pf:%d vf:%d) success",
+ queue_id, (uint8_t)rbp->sportid, (uint8_t)rbp->spfid,
+ (uint8_t)rbp->svfid);
+ } else if ((rbp->srbp == 0) && (rbp->drbp != 0)) {
+ is_txq = 1;
+ src_user = ZXDH_GDMA_ZF_USER;
+ dst_user = ((rbp->dpfid << ZXDH_GDMA_PF_NUM_SHIFT) |
+ ((rbp->dportid + ZXDH_GDMA_EPID_OFFSET) << ZXDH_GDMA_EP_ID_SHIFT));
+
+ if (rbp->dvfid != 0)
+ dst_user |= (ZXDH_GDMA_VF_EN |
+ ((rbp->dvfid - 1) << ZXDH_GDMA_VF_NUM_SHIFT));
+
+ ZXDH_PMD_LOG(DEBUG, "txq->qidx:%d setup dst_user(ep:%d pf:%d vf:%d) success",
+ queue_id, (uint8_t)rbp->dportid, (uint8_t)rbp->dpfid,
+ (uint8_t)rbp->dvfid);
+ } else {
+ ZXDH_PMD_LOG(ERR, "Failed to setup queue, srbp/drbp is invalid");
+ return -EINVAL;
+ }
+ queue->is_txq = is_txq;
+
+ /* setup queue user info */
+ queue->user = (src_user & LOW16_MASK) | (dst_user << 16);
+
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_EXT_ADDR_OFFSET, queue->user);
+ gdmadev->used_num++;
+
+ return queue_id;
+}
+
static const struct rte_rawdev_ops zxdh_gdma_rawdev_ops = {
+ .queue_setup = zxdh_gdma_rawdev_queue_setup,
};
+static int
+zxdh_gdma_queue_init(struct rte_rawdev *dev, uint16_t queue_id)
+{
+ char name[RTE_RAWDEV_NAME_MAX_LEN];
+ struct zxdh_gdma_queue *queue = NULL;
+ const struct rte_memzone *mz = NULL;
+ uint size = 0;
+ int ret = 0;
+
+ queue = zxdh_gdma_get_queue(dev, queue_id);
+ if (queue == NULL)
+ return -EINVAL;
+
+ queue->enable = 1;
+ queue->vq_id = queue_id;
+ queue->flag = 0;
+ queue->tc_cnt = 0;
+
+ /* Init sw_ring */
+ memset(name, 0, sizeof(name));
+ snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "gdma_vq%d_sw_ring", queue_id);
+ size = queue->queue_size * sizeof(struct zxdh_gdma_job *);
+ queue->sw_ring.job = rte_zmalloc(name, size, 0);
+ if (queue->sw_ring.job == NULL) {
+ ZXDH_PMD_LOG(ERR, "can not allocate sw_ring %s", name);
+ ret = -ENOMEM;
+ goto free_queue;
+ }
+
+ /* Cache up to size-1 job in the ring to prevent overwriting hardware prefetching */
+ queue->sw_ring.free_cnt = queue->queue_size - 1;
+ queue->sw_ring.deq_cnt = 0;
+ queue->sw_ring.pend_cnt = 0;
+ queue->sw_ring.enq_idx = 0;
+ queue->sw_ring.deq_idx = 0;
+ queue->sw_ring.used_idx = 0;
+
+ /* Init ring */
+ memset(name, 0, sizeof(name));
+ snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "gdma_vq%d_ring", queue_id);
+ size = ZXDH_GDMA_RING_SIZE * sizeof(struct zxdh_gdma_buff_desc);
+ mz = rte_memzone_reserve_aligned(name, size, rte_socket_id(),
+ RTE_MEMZONE_IOVA_CONTIG, size);
+ if (mz == NULL) {
+ if (rte_errno == EEXIST)
+ mz = rte_memzone_lookup(name);
+ if (mz == NULL) {
+ ZXDH_PMD_LOG(ERR, "can not allocate ring %s", name);
+ ret = -ENOMEM;
+ goto free_queue;
+ }
+ }
+ memset(mz->addr, 0, size);
+ queue->ring.ring_mz = mz;
+ queue->ring.desc = (struct zxdh_gdma_buff_desc *)(mz->addr);
+ queue->ring.ring_mem = mz->iova;
+ queue->ring.avail_idx = 0;
+ ZXDH_PMD_LOG(INFO, "queue%u ring phy addr:0x%"PRIx64" virt addr:%p",
+ queue_id, mz->iova, mz->addr);
+
+ /* Initialize the hardware channel */
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_CONTROL_OFFSET,
+ ZXDH_GDMA_CHAN_FORCE_CLOSE);
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_TC_CNT_OFFSET,
+ ZXDH_GDMA_ERR_INTR_ENABLE | ZXDH_GDMA_ERR_STATUS | ZXDH_GDMA_TC_CNT_CLEAN);
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_LLI_USER_OFFSET,
+ ZXDH_GDMA_ZF_USER);
+
+ return 0;
+
+free_queue:
+ zxdh_gdma_queue_free(dev, queue_id);
+ return ret;
+}
+
+static int
+zxdh_gdma_queue_free(struct rte_rawdev *dev, uint16_t queue_id)
+{
+ struct zxdh_gdma_rawdev *gdmadev = NULL;
+ struct zxdh_gdma_queue *queue = NULL;
+ uint val = 0;
+
+ queue = zxdh_gdma_get_queue(dev, queue_id);
+ if (queue == NULL)
+ return -EINVAL;
+
+ gdmadev = zxdh_gdma_rawdev_get_priv(dev);
+ gdmadev->used_num--;
+
+ /* disable gdma channel */
+ val = ZXDH_GDMA_CHAN_FORCE_CLOSE;
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_CONTROL_OFFSET, val);
+
+ queue->enable = 0;
+ queue->is_txq = 0;
+ queue->flag = 0;
+ queue->user = 0;
+ queue->tc_cnt = 0;
+ queue->ring.avail_idx = 0;
+ queue->sw_ring.free_cnt = 0;
+ queue->sw_ring.deq_cnt = 0;
+ queue->sw_ring.pend_cnt = 0;
+ queue->sw_ring.enq_idx = 0;
+ queue->sw_ring.deq_idx = 0;
+ queue->sw_ring.used_idx = 0;
+
+ if (queue->sw_ring.job != NULL)
+ rte_free(queue->sw_ring.job);
+
+ if (queue->ring.ring_mz != NULL)
+ rte_memzone_free(queue->ring.ring_mz);
+
+ return 0;
+}
+
static int
zxdh_gdma_map_resource(struct rte_pci_device *dev)
{
diff --git a/drivers/raw/zxdh/zxdh_rawdev.h b/drivers/raw/zxdh/zxdh_rawdev.h
index 59180b2b75..850f1f7ec4 100644
--- a/drivers/raw/zxdh/zxdh_rawdev.h
+++ b/drivers/raw/zxdh/zxdh_rawdev.h
@@ -102,6 +102,25 @@ struct zxdh_gdma_rawdev {
struct zxdh_gdma_queue vqs[ZXDH_GDMA_TOTAL_CHAN_NUM];
};
+struct zxdh_gdma_rbp {
+ uint use_ultrashort:1;
+ uint enable:1;
+ uint dportid:3;
+ uint dpfid:3;
+ uint dvfid:8; /*using route by port for destination */
+ uint drbp:1;
+ uint sportid:3;
+ uint spfid:3;
+ uint svfid:8;
+ uint srbp:1;
+};
+
+struct zxdh_gdma_queue_config {
+ uint lcore_id;
+ uint flags;
+ struct zxdh_gdma_rbp *rbp;
+};
+
static inline struct zxdh_gdma_rawdev *
zxdh_gdma_rawdev_get_priv(const struct rte_rawdev *rawdev)
{
--
2.43.0
[-- Attachment #1.1.2: Type: text/html , Size: 23878 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread* [v1,3/5] raw/zxdh: add support for standard rawdev operations
2024-08-05 13:34 [v1,1/5] raw/zxdh: introduce zxdh raw device driver Yong Zhang
2024-08-05 13:34 ` [v1,2/5] raw/zxdh: add support for queue setup operation Yong Zhang
@ 2024-08-05 13:34 ` Yong Zhang
2024-08-05 13:35 ` [v1,4/5] raw/zxdh: add support for enqueue operation Yong Zhang
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Yong Zhang @ 2024-08-05 13:34 UTC (permalink / raw)
To: dev; +Cc: Yong Zhang
[-- Attachment #1.1.1: Type: text/plain, Size: 5402 bytes --]
Add support for rawdev operations such as dev_start and dev_stop.
Signed-off-by: Yong Zhang <zhang.yong25@zte.com.cn>
---
drivers/raw/zxdh/zxdh_rawdev.c | 136 ++++++++++++++++++++++++++++++++-
drivers/raw/zxdh/zxdh_rawdev.h | 10 +++
2 files changed, 145 insertions(+), 1 deletion(-)
diff --git a/drivers/raw/zxdh/zxdh_rawdev.c b/drivers/raw/zxdh/zxdh_rawdev.c
index 5e42669bc7..ce83c3b626 100644
--- a/drivers/raw/zxdh/zxdh_rawdev.c
+++ b/drivers/raw/zxdh/zxdh_rawdev.c
@@ -111,6 +111,96 @@ zxdh_gdma_write_reg(struct rte_rawdev *dev, uint16_t queue_id, uint offset, uint
*(uint *)(gdmadev->base_addr + addr) = val;
}
+static int
+zxdh_gdma_rawdev_info_get(struct rte_rawdev *dev,
+ __rte_unused rte_rawdev_obj_t dev_info,
+ __rte_unused size_t dev_info_size)
+{
+ if (dev == NULL)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int
+zxdh_gdma_rawdev_configure(const struct rte_rawdev *dev,
+ rte_rawdev_obj_t config,
+ size_t config_size)
+{
+ struct zxdh_gdma_config *gdma_config = NULL;
+
+ if ((dev == NULL) ||
+ (config == NULL) ||
+ (config_size != sizeof(struct zxdh_gdma_config)))
+ return -EINVAL;
+
+ gdma_config = (struct zxdh_gdma_config *)config;
+ if (gdma_config->max_vqs > ZXDH_GDMA_TOTAL_CHAN_NUM) {
+ ZXDH_PMD_LOG(ERR, "gdma supports up to %d queues", ZXDH_GDMA_TOTAL_CHAN_NUM);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+zxdh_gdma_rawdev_start(struct rte_rawdev *dev)
+{
+ struct zxdh_gdma_rawdev *gdmadev = NULL;
+
+ if (dev == NULL)
+ return -EINVAL;
+
+ gdmadev = zxdh_gdma_rawdev_get_priv(dev);
+ gdmadev->device_state = ZXDH_GDMA_DEV_RUNNING;
+
+ return 0;
+}
+
+static void
+zxdh_gdma_rawdev_stop(struct rte_rawdev *dev)
+{
+ struct zxdh_gdma_rawdev *gdmadev = NULL;
+
+ if (dev == NULL)
+ return;
+
+ gdmadev = zxdh_gdma_rawdev_get_priv(dev);
+ gdmadev->device_state = ZXDH_GDMA_DEV_STOPPED;
+}
+
+static int
+zxdh_gdma_rawdev_reset(struct rte_rawdev *dev)
+{
+ if (dev == NULL)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int
+zxdh_gdma_rawdev_close(struct rte_rawdev *dev)
+{
+ struct zxdh_gdma_rawdev *gdmadev = NULL;
+ struct zxdh_gdma_queue *queue = NULL;
+ uint16_t queue_id = 0;
+
+ if (dev == NULL)
+ return -EINVAL;
+
+ for (queue_id = 0; queue_id < ZXDH_GDMA_TOTAL_CHAN_NUM; queue_id++) {
+ queue = zxdh_gdma_get_queue(dev, queue_id);
+ if ((queue == NULL) || (queue->enable == 0))
+ continue;
+
+ zxdh_gdma_queue_free(dev, queue_id);
+ }
+ gdmadev = zxdh_gdma_rawdev_get_priv(dev);
+ gdmadev->device_state = ZXDH_GDMA_DEV_STOPPED;
+
+ return 0;
+}
+
static int
zxdh_gdma_rawdev_queue_setup(struct rte_rawdev *dev,
uint16_t queue_id,
@@ -192,8 +282,52 @@ zxdh_gdma_rawdev_queue_setup(struct rte_rawdev *dev,
return queue_id;
}
+static int
+zxdh_gdma_rawdev_queue_release(struct rte_rawdev *dev, uint16_t queue_id)
+{
+ struct zxdh_gdma_queue *queue = NULL;
+
+ if (dev == NULL)
+ return -EINVAL;
+
+ queue = zxdh_gdma_get_queue(dev, queue_id);
+ if ((queue == NULL) || (queue->enable == 0))
+ return -EINVAL;
+
+ zxdh_gdma_queue_free(dev, queue_id);
+
+ return 0;
+}
+
+static int
+zxdh_gdma_rawdev_get_attr(struct rte_rawdev *dev,
+ __rte_unused const char *attr_name,
+ uint64_t *attr_value)
+{
+ struct zxdh_gdma_rawdev *gdmadev = NULL;
+ struct zxdh_gdma_attr *gdma_attr = NULL;
+
+ if ((dev == NULL) || (attr_value == NULL))
+ return -EINVAL;
+
+ gdmadev = zxdh_gdma_rawdev_get_priv(dev);
+ gdma_attr = (struct zxdh_gdma_attr *)attr_value;
+ gdma_attr->num_hw_queues = gdmadev->used_num;
+
+ return 0;
+}
static const struct rte_rawdev_ops zxdh_gdma_rawdev_ops = {
+ .dev_info_get = zxdh_gdma_rawdev_info_get,
+ .dev_configure = zxdh_gdma_rawdev_configure,
+ .dev_start = zxdh_gdma_rawdev_start,
+ .dev_stop = zxdh_gdma_rawdev_stop,
+ .dev_close = zxdh_gdma_rawdev_close,
+ .dev_reset = zxdh_gdma_rawdev_reset,
+
.queue_setup = zxdh_gdma_rawdev_queue_setup,
+ .queue_release = zxdh_gdma_rawdev_queue_release,
+
+ .attr_get = zxdh_gdma_rawdev_get_attr,
};
static int
@@ -256,7 +390,7 @@ zxdh_gdma_queue_init(struct rte_rawdev *dev, uint16_t queue_id)
ZXDH_PMD_LOG(INFO, "queue%u ring phy addr:0x%"PRIx64" virt addr:%p",
queue_id, mz->iova, mz->addr);
- /* Initialize the hardware channel */
+ /* Configure the hardware channel to the initial state */
zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_CONTROL_OFFSET,
ZXDH_GDMA_CHAN_FORCE_CLOSE);
zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_TC_CNT_OFFSET,
diff --git a/drivers/raw/zxdh/zxdh_rawdev.h b/drivers/raw/zxdh/zxdh_rawdev.h
index 850f1f7ec4..b4e923261d 100644
--- a/drivers/raw/zxdh/zxdh_rawdev.h
+++ b/drivers/raw/zxdh/zxdh_rawdev.h
@@ -102,6 +102,12 @@ struct zxdh_gdma_rawdev {
struct zxdh_gdma_queue vqs[ZXDH_GDMA_TOTAL_CHAN_NUM];
};
+struct zxdh_gdma_config {
+ uint16_t max_hw_queues_per_core;
+ uint16_t max_vqs;
+ int fle_queue_pool_cnt;
+};
+
struct zxdh_gdma_rbp {
uint use_ultrashort:1;
uint enable:1;
@@ -121,6 +127,10 @@ struct zxdh_gdma_queue_config {
struct zxdh_gdma_rbp *rbp;
};
+struct zxdh_gdma_attr {
+ uint16_t num_hw_queues;
+};
+
static inline struct zxdh_gdma_rawdev *
zxdh_gdma_rawdev_get_priv(const struct rte_rawdev *rawdev)
{
--
2.43.0
[-- Attachment #1.1.2: Type: text/html , Size: 11771 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread* [v1,4/5] raw/zxdh: add support for enqueue operation
2024-08-05 13:34 [v1,1/5] raw/zxdh: introduce zxdh raw device driver Yong Zhang
2024-08-05 13:34 ` [v1,2/5] raw/zxdh: add support for queue setup operation Yong Zhang
2024-08-05 13:34 ` [v1,3/5] raw/zxdh: add support for standard rawdev operations Yong Zhang
@ 2024-08-05 13:35 ` Yong Zhang
2024-08-05 13:35 ` [v1,5/5] raw/zxdh: add support for dequeue operation Yong Zhang
2024-08-05 15:45 ` [v1,1/5] raw/zxdh: introduce zxdh raw device driver Stephen Hemminger
4 siblings, 0 replies; 7+ messages in thread
From: Yong Zhang @ 2024-08-05 13:35 UTC (permalink / raw)
To: dev; +Cc: Yong Zhang
[-- Attachment #1.1.1: Type: text/plain, Size: 10966 bytes --]
Add rawdev enqueue operation for zxdh devices.
Signed-off-by: Yong Zhang <zhang.yong25@zte.com.cn>
---
drivers/raw/zxdh/zxdh_rawdev.c | 220 +++++++++++++++++++++++++++++++++
drivers/raw/zxdh/zxdh_rawdev.h | 19 +++
2 files changed, 239 insertions(+)
diff --git a/drivers/raw/zxdh/zxdh_rawdev.c b/drivers/raw/zxdh/zxdh_rawdev.c
index ce83c3b626..76b8f7f728 100644
--- a/drivers/raw/zxdh/zxdh_rawdev.c
+++ b/drivers/raw/zxdh/zxdh_rawdev.c
@@ -51,10 +51,34 @@
/* Register offset */
#define ZXDH_GDMA_BASE_OFFSET 0x100000
#define ZXDH_GDMA_EXT_ADDR_OFFSET 0x218
+#define ZXDH_GDMA_SAR_LOW_OFFSET 0x200
+#define ZXDH_GDMA_DAR_LOW_OFFSET 0x204
+#define ZXDH_GDMA_SAR_HIGH_OFFSET 0x234
+#define ZXDH_GDMA_DAR_HIGH_OFFSET 0x238
+#define ZXDH_GDMA_XFERSIZE_OFFSET 0x208
#define ZXDH_GDMA_CONTROL_OFFSET 0x230
+#define ZXDH_GDMA_TC_STATUS_OFFSET 0x0
+#define ZXDH_GDMA_STATUS_CLEAN_OFFSET 0x80
+#define ZXDH_GDMA_LLI_L_OFFSET 0x21c
+#define ZXDH_GDMA_LLI_H_OFFSET 0x220
+#define ZXDH_GDMA_CHAN_CONTINUE_OFFSET 0x224
#define ZXDH_GDMA_TC_CNT_OFFSET 0x23c
#define ZXDH_GDMA_LLI_USER_OFFSET 0x228
+/* Control register */
+#define ZXDH_GDMA_CHAN_ENABLE 0x1
+#define ZXDH_GDMA_CHAN_DISABLE 0
+#define ZXDH_GDMA_SOFT_CHAN 0x2
+#define ZXDH_GDMA_TC_INTR_ENABLE 0x10
+#define ZXDH_GDMA_ALL_INTR_ENABLE 0x30
+#define ZXDH_GDMA_SBS_SHIFT 6 /* src burst size */
+#define ZXDH_GDMA_SBL_SHIFT 9 /* src burst length */
+#define ZXDH_GDMA_DBS_SHIFT 13 /* dest burst size */
+#define ZXDH_GDMA_BURST_SIZE_MIN 0x1 /* 1 byte */
+#define ZXDH_GDMA_BURST_SIZE_MEDIUM 0x4 /* 4 word */
+#define ZXDH_GDMA_BURST_SIZE_MAX 0x6 /* 16 word */
+#define ZXDH_GDMA_DEFAULT_BURST_LEN 0xf /* 16 beats */
+#define ZXDH_GDMA_TC_CNT_ENABLE (1 << 27)
#define ZXDH_GDMA_CHAN_FORCE_CLOSE (1 << 31)
/* TC count & Error interrupt status register */
@@ -66,9 +90,15 @@
#define ZXDH_GDMA_TC_CNT_CLEAN (1)
#define ZXDH_GDMA_CHAN_SHIFT 0x80
+#define ZXDH_GDMA_LINK_END_NODE (1 << 30)
+#define ZXDH_GDMA_CHAN_CONTINUE (1)
+
#define LOW32_MASK 0xffffffff
#define LOW16_MASK 0xffff
+#define IDX_TO_ADDR(addr, idx, t) \
+ ((t)((uintptr_t)(addr) + (idx) * sizeof(struct zxdh_gdma_buff_desc)))
+
static int zxdh_gdma_queue_init(struct rte_rawdev *dev, uint16_t queue_id);
static int zxdh_gdma_queue_free(struct rte_rawdev *dev, uint16_t queue_id);
@@ -316,6 +346,194 @@ zxdh_gdma_rawdev_get_attr(struct rte_rawdev *dev,
return 0;
}
+
+static inline void
+zxdh_gdma_control_cal(uint *val, uint8_t tc_enable)
+{
+ *val = (ZXDH_GDMA_CHAN_ENABLE |
+ ZXDH_GDMA_SOFT_CHAN |
+ (ZXDH_GDMA_DEFAULT_BURST_LEN << ZXDH_GDMA_SBL_SHIFT) |
+ (ZXDH_GDMA_BURST_SIZE_MAX << ZXDH_GDMA_SBS_SHIFT) |
+ (ZXDH_GDMA_BURST_SIZE_MAX << ZXDH_GDMA_DBS_SHIFT));
+
+ if (tc_enable != 0)
+ *val |= ZXDH_GDMA_TC_CNT_ENABLE;
+}
+
+static inline uint
+zxdh_gdma_user_get(struct zxdh_gdma_queue *queue, struct zxdh_gdma_job *job)
+{
+ uint src_user = 0;
+ uint dst_user = 0;
+
+ if ((job->flags & ZXDH_GDMA_JOB_DIR_MASK) == 0) {
+ ZXDH_PMD_LOG(DEBUG, "job flags:0x%x default user:0x%x",
+ job->flags, queue->user);
+ return queue->user;
+ } else if ((job->flags & ZXDH_GDMA_JOB_DIR_TX) != 0) {
+ src_user = ZXDH_GDMA_ZF_USER;
+ dst_user = ((job->pf_id << ZXDH_GDMA_PF_NUM_SHIFT) |
+ ((job->ep_id + ZXDH_GDMA_EPID_OFFSET) << ZXDH_GDMA_EP_ID_SHIFT));
+
+ if (job->vf_id != 0)
+ dst_user |= (ZXDH_GDMA_VF_EN |
+ ((job->vf_id - 1) << ZXDH_GDMA_VF_NUM_SHIFT));
+ } else {
+ dst_user = ZXDH_GDMA_ZF_USER;
+ src_user = ((job->pf_id << ZXDH_GDMA_PF_NUM_SHIFT) |
+ ((job->ep_id + ZXDH_GDMA_EPID_OFFSET) << ZXDH_GDMA_EP_ID_SHIFT));
+
+ if (job->vf_id != 0)
+ src_user |= (ZXDH_GDMA_VF_EN |
+ ((job->vf_id - 1) << ZXDH_GDMA_VF_NUM_SHIFT));
+ }
+ ZXDH_PMD_LOG(DEBUG, "job flags:0x%x ep_id:%u, pf_id:%u, vf_id:%u, user:0x%x",
+ job->flags, job->ep_id, job->pf_id, job->vf_id,
+ (src_user & LOW16_MASK) | (dst_user << 16));
+
+ return (src_user & LOW16_MASK) | (dst_user << 16);
+}
+
+static inline void
+zxdh_gdma_fill_bd(struct zxdh_gdma_queue *queue, struct zxdh_gdma_job *job)
+{
+ struct zxdh_gdma_buff_desc *bd = NULL;
+ uint val = 0;
+ uint64_t next_bd_addr = 0;
+ uint16_t avail_idx = 0;
+
+ avail_idx = queue->ring.avail_idx;
+ bd = &(queue->ring.desc[avail_idx]);
+ memset(bd, 0, sizeof(struct zxdh_gdma_buff_desc));
+
+ /* data bd */
+ if (job != NULL) {
+ zxdh_gdma_control_cal(&val, 1);
+ next_bd_addr = IDX_TO_ADDR(queue->ring.ring_mem,
+ (avail_idx + 1) % ZXDH_GDMA_RING_SIZE,
+ uint64_t);
+ bd->SrcAddr_L = job->src & LOW32_MASK;
+ bd->DstAddr_L = job->dest & LOW32_MASK;
+ bd->SrcAddr_H = (job->src >> 32) & LOW32_MASK;
+ bd->DstAddr_H = (job->dest >> 32) & LOW32_MASK;
+ bd->Xpara = job->len;
+ bd->ExtAddr = zxdh_gdma_user_get(queue, job);
+ bd->LLI_Addr_L = (next_bd_addr >> 6) & LOW32_MASK;
+ bd->LLI_Addr_H = next_bd_addr >> 38;
+ bd->LLI_User = ZXDH_GDMA_ZF_USER;
+ bd->Control = val;
+ } else {
+ zxdh_gdma_control_cal(&val, 0);
+ next_bd_addr = IDX_TO_ADDR(queue->ring.ring_mem, avail_idx, uint64_t);
+ bd->ExtAddr = queue->user;
+ bd->LLI_User = ZXDH_GDMA_ZF_USER;
+ bd->Control = val;
+ bd->LLI_Addr_L = (next_bd_addr >> 6) & LOW32_MASK;
+ bd->LLI_Addr_H = (next_bd_addr >> 38) | ZXDH_GDMA_LINK_END_NODE;
+ if (queue->flag != 0) {
+ bd = IDX_TO_ADDR(queue->ring.desc,
+ queue->ring.last_avail_idx,
+ struct zxdh_gdma_buff_desc*);
+ next_bd_addr = IDX_TO_ADDR(queue->ring.ring_mem,
+ (queue->ring.last_avail_idx + 1) % ZXDH_GDMA_RING_SIZE,
+ uint64_t);
+ bd->LLI_Addr_L = (next_bd_addr >> 6) & LOW32_MASK;
+ bd->LLI_Addr_H = next_bd_addr >> 38;
+ rte_wmb();
+ bd->LLI_Addr_H &= ~ZXDH_GDMA_LINK_END_NODE;
+ }
+ /* Record the index of empty bd for dynamic chaining */
+ queue->ring.last_avail_idx = avail_idx;
+ }
+
+ if (++avail_idx >= ZXDH_GDMA_RING_SIZE)
+ avail_idx -= ZXDH_GDMA_RING_SIZE;
+
+ queue->ring.avail_idx = avail_idx;
+}
+
+static int
+zxdh_gdma_rawdev_enqueue_bufs(struct rte_rawdev *dev,
+ __rte_unused struct rte_rawdev_buf **buffers,
+ uint count,
+ rte_rawdev_obj_t context)
+{
+ struct zxdh_gdma_rawdev *gdmadev = NULL;
+ struct zxdh_gdma_queue *queue = NULL;
+ struct zxdh_gdma_enqdeq *e_context = NULL;
+ struct zxdh_gdma_job *job = NULL;
+ uint16_t queue_id = 0;
+ uint val = 0;
+ uint16_t i = 0;
+ uint16_t free_cnt = 0;
+
+ if (dev == NULL)
+ return -EINVAL;
+
+ if (unlikely((count < 1) || (context == NULL)))
+ return -EINVAL;
+
+ gdmadev = zxdh_gdma_rawdev_get_priv(dev);
+ if (gdmadev->device_state == ZXDH_GDMA_DEV_STOPPED) {
+ ZXDH_PMD_LOG(ERR, "gdma dev is stop");
+ return 0;
+ }
+
+ e_context = (struct zxdh_gdma_enqdeq *)context;
+ queue_id = e_context->vq_id;
+ queue = zxdh_gdma_get_queue(dev, queue_id);
+ if ((queue == NULL) || (queue->enable == 0))
+ return -EINVAL;
+
+ free_cnt = queue->sw_ring.free_cnt;
+ if (free_cnt == 0) {
+ ZXDH_PMD_LOG(ERR, "queue %u is full, enq_idx:%u deq_idx:%u used_idx:%u",
+ queue_id, queue->sw_ring.enq_idx,
+ queue->sw_ring.deq_idx, queue->sw_ring.used_idx);
+ return 0;
+ } else if (free_cnt < count) {
+ ZXDH_PMD_LOG(DEBUG, "job num %u > free_cnt, change to %u", count, free_cnt);
+ count = free_cnt;
+ }
+
+ rte_spinlock_lock(&queue->enqueue_lock);
+
+ /* Build bd list, the last bd is empty bd */
+ for (i = 0; i < count; i++) {
+ job = e_context->job[i];
+ zxdh_gdma_fill_bd(queue, job);
+ }
+ zxdh_gdma_fill_bd(queue, NULL);
+
+ if (unlikely(queue->flag == 0)) {
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_LLI_L_OFFSET,
+ (queue->ring.ring_mem >> 6) & LOW32_MASK);
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_LLI_H_OFFSET,
+ queue->ring.ring_mem >> 38);
+ /* Start hardware handling */
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_XFERSIZE_OFFSET, 0);
+ zxdh_gdma_control_cal(&val, 0);
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_CONTROL_OFFSET, val);
+ queue->flag = 1;
+ } else {
+ val = ZXDH_GDMA_CHAN_CONTINUE;
+ zxdh_gdma_write_reg(dev, queue->vq_id, ZXDH_GDMA_CHAN_CONTINUE_OFFSET, val);
+ }
+
+ /* job enqueue */
+ for (i = 0; i < count; i++) {
+ queue->sw_ring.job[queue->sw_ring.enq_idx] = e_context->job[i];
+ if (++queue->sw_ring.enq_idx >= queue->queue_size)
+ queue->sw_ring.enq_idx -= queue->queue_size;
+
+ free_cnt--;
+ }
+ queue->sw_ring.free_cnt = free_cnt;
+ queue->sw_ring.pend_cnt += count;
+ rte_spinlock_unlock(&queue->enqueue_lock);
+
+ return count;
+}
static const struct rte_rawdev_ops zxdh_gdma_rawdev_ops = {
.dev_info_get = zxdh_gdma_rawdev_info_get,
.dev_configure = zxdh_gdma_rawdev_configure,
@@ -328,6 +546,8 @@ static const struct rte_rawdev_ops zxdh_gdma_rawdev_ops = {
.queue_release = zxdh_gdma_rawdev_queue_release,
.attr_get = zxdh_gdma_rawdev_get_attr,
+
+ .enqueue_bufs = zxdh_gdma_rawdev_enqueue_bufs,
};
static int
diff --git a/drivers/raw/zxdh/zxdh_rawdev.h b/drivers/raw/zxdh/zxdh_rawdev.h
index b4e923261d..643c8be593 100644
--- a/drivers/raw/zxdh/zxdh_rawdev.h
+++ b/drivers/raw/zxdh/zxdh_rawdev.h
@@ -26,6 +26,20 @@ extern int zxdh_gdma_rawdev_logtype;
#define ZXDH_GDMA_QUEUE_SIZE 16384
#define ZXDH_GDMA_RING_SIZE 32768
+/* States if the source addresses is physical. */
+#define ZXDH_GDMA_JOB_SRC_PHY (1UL)
+
+/* States if the destination addresses is physical. */
+#define ZXDH_GDMA_JOB_DEST_PHY (1UL << 1)
+
+/* ZF->HOST */
+#define ZXDH_GDMA_JOB_DIR_TX (1UL << 2)
+
+/* HOST->ZF */
+#define ZXDH_GDMA_JOB_DIR_RX (1UL << 3)
+
+#define ZXDH_GDMA_JOB_DIR_MASK (ZXDH_GDMA_JOB_DIR_TX | ZXDH_GDMA_JOB_DIR_RX)
+
enum zxdh_gdma_device_state {
ZXDH_GDMA_DEV_RUNNING,
ZXDH_GDMA_DEV_STOPPED
@@ -102,6 +116,11 @@ struct zxdh_gdma_rawdev {
struct zxdh_gdma_queue vqs[ZXDH_GDMA_TOTAL_CHAN_NUM];
};
+struct zxdh_gdma_enqdeq {
+ uint16_t vq_id;
+ struct zxdh_gdma_job **job;
+};
+
struct zxdh_gdma_config {
uint16_t max_hw_queues_per_core;
uint16_t max_vqs;
--
2.43.0
[-- Attachment #1.1.2: Type: text/html , Size: 28488 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread* [v1,5/5] raw/zxdh: add support for dequeue operation
2024-08-05 13:34 [v1,1/5] raw/zxdh: introduce zxdh raw device driver Yong Zhang
` (2 preceding siblings ...)
2024-08-05 13:35 ` [v1,4/5] raw/zxdh: add support for enqueue operation Yong Zhang
@ 2024-08-05 13:35 ` Yong Zhang
2024-08-05 15:45 ` [v1,1/5] raw/zxdh: introduce zxdh raw device driver Stephen Hemminger
4 siblings, 0 replies; 7+ messages in thread
From: Yong Zhang @ 2024-08-05 13:35 UTC (permalink / raw)
To: dev; +Cc: Yong Zhang
[-- Attachment #1.1.1: Type: text/plain, Size: 4708 bytes --]
Add rawdev dequeue operation for zxdh devices.
Signed-off-by: Yong Zhang <zhang.yong25@zte.com.cn>
---
drivers/raw/zxdh/zxdh_rawdev.c | 113 +++++++++++++++++++++++++++++++++
1 file changed, 113 insertions(+)
diff --git a/drivers/raw/zxdh/zxdh_rawdev.c b/drivers/raw/zxdh/zxdh_rawdev.c
index 76b8f7f728..2019bd3704 100644
--- a/drivers/raw/zxdh/zxdh_rawdev.c
+++ b/drivers/raw/zxdh/zxdh_rawdev.c
@@ -96,6 +96,8 @@
#define LOW32_MASK 0xffffffff
#define LOW16_MASK 0xffff
+#define ZXDH_GDMA_TC_CNT_MAX 0x10000
+
#define IDX_TO_ADDR(addr, idx, t) \
((t)((uintptr_t)(addr) + (idx) * sizeof(struct zxdh_gdma_buff_desc)))
@@ -534,6 +536,116 @@ zxdh_gdma_rawdev_enqueue_bufs(struct rte_rawdev *dev,
return count;
}
+
+static inline void
+zxdh_gdma_used_idx_update(struct zxdh_gdma_queue *queue, uint16_t cnt, uint8_t data_bd_err)
+{
+ uint16_t idx = 0;
+
+ if (queue->sw_ring.used_idx + cnt < queue->queue_size)
+ queue->sw_ring.used_idx += cnt;
+ else
+ queue->sw_ring.used_idx = queue->sw_ring.used_idx + cnt - queue->queue_size;
+
+ if (data_bd_err == 1) {
+ /* Update job status, the last job status is error */
+ if (queue->sw_ring.used_idx == 0)
+ idx = queue->queue_size - 1;
+ else
+ idx = queue->sw_ring.used_idx - 1;
+
+ queue->sw_ring.job[idx]->status = 1;
+ }
+}
+
+static int
+zxdh_gdma_rawdev_dequeue_bufs(struct rte_rawdev *dev,
+ __rte_unused struct rte_rawdev_buf **buffers,
+ uint count,
+ rte_rawdev_obj_t context)
+{
+ struct zxdh_gdma_queue *queue = NULL;
+ struct zxdh_gdma_enqdeq *e_context = NULL;
+ uint16_t queue_id = 0;
+ uint val = 0;
+ uint16_t tc_cnt = 0;
+ uint16_t diff_cnt = 0;
+ uint16_t i = 0;
+ uint16_t bd_idx = 0;
+ uint64_t next_bd_addr = 0;
+ uint8_t data_bd_err = 0;
+
+ if ((dev == NULL) || (context == NULL))
+ return -EINVAL;
+
+ e_context = (struct zxdh_gdma_enqdeq *)context;
+ queue_id = e_context->vq_id;
+ queue = zxdh_gdma_get_queue(dev, queue_id);
+ if ((queue == NULL) || (queue->enable == 0))
+ return -EINVAL;
+
+ if (queue->sw_ring.pend_cnt == 0)
+ goto deq_job;
+
+ /* Get data transmit count */
+ val = zxdh_gdma_read_reg(dev, queue_id, ZXDH_GDMA_TC_CNT_OFFSET);
+ tc_cnt = val & LOW16_MASK;
+ if (tc_cnt >= queue->tc_cnt)
+ diff_cnt = tc_cnt - queue->tc_cnt;
+ else
+ diff_cnt = tc_cnt + ZXDH_GDMA_TC_CNT_MAX - queue->tc_cnt;
+
+ queue->tc_cnt = tc_cnt;
+
+ /* Data transmit error, channel stopped */
+ if ((val & ZXDH_GDMA_ERR_STATUS) != 0) {
+ next_bd_addr = zxdh_gdma_read_reg(dev, queue_id, ZXDH_GDMA_LLI_L_OFFSET);
+ next_bd_addr |= ((uint64_t)zxdh_gdma_read_reg(dev, queue_id,
+ ZXDH_GDMA_LLI_H_OFFSET) << 32);
+ next_bd_addr = next_bd_addr << 6;
+ bd_idx = (next_bd_addr - queue->ring.ring_mem) / sizeof(struct zxdh_gdma_buff_desc);
+ if ((val & ZXDH_GDMA_SRC_DATA_ERR) || (val & ZXDH_GDMA_DST_ADDR_ERR)) {
+ diff_cnt++;
+ data_bd_err = 1;
+ }
+ ZXDH_PMD_LOG(INFO, "queue%d is err(0x%x) next_bd_idx:%u ll_addr:0x%"PRIx64" def user:0x%x",
+ queue_id, val, bd_idx, next_bd_addr, queue->user);
+
+ ZXDH_PMD_LOG(INFO, "Clean up error status");
+ val = ZXDH_GDMA_ERR_STATUS | ZXDH_GDMA_ERR_INTR_ENABLE;
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_TC_CNT_OFFSET, val);
+
+ ZXDH_PMD_LOG(INFO, "Restart channel");
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_XFERSIZE_OFFSET, 0);
+ zxdh_gdma_control_cal(&val, 0);
+ zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_CONTROL_OFFSET, val);
+ }
+
+ if (diff_cnt != 0) {
+ zxdh_gdma_used_idx_update(queue, diff_cnt, data_bd_err);
+ queue->sw_ring.deq_cnt += diff_cnt;
+ queue->sw_ring.pend_cnt -= diff_cnt;
+ }
+
+deq_job:
+ if (queue->sw_ring.deq_cnt == 0)
+ return 0;
+ else if (queue->sw_ring.deq_cnt < count)
+ count = queue->sw_ring.deq_cnt;
+
+ queue->sw_ring.deq_cnt -= count;
+
+ for (i = 0; i < count; i++) {
+ e_context->job[i] = queue->sw_ring.job[queue->sw_ring.deq_idx];
+ queue->sw_ring.job[queue->sw_ring.deq_idx] = NULL;
+ if (++queue->sw_ring.deq_idx >= queue->queue_size)
+ queue->sw_ring.deq_idx -= queue->queue_size;
+ }
+ queue->sw_ring.free_cnt += count;
+
+ return count;
+}
+
static const struct rte_rawdev_ops zxdh_gdma_rawdev_ops = {
.dev_info_get = zxdh_gdma_rawdev_info_get,
.dev_configure = zxdh_gdma_rawdev_configure,
@@ -548,6 +660,7 @@ static const struct rte_rawdev_ops zxdh_gdma_rawdev_ops = {
.attr_get = zxdh_gdma_rawdev_get_attr,
.enqueue_bufs = zxdh_gdma_rawdev_enqueue_bufs,
+ .dequeue_bufs = zxdh_gdma_rawdev_dequeue_bufs,
};
static int
--
2.43.0
[-- Attachment #1.1.2: Type: text/html , Size: 11309 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [v1,1/5] raw/zxdh: introduce zxdh raw device driver
2024-08-05 13:34 [v1,1/5] raw/zxdh: introduce zxdh raw device driver Yong Zhang
` (3 preceding siblings ...)
2024-08-05 13:35 ` [v1,5/5] raw/zxdh: add support for dequeue operation Yong Zhang
@ 2024-08-05 15:45 ` Stephen Hemminger
2024-08-12 6:40 ` zhang.yong25
4 siblings, 1 reply; 7+ messages in thread
From: Stephen Hemminger @ 2024-08-05 15:45 UTC (permalink / raw)
To: Yong Zhang; +Cc: dev
On Mon, 5 Aug 2024 21:34:53 +0800
Yong Zhang <zhang.yong25@zte.com.cn> wrote:
> +struct zxdh_gdma_buff_desc {
> + uint SrcAddr_L;
> + uint DstAddr_L;
> + uint Xpara;
> + uint ZY_para;
> + uint ZY_SrcStep;
> + uint ZY_DstStep;
> + uint ExtAddr;
> + uint LLI_Addr_L;
> + uint LLI_Addr_H;
> + uint ChCont;
> + uint LLI_User;
> + uint ErrAddr;
> + uint Control;
> + uint SrcAddr_H;
> + uint DstAddr_H;
> + uint Reserved;
> +};
> +
Why is this driver using uint type?
It should be using datatypes with explicit size (like uint32_t) to
make sure it can be used on both 32 and 64 bit builds.
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [v1,1/5] raw/zxdh: introduce zxdh raw device driver
2024-08-05 15:45 ` [v1,1/5] raw/zxdh: introduce zxdh raw device driver Stephen Hemminger
@ 2024-08-12 6:40 ` zhang.yong25
0 siblings, 0 replies; 7+ messages in thread
From: zhang.yong25 @ 2024-08-12 6:40 UTC (permalink / raw)
To: stephen; +Cc: dev
[-- Attachment #1.1.1: Type: text/plain, Size: 1507 bytes --]
>> +struct zxdh_gdma_buff_desc {>> + uint SrcAddr_L;>> + uint DstAddr_L;>> + uint Xpara;>> + uint ZY_para;>> + uint ZY_SrcStep;>> + uint ZY_DstStep;>> + uint ExtAddr;>> + uint LLI_Addr_L;>> + uint LLI_Addr_H;>> + uint ChCont;>> + uint LLI_User;>> + uint ErrAddr;>> + uint Control;>> + uint SrcAddr_H;>> + uint DstAddr_H;>> + uint Reserved;>> +};>> +>Why is this driver using uint type?>It should be using datatypes with explicit size (like uint32_t) to>make sure it can be used on both 32 and 64 bit builds.
This was an oversight, I will fix it as suggested.
Thanks
Original
From: StephenHemminger <stephen@networkplumber.org>
To: 张勇10313449;
Cc: dev@dpdk.org <dev@dpdk.org>;
Date: 2024年08月05日 23:46
Subject: Re: [v1,1/5] raw/zxdh: introduce zxdh raw device driver
On Mon, 5 Aug 2024 21:34:53 +0800
Yong Zhang <zhang.yong25@zte.com.cn> wrote:
> +struct zxdh_gdma_buff_desc {
> + uint SrcAddr_L;
> + uint DstAddr_L;
> + uint Xpara;
> + uint ZY_para;
> + uint ZY_SrcStep;
> + uint ZY_DstStep;
> + uint ExtAddr;
> + uint LLI_Addr_L;
> + uint LLI_Addr_H;
> + uint ChCont;
> + uint LLI_User;
> + uint ErrAddr;
> + uint Control;
> + uint SrcAddr_H;
> + uint DstAddr_H;
> + uint Reserved;
> +};
> +
Why is this driver using uint type?
It should be using datatypes with explicit size (like uint32_t) to
make sure it can be used on both 32 and 64 bit builds.
[-- Attachment #1.1.2: Type: text/html , Size: 11010 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread