From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C04D74575B; Wed, 7 Aug 2024 11:35:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4DCA84114B; Wed, 7 Aug 2024 11:34:36 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by mails.dpdk.org (Postfix) with ESMTP id 3802D40E5E for ; Wed, 7 Aug 2024 11:34:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723023266; x=1754559266; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PuI8ws8QZpu20EpZEZTMXgmWpEspJN7UcXGSE6TqDfI=; b=cGE0rpN87BuLf3uDyjyzqUsI1xXgbRgsWKhMSMLdhDK7WalwFnJkjMtT 7u5GxjLJVSlJu2G5FE9rbrN5hqUUmdBk2aarddkWHReAbEoIlx4Wl5QtQ Yt3geAGowBjFySMjbR3EO12M7Ue+8ZDp/oaoHjHH5JxzfuaKFw8Pr3Ce0 2jxBsaeQ22tN1hQnjEWMBhVK2988Ff/NkLV/3FTofLlYi5l/nemF0xu/q MLWjT9oL3myGSk9BsgbMItbdaZjoefI5oswN6jHOnlwUYxAqSuKxDSZXl qEZurymC/IrcIiKSkjncpOLo9eV/rFs9SyOjSHrT7z3xLxuep8cf8B9OO Q==; X-CSE-ConnectionGUID: Y2PdQP87R/aEMOFiYfXtQA== X-CSE-MsgGUID: WooohjXaRyyqxfJ7jEW+9A== X-IronPort-AV: E=McAfee;i="6700,10204,11156"; a="12897963" X-IronPort-AV: E=Sophos;i="6.09,269,1716274800"; d="scan'208";a="12897963" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2024 02:34:26 -0700 X-CSE-ConnectionGUID: HoWfKW6SQjGW6LtgcWHqiA== X-CSE-MsgGUID: rLBkuQz1RwOgLQJMVugdGw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,269,1716274800"; d="scan'208";a="87731037" Received: from silpixa00400562.ir.intel.com (HELO silpixa00401385.ir.intel.com) ([10.237.214.39]) by fmviesa001.fm.intel.com with ESMTP; 07 Aug 2024 02:34:25 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: Bruce Richardson Subject: [PATCH 13/15] net/ice: limit the number of queues to sched capabilities Date: Wed, 7 Aug 2024 10:34:05 +0100 Message-ID: <20240807093407.452784-14-bruce.richardson@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240807093407.452784-1-bruce.richardson@intel.com> References: <20240807093407.452784-1-bruce.richardson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Rather than assuming that each VSI can hold up to 256 queue pairs, or the reported device limit, query the available nodes in the scheduler tree to check that we are not overflowing the limit for number of child scheduling nodes at each level. Do this by multiplying max_children for each level beyond the VSI and using that as an additional cap on the number of queues. Signed-off-by: Bruce Richardson --- drivers/net/ice/ice_ethdev.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 0d2445a317..ab3f88fd7d 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -913,7 +913,7 @@ ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) } static int -ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, +ice_vsi_config_tc_queue_mapping(struct ice_hw *hw, struct ice_vsi *vsi, struct ice_aqc_vsi_props *info, uint8_t enabled_tcmap) { @@ -929,13 +929,28 @@ ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, } /* vector 0 is reserved and 1 vector for ctrl vsi */ - if (vsi->adapter->hw.func_caps.common_cap.num_msix_vectors < 2) + if (vsi->adapter->hw.func_caps.common_cap.num_msix_vectors < 2) { vsi->nb_qps = 0; - else + } else { vsi->nb_qps = RTE_MIN ((uint16_t)vsi->adapter->hw.func_caps.common_cap.num_msix_vectors - 2, RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC)); + /* cap max QPs to what the HW reports as num-children for each layer. + * Multiply num_children for each layer from the entry_point layer to + * the qgroup, or second-last layer. + * Avoid any potential overflow by using uint32_t type and breaking loop + * once we have a number greater than the already configured max. + */ + uint32_t max_sched_vsi_nodes = 1; + for (uint8_t i = hw->sw_entry_point_layer; i < hw->num_tx_sched_layers - 1; i++) { + max_sched_vsi_nodes *= hw->max_children[i]; + if (max_sched_vsi_nodes >= vsi->nb_qps) + break; + } + vsi->nb_qps = RTE_MIN(vsi->nb_qps, max_sched_vsi_nodes); + } + /* nb_qps(hex) -> fls */ /* 0000 -> 0 */ /* 0001 -> 0 */ @@ -1707,7 +1722,7 @@ ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort); /* Enable VLAN/UP trip */ - ret = ice_vsi_config_tc_queue_mapping(vsi, + ret = ice_vsi_config_tc_queue_mapping(hw, vsi, &vsi_ctx.info, ICE_DEFAULT_TCMAP); if (ret) { @@ -1731,7 +1746,7 @@ ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); vsi_ctx.info.sw_id = hw->port_info->sw_id; vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; - ret = ice_vsi_config_tc_queue_mapping(vsi, + ret = ice_vsi_config_tc_queue_mapping(hw, vsi, &vsi_ctx.info, ICE_DEFAULT_TCMAP); if (ret) { -- 2.43.0