From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D3B2345777; Fri, 9 Aug 2024 11:14:50 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9B45B42E8F; Fri, 9 Aug 2024 11:14:24 +0200 (CEST) Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2041.outbound.protection.outlook.com [40.107.104.41]) by mails.dpdk.org (Postfix) with ESMTP id 7CDB142E46 for ; Fri, 9 Aug 2024 11:14:19 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=g5IZxPIGBYUlJ3t3/KdK9pPKkLtzJF29JiWxu0OPan2G+KbQyJmZITigpKInxliGyBVTjbINZisLrkAuhkZ+0TG1NWGXl4bYTxhVoU1DXKdCpYcejQTB7J5yhJC1OtfiqLcLOOaHjslxloKU3qme32CKkFkp3kgmIRweyFODTi8C/MNnwfWQ3DF1VLx+xRKeEZNj5E6UyVEMDi8fJjPx93ujXL6fIKFusonJ8HLG0qG3Ld+caJZZnGFmG1OPr80RSsoqMB4Ht970PLU8N47grz4yYZH3g1TQhJPtuqs0Pl5bIZwR27Vo5HVblT07YhXK3/+nRC4eLEzeo90DQ5SdSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bpTu1BJa9LiTtAkdxe9Wxu7Fs/6r2nSAYg7gg++Hfp8=; b=FMd3QiWfiipeTyvg8om0rWEM5rXOINg+XeBFqjyF7yC0s8KYqq6Wb2G+VH8WF9NzDsYmdCmh+1BfQ71ybYXSN44VkZRI4sOqCobSx1IT2NK3d2xkT9O9WI0V5tgoVfGUbmw8cqZOsY+n+tDGvvncNFDKtFpTO4sUQby09x2cLyVYQlFWxR+gFg2Aqh4R5B3yxweo3rcTgdwFkOm2JaotcK78iPc+jxrY1G+oJHtalVwVfcqspUNjIznuO7DXybbfyS30kYWZXa2MGDdP6e3StKZB5ES5CAGmXEeWlDfFWwMM9EHhDri7m34npujnmRP8WgrLwBEw1mHJ5Hlun9xhHQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=arm.com smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bpTu1BJa9LiTtAkdxe9Wxu7Fs/6r2nSAYg7gg++Hfp8=; b=SwgbNq2JaGGBAblgkvUB3NnVLUdC9N1uZp51UmyeiMSqC8atBwYNLHE4gBRWPCkcQESp3br/IUWal/YYHkQzCgZR145pzBCFvH2rG6VEdZP7ng/R1aE+vAdoExmTVmbXH0uNWGD/BIahmHflbJ/6kjsSmukk7QtAaNtNgLkSSlaxQrzDVFdB2SwFuHVgV9Tyeq6Tx18FLegKewdjcmRPrej9UDg5kjn+McTFnWnZM9+OfAn0cf7gqJuYdzRNwfmlIPn40+O8eAh4AFDocv4nU8G9RbSwrY4NIs/+STahEb7CmNzUU6aElTPFPCNMpFyx8uEhoMDQMTkUFCoK9tHAFw== Received: from PR1P264CA0140.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:2ce::8) by AS8PR07MB7383.eurprd07.prod.outlook.com (2603:10a6:20b:2ab::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.15; Fri, 9 Aug 2024 09:14:16 +0000 Received: from AM4PEPF00025F96.EURPRD83.prod.outlook.com (2603:10a6:102:2ce:cafe::8d) by PR1P264CA0140.outlook.office365.com (2603:10a6:102:2ce::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.14 via Frontend Transport; Fri, 9 Aug 2024 09:14:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by AM4PEPF00025F96.mail.protection.outlook.com (10.167.16.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7875.2 via Frontend Transport; Fri, 9 Aug 2024 09:14:16 +0000 Received: from seliicinfr00050.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.67) with Microsoft SMTP Server id 15.2.1544.11; Fri, 9 Aug 2024 11:14:15 +0200 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00050.seli.gic.ericsson.se (Postfix) with ESMTP id A4F141C0070; Fri, 9 Aug 2024 11:14:15 +0200 (CEST) From: =?UTF-8?q?Mattias=20R=C3=B6nnblom?= To: CC: , Heng Wang , "Stephen Hemminger" , Joyce Kong , Tyler Retzlaff , =?UTF-8?q?Morten=20Br=C3=B8rup?= , =?UTF-8?q?Mattias=20R=C3=B6nnblom?= Subject: [PATCH 3/5] eal: add atomic bit operations Date: Fri, 9 Aug 2024 11:04:37 +0200 Message-ID: <20240809090439.589295-4-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240809090439.589295-1-mattias.ronnblom@ericsson.com> References: <20240505083737.118649-2-mattias.ronnblom@ericsson.com> <20240809090439.589295-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00025F96:EE_|AS8PR07MB7383:EE_ X-MS-Office365-Filtering-Correlation-Id: c7dccf88-df58-4055-3761-08dcb853a4bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?QUowVnNyczB5bnBuT0lGWGsyaGJpalo5Z3o4bjZyZHJrWmZHR0lvRENiK3Vi?= =?utf-8?B?eEZiU1RLV0hSNTlUTEpLalJ3VUpiVEFjWXk4b3htdjdRczhpZThabm9aOUsz?= =?utf-8?B?alYxYktLSm1iaGcxaXN4KzllZTJtMHV5cWlOZHgxMGRTKzY3blRNY3hHemgz?= =?utf-8?B?U0xLQ0RNWXJwbnQzejhUWVd2dU5qdmhvdUdFOXdoUkVoQzBMaGdGZjBnVFlI?= =?utf-8?B?RVUveTRJaUxVdy9Qdm4wR2pxSFhuRGkrb1I5b0trMDY3MUNUcytidTJoZjB2?= =?utf-8?B?cTl4dU9LZWRsREZHeUlENSt5U2ZCMkxzajdESlZnbEhjQXFsSWdVNTlSb1ow?= =?utf-8?B?NUVRSU5OWFdFSmNjRnNMUHVTY0E4NnJFVUdzU1k1bFIzc0drN3pnL0hnYi95?= =?utf-8?B?b0VmS1J2U1U3a1c5dmgvT2NMM3RhOUFVcXZiSklhMXdiekxrMHJzNU9lN0gv?= =?utf-8?B?dWMrUHdZcmhCMGYwWmFFSFpFblpUUVZFMVVvbXF5NlBobEVvUzFaampMaWJR?= =?utf-8?B?RXFWeU5OcU92MnUyNlV6QS9LcHNodGhUT3FySmFiaVk0bDdsbmU4SExRVTBu?= =?utf-8?B?VkZYWllJNFhBSW1BNEI2Tk1xNnVMeWh0b09yK2x4cnJNSk9RdXcyRlMzT3Zq?= =?utf-8?B?UUJYbFlkbEIyTkJPOUpDaFBsaVZQYUVaS29TT3JRa1VESXR5Unp3aEJvT284?= =?utf-8?B?STQyNTVxYXd4ZTlEazhwdEJUTi9FcW12ckIxNXU1bE5QS2ZScDNzcjQ5MmRJ?= =?utf-8?B?Sm5kcW1NTVE4Zm1xQS81bmM3U2wxUWJQdWhoaUU2VkcyVXJBQ05rMmtHeE9R?= =?utf-8?B?eUdOTFR6Mkx3U0hqaXNBVmRDV2NQYVdqb09qbk1nZkJsUnR6eGI0cmRTdFUz?= =?utf-8?B?RTI1SWVGeU92L1FBcmdqZW9YYjB1emZrME1DcXZtdzFnbUtaVDJFYk5pZGF4?= =?utf-8?B?cVgvL0xqMkZUZ0NOMmE0Q2tuaXN4TzlYL3BhWTRpUkV4dThZcGJ4VEk5MG5z?= =?utf-8?B?U3ZZM3VDdXRqSEhLZkhjbEk5dWFMNWl3c0JoclVrMFFUTzczSnB0WHd6NHhV?= =?utf-8?B?c08vYUxSMlROZkwyQjZEcUtYZU5QYkFLZ3kwbmM0ZnIxSmdhd1g1UW05SUlF?= =?utf-8?B?K2NqelYxSVhLQzYwWGUvdWZZak91SEhuc2tyM0dwUWZXVnVLYTdXU1pSSW5k?= =?utf-8?B?cERsUWZSS0lhTnh0K3pJYkhrU3IrVDhyYk5JVjl3cnJTT2MzMXNxRDJJdGFh?= =?utf-8?B?OUJqbmR0NWU0MHAwbVpZR2NJWVpEK2JQVkxGZWk3SXUwOFJ3djNzdCtpVnlK?= =?utf-8?B?MDYrU3VyZHFkTmtNT0M1U3Npak8rVGNGa0lMSWVyR0ZKUmQwWmdTTnhYT29o?= =?utf-8?B?YjhhekhkUTVyaDRZQk5oRFN3Yk9CY0krL0RNYkcrbzMxZSt6dUpsUldLYUlt?= =?utf-8?B?VmdQQVZ4SnVQbU5DeHZVNndXMTUvK3ZvME9EYVZlV2J6Y2RaREdXS2hyZm5k?= =?utf-8?B?N2xFOHBMeE5ZUXJpM3p5K0pacy9KZUkvSU5Qbmd4eEx0cVpOSUU5eENoL05z?= =?utf-8?B?dzl5ZGpGRWh5a3dEdWpCYlZkSlg0RDYvSnoxaThkcG5lVjJVZG9HS1hLQWox?= =?utf-8?B?RFIrb2xqc2tGRVpFOWUzaDVBbEpJa1dOSFVpSGVkOVhucTJxaDNNRUtqWmJR?= =?utf-8?B?bnFaSC90YldXN3VDbXJVU0RhRlZudSs4NjltcVhPRFYrYkRsajFBQ0VuQ3NX?= =?utf-8?B?Y0djcmwrdXlRV29meVp3eEhyQVU1SXhROUVxbzBoY0hOT3RHZnBXYi9EdHVt?= =?utf-8?B?Y200K2hDc3RYT21na015YkFIS3JNdXBHcWE0cjdnUkxOYmxHRXliblZwUkVq?= =?utf-8?B?bm92eGpvbG1jcGh0RWdDOEZHQlNDMjJMTVJ0K25RemovYnc9PQ==?= X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Aug 2024 09:14:16.5090 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c7dccf88-df58-4055-3761-08dcb853a4bf X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00025F96.EURPRD83.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR07MB7383 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add atomic bit test/set/clear/assign/flip and test-and-set/clear/assign/flip functions. All atomic bit functions allow (and indeed, require) the caller to specify a memory order. RFC v8: * Add missing macro #undef for C++ version of atomic bit flip. RFC v7: * Replace compare-exchange-based rte_bitset_atomic_test_and_*() and flip() with implementations that use the previous value as returned by the atomic fetch function. * Reword documentation to match the non-atomic macro variants. * Remove pointer to for memory model documentation, since there is no documentation for that API. RFC v6: * Have rte_bit_atomic_test() accept const-marked bitsets. RFC v4: * Add atomic bit flip. * Mark macro-generated private functions experimental. RFC v3: * Work around lack of C++ support for _Generic (Tyler Retzlaff). RFC v2: o Add rte_bit_atomic_test_and_assign() (for consistency). o Fix bugs in rte_bit_atomic_test_and_[set|clear](). o Use to support MSVC. Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup Acked-by: Tyler Retzlaff --- lib/eal/include/rte_bitops.h | 414 +++++++++++++++++++++++++++++++++++ 1 file changed, 414 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index 3297133e22..4d878099ed 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -21,6 +21,7 @@ #include #include +#include #ifdef __cplusplus extern "C" { @@ -226,6 +227,204 @@ extern "C" { uint32_t *: __rte_bit_flip32, \ uint64_t *: __rte_bit_flip64)(addr, nr) +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Test if a particular bit in a word is set with a particular memory + * order. + * + * Test a bit with the resulting memory load ordered as per the + * specified memory order. + * + * @param addr + * A pointer to the word to query. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. + * @return + * Returns true if the bit is set, and false otherwise. + */ +#define rte_bit_atomic_test(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test32, \ + const uint32_t *: __rte_bit_atomic_test32, \ + uint64_t *: __rte_bit_atomic_test64, \ + const uint64_t *: __rte_bit_atomic_test64)(addr, nr, \ + memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically set bit in word. + * + * Generic selection macro to atomically set bit specified by @c nr in + * the word pointed to by @c addr to '1', with the memory ordering as + * specified by @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. + */ +#define rte_bit_atomic_set(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_set32, \ + uint64_t *: __rte_bit_atomic_set64)(addr, nr, memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically clear bit in word. + * + * Generic selection macro to atomically set bit specified by @c nr in + * the word pointed to by @c addr to '0', with the memory ordering as + * specified by @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. + */ +#define rte_bit_atomic_clear(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_clear32, \ + uint64_t *: __rte_bit_atomic_clear64)(addr, nr, memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically assign a value to bit in word. + * + * Generic selection macro to atomically set bit specified by @c nr in the + * word pointed to by @c addr to the value indicated by @c value, with + * the memory ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + * @param memory_order + * The memory order to use. + */ +#define rte_bit_atomic_assign(addr, nr, value, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_assign32, \ + uint64_t *: __rte_bit_atomic_assign64)(addr, nr, value, \ + memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically flip bit in word. + * + * Generic selection macro to atomically negate the value of the bit + * specified by @c nr in the word pointed to by @c addr to the value + * indicated by @c value, with the memory ordering as specified with + * @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. + */ +#define rte_bit_atomic_flip(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_flip32, \ + uint64_t *: __rte_bit_atomic_flip64)(addr, nr, memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically test and set a bit in word. + * + * Generic selection macro to atomically test and set bit specified by + * @c nr in the word pointed to by @c addr to '1', with the memory + * ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. + * @return + * Returns true if the bit was set, and false otherwise. + */ +#define rte_bit_atomic_test_and_set(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test_and_set32, \ + uint64_t *: __rte_bit_atomic_test_and_set64)(addr, nr, \ + memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically test and clear a bit in word. + * + * Generic selection macro to atomically test and clear bit specified + * by @c nr in the word pointed to by @c addr to '0', with the memory + * ordering as specified with @c memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param memory_order + * The memory order to use. + * @return + * Returns true if the bit was set, and false otherwise. + */ +#define rte_bit_atomic_test_and_clear(addr, nr, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test_and_clear32, \ + uint64_t *: __rte_bit_atomic_test_and_clear64)(addr, nr, \ + memory_order) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Atomically test and assign a bit in word. + * + * Generic selection macro to atomically test and assign bit specified + * by @c nr in the word pointed to by @c addr the value specified by + * @c value, with the memory ordering as specified with @c + * memory_order. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + * @param memory_order + * The memory order to use. + * @return + * Returns true if the bit was set, and false otherwise. + */ +#define rte_bit_atomic_test_and_assign(addr, nr, value, memory_order) \ + _Generic((addr), \ + uint32_t *: __rte_bit_atomic_test_and_assign32, \ + uint64_t *: __rte_bit_atomic_test_and_assign64)(addr, nr, \ + value, \ + memory_order) + #define __RTE_GEN_BIT_TEST(family, fun, qualifier, size) \ __rte_experimental \ static inline bool \ @@ -298,6 +497,145 @@ __RTE_GEN_BIT_CLEAR(, clear,, 64) __RTE_GEN_BIT_ASSIGN(, assign,, 64) __RTE_GEN_BIT_FLIP(, flip,, 64) +#define __RTE_GEN_BIT_ATOMIC_TEST(size) \ + __rte_experimental \ + static inline bool \ + __rte_bit_atomic_test ## size(const uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + const RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (const RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + return rte_atomic_load_explicit(a_addr, memory_order) & mask; \ + } + +#define __RTE_GEN_BIT_ATOMIC_SET(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_set ## size(uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + rte_atomic_fetch_or_explicit(a_addr, mask, memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_CLEAR(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_clear ## size(uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + rte_atomic_fetch_and_explicit(a_addr, ~mask, memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_FLIP(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_flip ## size(uint ## size ## _t *addr, \ + unsigned int nr, int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + rte_atomic_fetch_xor_explicit(a_addr, mask, memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_ASSIGN(size) \ + __rte_experimental \ + static inline void \ + __rte_bit_atomic_assign ## size(uint ## size ## _t *addr, \ + unsigned int nr, bool value, \ + int memory_order) \ + { \ + if (value) \ + __rte_bit_atomic_set ## size(addr, nr, memory_order); \ + else \ + __rte_bit_atomic_clear ## size(addr, nr, \ + memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_TEST_AND_SET(size) \ + __rte_experimental \ + static inline bool \ + __rte_bit_atomic_test_and_set ## size(uint ## size ## _t *addr, \ + unsigned int nr, \ + int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + uint ## size ## _t prev; \ + \ + prev = rte_atomic_fetch_or_explicit(a_addr, mask, \ + memory_order); \ + \ + return prev & mask; \ + } + +#define __RTE_GEN_BIT_ATOMIC_TEST_AND_CLEAR(size) \ + __rte_experimental \ + static inline bool \ + __rte_bit_atomic_test_and_clear ## size(uint ## size ## _t *addr, \ + unsigned int nr, \ + int memory_order) \ + { \ + RTE_ASSERT(nr < size); \ + \ + RTE_ATOMIC(uint ## size ## _t) *a_addr = \ + (RTE_ATOMIC(uint ## size ## _t) *)addr; \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + uint ## size ## _t prev; \ + \ + prev = rte_atomic_fetch_and_explicit(a_addr, ~mask, \ + memory_order); \ + \ + return prev & mask; \ + } + +#define __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size) \ + __rte_experimental \ + static inline bool \ + __rte_bit_atomic_test_and_assign ## size(uint ## size ## _t *addr, \ + unsigned int nr, \ + bool value, \ + int memory_order) \ + { \ + if (value) \ + return __rte_bit_atomic_test_and_set ## size(addr, nr, \ + memory_order); \ + else \ + return __rte_bit_atomic_test_and_clear ## size(addr, nr, \ + memory_order); \ + } + +#define __RTE_GEN_BIT_ATOMIC_OPS(size) \ + __RTE_GEN_BIT_ATOMIC_TEST(size) \ + __RTE_GEN_BIT_ATOMIC_SET(size) \ + __RTE_GEN_BIT_ATOMIC_CLEAR(size) \ + __RTE_GEN_BIT_ATOMIC_ASSIGN(size) \ + __RTE_GEN_BIT_ATOMIC_TEST_AND_SET(size) \ + __RTE_GEN_BIT_ATOMIC_TEST_AND_CLEAR(size) \ + __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size) \ + __RTE_GEN_BIT_ATOMIC_FLIP(size) + +__RTE_GEN_BIT_ATOMIC_OPS(32) +__RTE_GEN_BIT_ATOMIC_OPS(64) + /*------------------------ 32-bit relaxed operations ------------------------*/ /** @@ -993,6 +1331,15 @@ rte_log2_u64(uint64_t v) #undef rte_bit_assign #undef rte_bit_flip +#undef rte_bit_atomic_test +#undef rte_bit_atomic_set +#undef rte_bit_atomic_clear +#undef rte_bit_atomic_assign +#undef rte_bit_atomic_flip +#undef rte_bit_atomic_test_and_set +#undef rte_bit_atomic_test_and_clear +#undef rte_bit_atomic_test_and_assign + #define __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, size, arg1_type, arg1_name) \ static inline void \ rte_bit_ ## fun(qualifier uint ## size ## _t *addr, \ @@ -1036,12 +1383,79 @@ rte_log2_u64(uint64_t v) __RTE_BIT_OVERLOAD_SZ_3(fun, qualifier, 64, arg1_type, arg1_name, \ arg2_type, arg2_name) +#define __RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, size, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name) \ + static inline ret_type \ + rte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name, \ + arg2_type arg2_name) \ + { \ + return __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name); \ + } + +#define __RTE_BIT_OVERLOAD_3R(fun, qualifier, ret_type, arg1_type, arg1_name, \ + arg2_type, arg2_name) \ + __RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, 32, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name) \ + __RTE_BIT_OVERLOAD_SZ_3R(fun, qualifier, 64, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name) + +#define __RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, size, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) \ + static inline void \ + rte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name, \ + arg2_type arg2_name, arg3_type arg3_name) \ + { \ + __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name, \ + arg3_name); \ + } + +#define __RTE_BIT_OVERLOAD_4(fun, qualifier, arg1_type, arg1_name, arg2_type, \ + arg2_name, arg3_type, arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, 32, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4(fun, qualifier, 64, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) + +#define __RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, size, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name, arg3_type, \ + arg3_name) \ + static inline ret_type \ + rte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name, \ + arg2_type arg2_name, arg3_type arg3_name) \ + { \ + return __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name, \ + arg3_name); \ + } + +#define __RTE_BIT_OVERLOAD_4R(fun, qualifier, ret_type, arg1_type, arg1_name, \ + arg2_type, arg2_name, arg3_type, arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, 32, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name, arg3_type, \ + arg3_name) \ + __RTE_BIT_OVERLOAD_SZ_4R(fun, qualifier, 64, ret_type, arg1_type, \ + arg1_name, arg2_type, arg2_name, arg3_type, \ + arg3_name) + __RTE_BIT_OVERLOAD_2R(test, const, bool, unsigned int, nr) __RTE_BIT_OVERLOAD_2(set,, unsigned int, nr) __RTE_BIT_OVERLOAD_2(clear,, unsigned int, nr) __RTE_BIT_OVERLOAD_3(assign,, unsigned int, nr, bool, value) __RTE_BIT_OVERLOAD_2(flip,, unsigned int, nr) +__RTE_BIT_OVERLOAD_3R(atomic_test, const, bool, unsigned int, nr, + int, memory_order) +__RTE_BIT_OVERLOAD_3(atomic_set,, unsigned int, nr, int, memory_order) +__RTE_BIT_OVERLOAD_3(atomic_clear,, unsigned int, nr, int, memory_order) +__RTE_BIT_OVERLOAD_4(atomic_assign,, unsigned int, nr, bool, value, + int, memory_order) +__RTE_BIT_OVERLOAD_3(atomic_flip,, unsigned int, nr, int, memory_order) +__RTE_BIT_OVERLOAD_3R(atomic_test_and_set,, bool, unsigned int, nr, + int, memory_order) +__RTE_BIT_OVERLOAD_3R(atomic_test_and_clear,, bool, unsigned int, nr, + int, memory_order) +__RTE_BIT_OVERLOAD_4R(atomic_test_and_assign,, bool, unsigned int, nr, + bool, value, int, memory_order) + #endif #endif /* _RTE_BITOPS_H_ */ -- 2.34.1