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([10.145.170.182]) by fmviesa010.fm.intel.com with ESMTP; 22 Aug 2024 03:50:55 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v1 06/12] net/ice: address compilation errors Date: Thu, 22 Aug 2024 09:56:06 +0000 Message-ID: <20240822095612.216214-7-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822095612.216214-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Visual Studio C++ compiler does not pass 32->16 or 16->8 bits conversions because of possible loss of data. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_ptp_hw.c | 31 ++++--------------------------- 1 file changed, 4 insertions(+), 27 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index e61810cbdc..2a112fea12 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1092,7 +1092,7 @@ ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u8 phy_index, u32 reg_addr, */ static int ice_phy_port_res_address_eth56g(u8 port, enum eth56g_res_type res_type, - u16 offset, u32 *address) + u32 offset, u32 *address) { u8 phy, lane; @@ -1615,7 +1615,7 @@ ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) */ static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) { - unsigned int port; + u8 port; for (port = 0; port < hw->max_phy_port; port++) { ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, @@ -2018,21 +2018,6 @@ int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port) return ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); } -/** - * ice_calc_fixed_rx_offset_eth56g - Calculated the fixed Rx offset for a port - * @hw: pointer to HW struct - * @link_spd: The Link speed to calculate for - * - * Determine the fixed Rx latency for a given link speed. - */ -static u64 -ice_calc_fixed_rx_offset_eth56g(struct ice_hw *hw, - enum ice_ptp_link_spd link_spd) -{ - u64 fixed_offset = 0; - return fixed_offset; -} - /** * ice_phy_cfg_rx_offset_eth56g - Configure total Rx timestamp offset * @hw: pointer to the HW struct @@ -2055,16 +2040,8 @@ ice_calc_fixed_rx_offset_eth56g(struct ice_hw *hw, int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port) { int err; - u64 total_offset; - - total_offset = ice_calc_fixed_rx_offset_eth56g(hw, 0); - /* Now that the total offset has been calculated, program it to the - * PHY and indicate that the Rx offset is ready. After this, - * timestamps will be enabled. - */ - err = ice_write_64b_phy_reg_eth56g(hw, port, PHY_REG_TOTAL_RX_OFFSET_L, - total_offset); + err = ice_write_64b_phy_reg_eth56g(hw, port, PHY_REG_TOTAL_RX_OFFSET_L, 0); if (err) return err; @@ -5672,7 +5649,7 @@ void ice_ptp_unlock(struct ice_hw *hw) */ void ice_ptp_init_phy_model(struct ice_hw *hw) { - unsigned int phy; + u8 phy; for (phy = 0; phy < MAX_PHYS_PER_ICE; phy++) hw->phy_addr[phy] = 0; -- 2.43.0