From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AD3154584B; Thu, 22 Aug 2024 21:49:21 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AC02942FC1; Thu, 22 Aug 2024 21:48:34 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by mails.dpdk.org (Postfix) with ESMTP id AA3A942FB9 for ; Thu, 22 Aug 2024 21:48:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724356113; x=1755892113; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=g7m4D9MpoZfTZ1C58rcKHWnj3SH6/vP32lFbobOB6cw=; b=EMztBuP+E2b14dTtO3g1cG3WUVO9x1i7gMEvz7MnT2tYqGC8pRdQ+Mkm PPRKjtY/jjtR7RNLzVUVlIWQBFW3AVs7hEyM8k7pHplt+5wRZ4907n2NZ lbpWKch2wff1r+3BOKQvQbBKUF2pAOCfkBaCz1OIRMiV/kOp3S3RsbF1D 321zfy9h4A5TIErDZWtALIhCz6mZiFRB2Kgimk8VzsEzsafKtLSuZiuyS UMQDT+P4nyAnGASnHxlnY2VlaFYZlIOSIeq7NyokEyMxxzFFH6fkXPoAW Tmo4UCjDmabsFzzR+d0Q3GzyOmzekR0rM7ki+qCviwfmVEsIzityk4TX2 w==; X-CSE-ConnectionGUID: EksSJpldQdydGyuhC8ggXQ== X-CSE-MsgGUID: j+PeffnOQEaHT0FuFOnKeg== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22979682" X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="22979682" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2024 12:48:32 -0700 X-CSE-ConnectionGUID: ZFPepIEnQoC7dBlcRrhTGA== X-CSE-MsgGUID: Dt+EprKiQ9yOamHRodsOKw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,168,1719903600"; d="scan'208";a="92301460" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa002.jf.intel.com with ESMTP; 22 Aug 2024 12:48:31 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com Subject: [PATCH v2 09/12] net/ice: correct Tx Scheduler AQ command RD bit for E825C Date: Thu, 22 Aug 2024 18:53:43 +0000 Message-ID: <20240822185346.221885-10-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240822185346.221885-1-soumyadeep.hore@intel.com> References: <20240822095612.216214-1-soumyadeep.hore@intel.com> <20240822185346.221885-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In E825C, regarding the Get Tx Topology AQ command, there is a change in the way that the RD bit must be set. For E825C, the RD bit must be cleared for the Get Tx Topology operation, whereas for E810 devices, the RD bit must be set. Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_ddp.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index 24506dfaea..d0c1cb9660 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -2270,6 +2270,22 @@ void ice_release_change_lock(struct ice_hw *hw) ice_release_res(hw, ICE_CHANGE_LOCK_RES_ID); } +/** + * ice_is_get_tx_sched_new_format + * @hw: pointer to the HW struct + * + * Determines if the new format for the Tx scheduler get api is supported + */ +static bool +ice_is_get_tx_sched_new_format(struct ice_hw *hw) +{ + if (ice_is_e830(hw)) + return true; + if (ice_is_e825c(hw)) + return true; + return false; +} + /** * ice_get_set_tx_topo - get or set tx topology * @hw: pointer to the HW struct @@ -2303,7 +2319,7 @@ ice_get_set_tx_topo(struct ice_hw *hw, u8 *buf, u16 buf_size, ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_tx_topo); cmd->get_flags = ICE_AQC_TX_TOPO_GET_RAM; - if (!ice_is_e830(hw)) + if (!ice_is_get_tx_sched_new_format(hw)) desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); } -- 2.43.0