From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7B8E45849; Fri, 23 Aug 2024 12:52:21 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 263DB43330; Fri, 23 Aug 2024 12:51:41 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by mails.dpdk.org (Postfix) with ESMTP id 9CBF44334D for ; Fri, 23 Aug 2024 12:51:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724410299; x=1755946299; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=400g34CA6vhE8vVu/cdu35n0qWu7YE4D350KXqlaEX4=; b=LCs12ZP/Wyx+Lb448wMWD5RmC8KCTfLA+KcUF5IW8iHGELvSlR2GeopI CgNlWvgek6hEoPM9W6Of3syxFcyrCCD6OjIlA7luPaUfvVn5/02wY8pbg g+tX+uxxIpSsSk3nx2qTf/jHodBoTXwEDOwo21Bf+xz8gCv7k7HrOJzjl HCU3DNQd+YDO8Y5QcoPN4+n7+pGgCZ9+zRIuEFT/6prMGX370lIMZGgJj ZDsWbjiNJXuQRgYs1EFIBjfhTmHLzQa1SFxSiRD5aoVjXohsLs1XQenUD oBtGatobc+OCXbQbuamCPZYzswtCioLh/0GGxYJPXWbkLXBEtrViva1mq A==; X-CSE-ConnectionGUID: YjtS/VLjQlKeaTQ7Kb+9Nw== X-CSE-MsgGUID: qad/PZ1KRR6BK+xSdTiJPw== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="33535658" X-IronPort-AV: E=Sophos;i="6.10,170,1719903600"; d="scan'208";a="33535658" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2024 03:51:39 -0700 X-CSE-ConnectionGUID: SFBU4Re8RQutfQas6lz5hQ== X-CSE-MsgGUID: 7XKn1IAATw+jEcAp8fTUFg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,170,1719903600"; d="scan'208";a="61617748" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa010.jf.intel.com with ESMTP; 23 Aug 2024 03:51:37 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com, Dan Nowlin Subject: [PATCH v3 09/12] net/ice: correct Tx Scheduler AQ command RD bit for E825C Date: Fri, 23 Aug 2024 09:56:47 +0000 Message-ID: <20240823095650.349785-10-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823095650.349785-1-soumyadeep.hore@intel.com> References: <20240822185346.221885-13-soumyadeep.hore@intel.com> <20240823095650.349785-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Dan Nowlin In E825C, regarding the Get Tx Topology AQ command, there is a change in the way that the RD bit must be set. For E825C, the RD bit must be cleared for the Get Tx Topology operation, whereas for E810 devices, the RD bit must be set. Signed-off-by: Dan Nowlin Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_ddp.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index 24506dfaea..d0c1cb9660 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -2270,6 +2270,22 @@ void ice_release_change_lock(struct ice_hw *hw) ice_release_res(hw, ICE_CHANGE_LOCK_RES_ID); } +/** + * ice_is_get_tx_sched_new_format + * @hw: pointer to the HW struct + * + * Determines if the new format for the Tx scheduler get api is supported + */ +static bool +ice_is_get_tx_sched_new_format(struct ice_hw *hw) +{ + if (ice_is_e830(hw)) + return true; + if (ice_is_e825c(hw)) + return true; + return false; +} + /** * ice_get_set_tx_topo - get or set tx topology * @hw: pointer to the HW struct @@ -2303,7 +2319,7 @@ ice_get_set_tx_topo(struct ice_hw *hw, u8 *buf, u16 buf_size, ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_tx_topo); cmd->get_flags = ICE_AQC_TX_TOPO_GET_RAM; - if (!ice_is_e830(hw)) + if (!ice_is_get_tx_sched_new_format(hw)) desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); } -- 2.43.0