From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E350245849; Fri, 23 Aug 2024 12:51:41 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7AA1E43320; Fri, 23 Aug 2024 12:51:27 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by mails.dpdk.org (Postfix) with ESMTP id 2A4A443326 for ; Fri, 23 Aug 2024 12:51:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724410285; x=1755946285; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eQbDnhaeqajYtaWM2XirI08NmP56d/680Bv/G6BDwBE=; b=OzBsvjxzQEIjAm4LLwYI3LeFDxXfLtgWR9xAxh1OXzC8jYTy2o7r+5Y4 pYYNJLU+dWYQvnBIArkI9UkXUYXZIhJ4N2V+zSAbCzpt6cC6sA+Onw+hf JZGi8yVlkZ1WSSDEJbe6Kinu5Cb8rY6o/iF6meAGqJUVFXzSYzpNJICUd 8KgBZOVqUx3UID+E3j6oP6sT7TVvRfVKD7hn9nBRukJ3J0r/5X248k5zq PasIzMurbjAEcocgGL39FRU2E5yqGAaGzKOrkjE6etRw8hi3BN8SLhgUa AFe5dEENEhNrfD4Gw4OX0zGMap7t939pclhrvBfy4TLJNEk1cDvt3K/PB w==; X-CSE-ConnectionGUID: JVdWzzLcRjW7r0KuzJTObw== X-CSE-MsgGUID: kexwalQLQi6grmEWthifHQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="33535630" X-IronPort-AV: E=Sophos;i="6.10,170,1719903600"; d="scan'208";a="33535630" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2024 03:51:24 -0700 X-CSE-ConnectionGUID: JyEfBNSwQXm4BLT+ZTlYhA== X-CSE-MsgGUID: Y9stzd28S/yUt5blaRnPrg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,170,1719903600"; d="scan'208";a="61617663" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa010.jf.intel.com with ESMTP; 23 Aug 2024 03:51:23 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com, Paul Greenwalt Subject: [PATCH v3 03/12] net/ice: add new tag definitions Date: Fri, 23 Aug 2024 09:56:41 +0000 Message-ID: <20240823095650.349785-4-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823095650.349785-1-soumyadeep.hore@intel.com> References: <20240822185346.221885-13-soumyadeep.hore@intel.com> <20240823095650.349785-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Paul Greenwalt Add E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE* defines to unified_manual.inc to make them available externally. Signed-off-by: Paul Greenwalt Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_hw_autogen.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h index 3753cc77c2..5877ddb5e8 100644 --- a/drivers/net/ice/base/ice_hw_autogen.h +++ b/drivers/net/ice/base/ice_hw_autogen.h @@ -13,6 +13,20 @@ #define PRTMAC_CTL_RX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE) #define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S) #define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE(_i) (0x000FD000 + ((_i) * 64)) /*_i=0-7 Rst Src:CORER*/ +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_MAX_INDEX 7 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_START_S 0 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_START_M MAKEMASK(0x3F, 0) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_END_S 6 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_END_M MAKEMASK(0x3F, 6) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_TYPE_S 12 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_TYPE_M MAKEMASK(0x3, 12) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_NUM_S 14 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_VM_VF_NUM_M MAKEMASK(0x3FF, 14) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_PF_NUM_S 24 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_PF_NUM_M MAKEMASK(0x7, 24) +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_ENABLE_S 31 +#define E830_GLTCLAN_TSYN_REG_RANGE_ENFORCE_ENABLE_M BIT(31) #define GL_HIDA(_i) (0x00082000 + ((_i) * 4)) #define GL_HIBA(_i) (0x00081000 + ((_i) * 4)) #define GL_HICR 0x00082040 -- 2.43.0