From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 91DDA45849; Fri, 23 Aug 2024 12:51:54 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E0FAF4333C; Fri, 23 Aug 2024 12:51:30 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by mails.dpdk.org (Postfix) with ESMTP id CAF614333C for ; Fri, 23 Aug 2024 12:51:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724410290; x=1755946290; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fpQllOhjPrA4NN8Q8A7WBbdox1PdmiYyP+NTKlkq1eg=; b=eys6ca/WYpbUNQ7bji2CPLQ9eshZMpbU3mFmNvG77quzDYyi+wsSu8Co Oc/WdXQIWhKypDIfae94iYzbUY5k8mP8Ge60bgxQIfmPVPnQw/75+rnYz Ay4fbWvAXGW53s2N6pl36jIam4PtanDzt9MGlf9SW82HaoHoZTyCJG5vk LJePwuPWG8TyXyxuBFiBGRt7zLzDVyABRE0V5n2u5lZg2xWe0fDorxsSK EHVi1fEymm4/dwosFm+aIDwyzsca9GSHJRP1Gl9dptiqFp4B60xe+zyK1 ynY2HzIKbwpHUQfX95blu5VYwRGmTCWdsvJNi9N5iV4Q9mZJRcuplTGEp w==; X-CSE-ConnectionGUID: SAV38d1JThaoOK6oGJZxdA== X-CSE-MsgGUID: r4hRFwoQTPmpKyWk5t28PQ== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="33535637" X-IronPort-AV: E=Sophos;i="6.10,170,1719903600"; d="scan'208";a="33535637" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2024 03:51:29 -0700 X-CSE-ConnectionGUID: 2IMKvxmdTXGrFPSKN7ZWTA== X-CSE-MsgGUID: jolUnh9MT7CZ9cOMqnpglg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,170,1719903600"; d="scan'208";a="61617693" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa010.jf.intel.com with ESMTP; 23 Aug 2024 03:51:27 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, ian.stokes@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com, Norbert Zulinski Subject: [PATCH v3 05/12] net/ice: update PTP init Date: Fri, 23 Aug 2024 09:56:43 +0000 Message-ID: <20240823095650.349785-6-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240823095650.349785-1-soumyadeep.hore@intel.com> References: <20240822185346.221885-13-soumyadeep.hore@intel.com> <20240823095650.349785-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Norbert Zulinski Add Bit macro to init PHY 1 for E825C devices. Signed-off-by: Norbert Zulinski Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_ptp_hw.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index e574ae6d4f..e61810cbdc 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2365,9 +2365,10 @@ static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) u32 regval = rd32(hw, PF_SB_REM_DEV_CTL); if (enable) - regval |= (cgu | eth56g_dev_0 | eth56g_dev_1); + regval |= (BIT(eth56g_dev_1)); else - regval &= ~(cgu | eth56g_dev_0 | eth56g_dev_1); + regval &= ~(BIT(eth56g_dev_1)); + wr32(hw, PF_SB_REM_DEV_CTL, regval); } @@ -5691,6 +5692,7 @@ void ice_ptp_init_phy_model(struct ice_hw *hw) } ice_sb_access_ena_eth56g(hw, true); + for (phy = 0; phy < hw->num_phys; phy++) if (hw->phy_addr[phy]) { int err; -- 2.43.0