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From: Daniel Gregory <daniel.gregory@bytedance.com>
To: Stanislaw Kardach <stanislaw.kardach@gmail.com>,
Bruce Richardson <bruce.richardson@intel.com>
Cc: dev@dpdk.org, Punit Agrawal <punit.agrawal@bytedance.com>,
Liang Ma <liangma@liangbit.com>,
Pengcheng Wang <wangpengcheng.pp@bytedance.com>,
Chunsong Feng <fengchunsong@bytedance.com>,
Daniel Gregory <daniel.gregory@bytedance.com>
Subject: [PATCH v3 4/9] config/riscv: add qemu crossbuild target
Date: Tue, 27 Aug 2024 16:32:24 +0100
Message-Id: <20240827153230.52880-5-daniel.gregory@bytedance.com>
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A new cross-compilation target that has extensions that DPDK uses and
QEMU supports. Initially, this is just the Zbc extension for hardware
CRC support.
Signed-off-by: Daniel Gregory <daniel.gregory@bytedance.com>
---
config/riscv/meson.build | 3 ++-
config/riscv/riscv64_qemu_linux_gcc | 17 +++++++++++++++++
.../linux_gsg/cross_build_dpdk_for_riscv.rst | 5 +++++
3 files changed, 24 insertions(+), 1 deletion(-)
create mode 100644 config/riscv/riscv64_qemu_linux_gcc
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index 5d8411b254..337b26bbac 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -43,7 +43,8 @@ vendor_generic = {
['RTE_MAX_NUMA_NODES', 2]
],
'arch_config': {
- 'generic': {'machine_args': ['-march=rv64gc']}
+ 'generic': {'machine_args': ['-march=rv64gc']},
+ 'qemu': {'machine_args': ['-march=rv64gc_zbc']},
}
}
diff --git a/config/riscv/riscv64_qemu_linux_gcc b/config/riscv/riscv64_qemu_linux_gcc
new file mode 100644
index 0000000000..007cc98885
--- /dev/null
+++ b/config/riscv/riscv64_qemu_linux_gcc
@@ -0,0 +1,17 @@
+[binaries]
+c = ['ccache', 'riscv64-linux-gnu-gcc']
+cpp = ['ccache', 'riscv64-linux-gnu-g++']
+ar = 'riscv64-linux-gnu-ar'
+strip = 'riscv64-linux-gnu-strip'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'riscv64'
+cpu = 'rv64gc_zbc'
+endian = 'little'
+
+[properties]
+vendor_id = 'generic'
+arch_id = 'qemu'
+pkg_config_libdir = '/usr/lib/riscv64-linux-gnu/pkgconfig'
diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
index 7d7f7ac72b..c3b67671a0 100644
--- a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
+++ b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
@@ -110,6 +110,11 @@ Currently the following targets are supported:
* SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc``
+* QEMU: ``config/riscv/riscv64_qemu_linux_gcc``
+
+ * A target with all the extensions that QEMU supports that DPDK has a use for
+ (currently ``rv64gc_zbc``). Requires QEMU version 7.0.0 or newer.
+
To add a new target support, ``config/riscv/meson.build`` has to be modified by
adding a new vendor/architecture id and a corresponding cross-file has to be
added to ``config/riscv`` directory.
--
2.39.2