From: Harman Kalra <hkalra@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>,
Harman Kalra <hkalra@marvell.com>
Cc: <dev@dpdk.org>
Subject: [PATCH 4/5] common/cnxk: define PF VF bit encoding in pcifunc
Date: Mon, 2 Sep 2024 11:59:39 +0530 [thread overview]
Message-ID: <20240902062940.182273-5-hkalra@marvell.com> (raw)
In-Reply-To: <20240902062940.182273-1-hkalra@marvell.com>
In cn20k, PF and VF bit encoding format in a pcifunc has changed to
accommodate more no of PFs. Hence defining the pf/vf encoding
parameters for cn20k and cn9k/10k platforms.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
---
drivers/common/cnxk/roc_dev.c | 1 +
drivers/common/cnxk/roc_dev_priv.h | 31 ++++++++++++++++++++++++------
drivers/common/cnxk/roc_npc.c | 5 ++++-
3 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c
index b9bbcac3d8..0b434e4a8a 100644
--- a/drivers/common/cnxk/roc_dev.c
+++ b/drivers/common/cnxk/roc_dev.c
@@ -23,6 +23,7 @@
/* VF interrupt message pending bits - mbox or flr */
#define ROC_DEV_MBOX_PEND BIT_ULL(0)
#define ROC_DEV_FLR_PEND BIT_ULL(1)
+
static void *
mbox_mem_map(off_t off, size_t size)
{
diff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h
index 976eb48346..75395e5fd5 100644
--- a/drivers/common/cnxk/roc_dev_priv.h
+++ b/drivers/common/cnxk/roc_dev_priv.h
@@ -7,12 +7,19 @@
#define DEV_HWCAP_F_VF BIT_ULL(0) /* VF device */
+/* PF and VF bit encoding parameters in pcifunc */
+#define RVU_PFVF_PF_SHIFT_CN20K 9
+#define RVU_PFVF_PF_MASK_CN20K 0x7F
+#define RVU_PFVF_FUNC_SHIFT_CN20K 0
+#define RVU_PFVF_FUNC_MASK_CN20K 0x1FF
+
#define RVU_PFVF_PF_SHIFT 10
#define RVU_PFVF_PF_MASK 0x3F
#define RVU_PFVF_FUNC_SHIFT 0
#define RVU_PFVF_FUNC_MASK 0x3FF
-#define RVU_MAX_VF 64 /* RVU_PF_VFPF_MBOX_INT(0..1) */
-#define RVU_MAX_INT_RETRY 3
+
+#define RVU_MAX_VF 64 /* RVU_PF_VFPF_MBOX_INT(0..1) */
+#define RVU_MAX_INT_RETRY 3
/* PF/VF message handling timer */
#define VF_PF_MBOX_TIMER_MS (20 * 1000)
@@ -52,25 +59,37 @@ struct dev_ops {
static inline int
dev_get_vf(uint16_t pf_func)
{
- return (((pf_func >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK) - 1);
+ if (roc_model_is_cn20k())
+ return (((pf_func >> RVU_PFVF_FUNC_SHIFT_CN20K) & RVU_PFVF_FUNC_MASK_CN20K) - 1);
+ else
+ return (((pf_func >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK) - 1);
}
static inline int
dev_get_pf(uint16_t pf_func)
{
- return (pf_func >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
+ if (roc_model_is_cn20k())
+ return (pf_func >> RVU_PFVF_PF_SHIFT_CN20K) & RVU_PFVF_PF_MASK_CN20K;
+ else
+ return (pf_func >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
}
static inline int
dev_pf_func(int pf, int vf)
{
- return (pf << RVU_PFVF_PF_SHIFT) | ((vf << RVU_PFVF_FUNC_SHIFT) + 1);
+ if (roc_model_is_cn20k())
+ return (pf << RVU_PFVF_PF_SHIFT_CN20K) | ((vf << RVU_PFVF_FUNC_SHIFT_CN20K) + 1);
+ else
+ return (pf << RVU_PFVF_PF_SHIFT) | ((vf << RVU_PFVF_FUNC_SHIFT) + 1);
}
static inline int
dev_is_afvf(uint16_t pf_func)
{
- return !(pf_func & ~RVU_PFVF_FUNC_MASK);
+ if (roc_model_is_cn20k())
+ return !(pf_func & ~RVU_PFVF_FUNC_MASK_CN20K);
+ else
+ return !(pf_func & ~RVU_PFVF_FUNC_MASK);
}
struct mbox_sync {
diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index 37e1a6a7ef..8a951b6360 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -616,7 +616,10 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,
case ROC_NPC_ACTION_TYPE_VF:
vf_act = (const struct roc_npc_action_vf *)actions->conf;
req_act |= ROC_NPC_ACTION_TYPE_VF;
- vf_id = vf_act->id & RVU_PFVF_FUNC_MASK;
+ if (roc_model_is_cn20k())
+ vf_id = vf_act->id & RVU_PFVF_FUNC_MASK_CN20K;
+ else
+ vf_id = vf_act->id & RVU_PFVF_FUNC_MASK;
pf_func &= (0xfc00);
pf_func = (pf_func | (vf_id + 1));
break;
--
2.25.1
next prev parent reply other threads:[~2024-09-02 6:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-02 6:29 [PATCH 0/5] Marvell cn20K SOC base code Harman Kalra
2024-09-02 6:29 ` [PATCH 1/5] common/cnxk: define platform configuration Harman Kalra
2024-09-02 6:29 ` [PATCH 2/5] common/cnxk: add CN20ka A0 model Harman Kalra
2024-09-02 6:29 ` [PATCH 3/5] common/cnxk: add cn20ka mbox support Harman Kalra
2024-09-02 6:29 ` Harman Kalra [this message]
2024-09-02 6:29 ` [PATCH 5/5] common/cnxk: enable PF VF mbox Harman Kalra
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