From: Stephen Hemminger <stephen@networkplumber.org>
To: "Mattias Rönnblom" <hofors@lysator.liu.se>
Cc: "Varghese, Vipin" <vipin.varghese@amd.com>,
ferruh.yigit@amd.com, dev@dpdk.org
Subject: Re: [RFC 0/2] introduce LLC aware functions
Date: Wed, 4 Sep 2024 07:37:19 -0700 [thread overview]
Message-ID: <20240904073719.0603b2a5@hermes.local> (raw)
In-Reply-To: <db151bdb-7683-49e3-b759-d729f53a556c@lysator.liu.se>
On Wed, 4 Sep 2024 11:30:59 +0200
Mattias Rönnblom <hofors@lysator.liu.se> wrote:
> On 2024-09-02 02:39, Varghese, Vipin wrote:
> > <snipped>
> >
> > Thank you Mattias for the comments and question, please let me try to
> > explain the same below
> >
> >> We shouldn't have a separate CPU/cache hierarchy API instead?
> >
> > Based on the intention to bring in CPU lcores which share same L3 (for
> > better cache hits and less noisy neighbor) current API focuses on using
> >
> > Last Level Cache. But if the suggestion is `there are SoC where L2 cache
> > are also shared, and the new API should be provisioned`, I am also
> >
> > comfortable with the thought.
> >
>
> Rather than some AMD special case API hacked into <rte_lcore.h>, I think
> we are better off with no DPDK API at all for this kind of functionality.
>
> A DPDK CPU/memory hierarchy topology API very much makes sense, but it
> should be reasonably generic and complete from the start.
Agreed. This one of those cases where the existing project hwloc which
is part of open-mpi is more complete and well supported. It supports
multiple OS's and can deal with more quirks.
https://github.com/open-mpi/hwloc
next prev parent reply other threads:[~2024-09-04 14:37 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-27 15:10 Vipin Varghese
2024-08-27 15:10 ` [RFC 1/2] eal: add llc " Vipin Varghese
2024-08-27 17:36 ` Stephen Hemminger
2024-09-02 0:27 ` Varghese, Vipin
2024-08-27 20:56 ` Wathsala Wathawana Vithanage
2024-08-29 3:21 ` 答复: " Feifei Wang
2024-09-02 1:20 ` Varghese, Vipin
2024-09-03 17:54 ` Wathsala Wathawana Vithanage
2024-09-04 8:18 ` Bruce Richardson
2024-09-06 11:59 ` Varghese, Vipin
2024-09-12 16:58 ` Wathsala Wathawana Vithanage
2024-08-27 15:10 ` [RFC 2/2] eal/lcore: add llc aware for each macro Vipin Varghese
2024-08-27 21:23 ` [RFC 0/2] introduce LLC aware functions Mattias Rönnblom
2024-09-02 0:39 ` Varghese, Vipin
2024-09-04 9:30 ` Mattias Rönnblom
2024-09-04 14:37 ` Stephen Hemminger [this message]
2024-09-11 3:13 ` Varghese, Vipin
2024-09-11 3:53 ` Stephen Hemminger
2024-09-12 1:11 ` Varghese, Vipin
2024-09-09 14:22 ` Varghese, Vipin
2024-09-09 14:52 ` Mattias Rönnblom
2024-09-11 3:26 ` Varghese, Vipin
2024-09-11 15:55 ` Mattias Rönnblom
2024-09-11 17:04 ` Honnappa Nagarahalli
2024-09-12 1:33 ` Varghese, Vipin
2024-09-12 6:38 ` Mattias Rönnblom
2024-09-12 7:02 ` Mattias Rönnblom
2024-09-12 11:23 ` Varghese, Vipin
2024-09-12 12:12 ` Mattias Rönnblom
2024-09-12 15:50 ` Stephen Hemminger
2024-09-12 11:17 ` Varghese, Vipin
2024-09-12 11:59 ` Mattias Rönnblom
2024-09-12 13:30 ` Bruce Richardson
2024-09-12 16:32 ` Mattias Rönnblom
2024-09-12 2:28 ` Varghese, Vipin
2024-09-11 16:01 ` Bruce Richardson
2024-09-11 22:25 ` Konstantin Ananyev
2024-09-12 2:38 ` Varghese, Vipin
2024-09-12 2:19 ` Varghese, Vipin
2024-09-12 9:17 ` Bruce Richardson
2024-09-12 11:50 ` Varghese, Vipin
2024-09-13 14:15 ` Burakov, Anatoly
2024-09-12 13:18 ` Mattias Rönnblom
2024-08-28 8:38 ` Burakov, Anatoly
2024-09-02 1:08 ` Varghese, Vipin
2024-09-02 14:17 ` Burakov, Anatoly
2024-09-02 15:33 ` Varghese, Vipin
2024-09-03 8:50 ` Burakov, Anatoly
2024-09-05 13:05 ` Ferruh Yigit
2024-09-05 14:45 ` Burakov, Anatoly
2024-09-05 15:34 ` Ferruh Yigit
2024-09-06 8:44 ` Burakov, Anatoly
2024-09-09 14:14 ` Varghese, Vipin
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