From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2BD8A45909; Thu, 5 Sep 2024 09:47:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 21DEA42E56; Thu, 5 Sep 2024 09:46:59 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3F86242E3A for ; Thu, 5 Sep 2024 09:46:58 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48547eW1013745 for ; Thu, 5 Sep 2024 00:46:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=d HXJMotzQRVDEmi6SSSXjY8fxcY8LbL2IPVw3nZlppk=; b=f5FgEfcB9MxoqEQow n3HGp6FPS92zdNfJrSo+X4GXeFmKHBIE4uQZe+RhC9e/CteVhAwRYO6Xz3X8QSSw pu5T3s9CwNTVBbTQkco36a/E80GalBiJ0K4pYFuiIW3RSvNNfNYL95u2XsLPXJTo 4wNAPTCtJPfgIIR1kuGY6/obNln4Ofqwy9S3x+s7eaKL3IHAQEo2pBAO399he2aN 5OJEO7dIl36VK/D2xStA67b4paV+CjPBvJ8TNr/SHV3CoJ7IX8WZY2BYc+8O+x7O gmmV8EMaQ3NVsQmYoZ3vndft2qNZYbIIMzjYIp50bYilN/Z0wIRmQZ9sM3aT/DIq EQFKg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 41ev31tfqk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 05 Sep 2024 00:46:57 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 5 Sep 2024 00:46:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 5 Sep 2024 00:46:56 -0700 Received: from hyd1554.caveonetworks.com (unknown [10.29.56.32]) by maili.marvell.com (Postfix) with ESMTP id C8D5D5B6928; Thu, 5 Sep 2024 00:46:54 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Vidya Sagar Velumuri , Subject: [PATCH 10/11] crypto/cnxk: add CPTR read and write Date: Thu, 5 Sep 2024 13:16:30 +0530 Message-ID: <20240905074631.1462357-11-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240905074631.1462357-1-ktejasree@marvell.com> References: <20240905074631.1462357-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: U0VDfefwcxYNsr8ba8T02-of4S7mTnut X-Proofpoint-GUID: U0VDfefwcxYNsr8ba8T02-of4S7mTnut X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-05_04,2024-09-04_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph Add PMD API for CPTR read and write. Signed-off-by: Anoob Joseph --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 71 +++++++++++++++++++++++ drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h | 52 +++++++++++++++++ drivers/crypto/cnxk/version.map | 2 + 3 files changed, 125 insertions(+) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index ccb800730c..a7d58a5445 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -2,6 +2,7 @@ * Copyright(C) 2021 Marvell. */ +#include #include #include #include @@ -1090,3 +1091,73 @@ rte_pmd_cnxk_crypto_cptr_get(struct rte_pmd_cnxk_crypto_sess *rte_sess) plt_err("Invalid session type"); return NULL; } + +int +rte_pmd_cnxk_crypto_cptr_read(struct rte_pmd_cnxk_crypto_qptr *qptr, + struct rte_pmd_cnxk_crypto_cptr *cptr, void *data, uint32_t len) +{ + struct cnxk_cpt_qp *qp = PLT_PTR_CAST(qptr); + int ret; + + if (unlikely(qptr == NULL)) { + plt_err("Invalid queue pair pointer"); + return -EINVAL; + } + + if (unlikely(cptr == NULL)) { + plt_err("Invalid CPTR pointer"); + return -EINVAL; + } + + if (unlikely(data == NULL)) { + plt_err("Invalid data pointer"); + return -EINVAL; + } + + ret = roc_cpt_lf_ctx_flush(&qp->lf, cptr, false); + if (ret) + return ret; + + /* Wait for the flush to complete. */ + rte_delay_ms(1); + + memcpy(data, cptr, len); + return 0; +} + +int +rte_pmd_cnxk_crypto_cptr_write(struct rte_pmd_cnxk_crypto_qptr *qptr, + struct rte_pmd_cnxk_crypto_cptr *cptr, void *data, uint32_t len) +{ + struct cnxk_cpt_qp *qp = PLT_PTR_CAST(qptr); + int ret; + + if (unlikely(qptr == NULL)) { + plt_err("Invalid queue pair pointer"); + return -EINVAL; + } + + if (unlikely(cptr == NULL)) { + plt_err("Invalid CPTR pointer"); + return -EINVAL; + } + + if (unlikely(data == NULL)) { + plt_err("Invalid data pointer"); + return -EINVAL; + } + + ret = roc_cpt_ctx_write(&qp->lf, data, cptr, len); + if (ret) { + plt_err("Could not write to CPTR"); + return ret; + } + + ret = roc_cpt_lf_ctx_flush(&qp->lf, cptr, false); + if (ret) + return ret; + + rte_atomic_thread_fence(rte_memory_order_seq_cst); + + return 0; +} diff --git a/drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h b/drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h index 7a7d20c290..454261022b 100644 --- a/drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h +++ b/drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h @@ -124,4 +124,56 @@ __rte_experimental struct rte_pmd_cnxk_crypto_cptr *rte_pmd_cnxk_crypto_cptr_get( struct rte_pmd_cnxk_crypto_sess *rte_sess); +/** + * Read HW context (CPTR). + * + * @param qptr + * Pointer obtained with ``rte_pmd_cnxk_crypto_qptr_get``. + * @param cptr + * Pointer obtained with ``rte_pmd_cnxk_crypto_cptr_get`` or any valid CPTR address that can be + * used with CPT CTX cache. + * @param[out] data + * Destination pointer to copy CPTR context for application. + * @param len + * Length of CPTR context to copy into data parameter. + * + * @return + * - 0 On success. + * - Negative value on error. + * - -EINVAL if the input parameters are invalid. + * - -ENOTSUP if the operation is not supported. + * - -EAGAIN if the operation is not successful. + * - -EFAULT if the operation failed. + */ +__rte_experimental +int rte_pmd_cnxk_crypto_cptr_read(struct rte_pmd_cnxk_crypto_qptr *qptr, + struct rte_pmd_cnxk_crypto_cptr *cptr, void *data, + uint32_t len); + +/** + * Write HW context (CPTR). + * + * @param qptr + * Pointer obtained with ``rte_pmd_cnxk_crypto_qptr_get``. + * @param cptr + * Pointer obtained with ``rte_pmd_cnxk_crypto_cptr_get`` or any valid CPTR address that can be + * used with CPT CTX cache. + * @param data + * Source pointer to copy CPTR context from application. + * @param len + * Length of CPTR context to copy from data parameter. + * + * @return + * - 0 On success. + * - Negative value on error. + * - -EINVAL if the input parameters are invalid. + * - -ENOTSUP if the operation is not supported. + * - -EAGAIN if the operation is not successful. + * - -EFAULT if the operation failed. + */ +__rte_experimental +int rte_pmd_cnxk_crypto_cptr_write(struct rte_pmd_cnxk_crypto_qptr *qptr, + struct rte_pmd_cnxk_crypto_cptr *cptr, void *data, + uint32_t len); + #endif /* _PMD_CNXK_CRYPTO_H_ */ diff --git a/drivers/crypto/cnxk/version.map b/drivers/crypto/cnxk/version.map index 7a8122dc1d..6e51f7be1a 100644 --- a/drivers/crypto/cnxk/version.map +++ b/drivers/crypto/cnxk/version.map @@ -8,6 +8,8 @@ EXPERIMENTAL { # added in 24.07 rte_pmd_cnxk_crypto_cptr_flush; rte_pmd_cnxk_crypto_cptr_get; + rte_pmd_cnxk_crypto_cptr_read; + rte_pmd_cnxk_crypto_cptr_write; }; INTERNAL { -- 2.25.1