From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E531945909; Thu, 5 Sep 2024 09:47:07 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E2B7542E24; Thu, 5 Sep 2024 09:46:47 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4E7F842DD0 for ; Thu, 5 Sep 2024 09:46:43 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4856JiLU009239 for ; Thu, 5 Sep 2024 00:46:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=r M0evnN712mzzTkMS+rD/B9tcEGIs4LbYvSJ6RQRsSo=; b=QstLnBe1yqlw5ac16 33VroCyXafyVs7G+7Mo+2ZA0rGVvsRA3Nr/szyN/feZXeH6MvYiaZeJWHpY8SgdZ jjNvaJTiAhIlXX+vPTMffPtySDF394O74J7LnzIoc5uR+5ZBFqnuYRmjC9IANL2W 7gwe4S7oC0suBj6wE+NJFoE3wo3MMj7uZJOBs9Iu2fuflQx6KLURM4m37vgKoiNu FLLFr4OytGQJnUVRfGJyVjZ6TdQfxr5I56NXkpDhWLBl7ii8W8Rg+GZGLcOBa2vw wsFBq2gkwkoBD/IAOTLmbRtyyE54fvULIz6bklKb+YL+pEp0hBRGy6H5/D5GZZjo vtl9w== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 41f79dr95d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 05 Sep 2024 00:46:37 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 5 Sep 2024 00:46:36 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 5 Sep 2024 00:46:36 -0700 Received: from hyd1554.caveonetworks.com (unknown [10.29.56.32]) by maili.marvell.com (Postfix) with ESMTP id 25C7A3F70AD; Thu, 5 Sep 2024 00:46:34 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Vidya Sagar Velumuri , Anoob Joseph , Subject: [PATCH 01/11] crypto/cnxk: align passthrough data for SM ciphers Date: Thu, 5 Sep 2024 13:16:21 +0530 Message-ID: <20240905074631.1462357-2-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240905074631.1462357-1-ktejasree@marvell.com> References: <20240905074631.1462357-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 5ajpUhXQIAHp0SKnfEbf9RaeiRm-jwbw X-Proofpoint-GUID: 5ajpUhXQIAHp0SKnfEbf9RaeiRm-jwbw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-05_04,2024-09-04_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Add required padding to make passthrough data length multiple of 16 bytes for SM ciphers Signed-off-by: Vidya Sagar Velumuri --- drivers/crypto/cnxk/cnxk_se.h | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index dbd36a8a54..426147a9d4 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -1100,6 +1100,7 @@ cpt_sm_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, struct roc_se_fc_p { int32_t inputlen, outputlen, enc_dlen; union cpt_inst_w4 cpt_inst_w4; + uint32_t passthr_len, pad_len; uint32_t passthrough_len = 0; const uint8_t *src = NULL; struct roc_se_ctx *se_ctx; @@ -1119,21 +1120,18 @@ cpt_sm_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, struct roc_se_fc_p if (unlikely(!(flags & ROC_SE_VALID_IV_BUF))) iv_len = 0; - encr_offset += iv_len; - enc_dlen = RTE_ALIGN_CEIL(encr_data_len, 8) + encr_offset; + passthr_len = encr_offset + iv_len; + passthr_len = RTE_ALIGN_CEIL(passthr_len, 8); + pad_len = passthr_len - encr_offset - iv_len; + enc_dlen = RTE_ALIGN_CEIL(encr_data_len, 8) + passthr_len; inputlen = enc_dlen; outputlen = enc_dlen; cpt_inst_w4.s.param1 = encr_data_len; - if (unlikely(encr_offset >> 8)) { - plt_dp_err("Offset not supported"); - plt_dp_err("enc_offset: %d", encr_offset); - return -1; - } - - offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset); + offset_ctrl = passthr_len & 0xff; + offset_ctrl = rte_cpu_to_be_64(offset_ctrl); /* * In cn9k, cn10k since we have a limitation of @@ -1146,14 +1144,14 @@ cpt_sm_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, struct roc_se_fc_p /* Use Direct mode */ - offset_vaddr = PLT_PTR_SUB(dm_vaddr, ROC_SE_OFF_CTRL_LEN + iv_len); + offset_vaddr = PLT_PTR_SUB(dm_vaddr, ROC_SE_OFF_CTRL_LEN + pad_len + iv_len); *(uint64_t *)offset_vaddr = offset_ctrl; /* DPTR */ inst->dptr = (uint64_t)offset_vaddr; /* RPTR should just exclude offset control word */ - inst->rptr = (uint64_t)dm_vaddr - iv_len; + inst->rptr = (uint64_t)dm_vaddr - iv_len - pad_len; cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN; @@ -1171,12 +1169,13 @@ cpt_sm_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, struct roc_se_fc_p inst->w4.u64 = cpt_inst_w4.u64; if (is_sg_ver2) - ret = sg2_inst_prep(fc_params, inst, offset_ctrl, src, iv_len, 0, 0, - inputlen, outputlen, passthrough_len, flags, 0, + ret = sg2_inst_prep(fc_params, inst, offset_ctrl, src, iv_len + pad_len, 0, + 0, inputlen, outputlen, passthrough_len, flags, 0, decrypt); else - ret = sg_inst_prep(fc_params, inst, offset_ctrl, src, iv_len, 0, 0, - inputlen, outputlen, passthrough_len, flags, 0, decrypt); + ret = sg_inst_prep(fc_params, inst, offset_ctrl, src, iv_len + pad_len, 0, + 0, inputlen, outputlen, passthrough_len, flags, 0, + decrypt); if (unlikely(ret)) { plt_dp_err("sg prep failed"); -- 2.25.1