From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4881945909; Thu, 5 Sep 2024 09:46:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6D87742DD3; Thu, 5 Sep 2024 09:46:44 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 22C1F42DC3 for ; Thu, 5 Sep 2024 09:46:42 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4856Jd75009118 for ; Thu, 5 Sep 2024 00:46:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=J 5z1K6fjYb9bX1gGEWUvpxbYPCN8PQ2u0sj7KQGp93k=; b=IJvWb5fP7cFFJtChu PJDWF3VB5OMfrfrUAzAfDtkfIwPBroCVhus8JJK59/ve6U/hxtd9lijBqdAW0Byk FyKuwcGxgoDC8XviBDDXQ05bsJ7yOUVl66vXwPpPs4GCWZ+nDl/OpqL1I4JWwTlP XNWlR0iz/JlXnmX27Lma4sUrOLyXe3FFjR/p7mW2ft2k3idXRVznQ4m61hhwXfYt PsEVMWWyhkA5k3nTN5V8ZgpnEwwioU597eN+yijf/s7v5qkjGkKT+6xw5ja9XnrS MPG49mevJv3DAq1QvSlHdJTYFVJrQTnQIaS+Ay5ZkITMMPVTDZh5VSeor8xPHs+8 0N2ug== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 41f79dr95r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 05 Sep 2024 00:46:42 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 5 Sep 2024 00:46:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 5 Sep 2024 00:46:41 -0700 Received: from hyd1554.caveonetworks.com (unknown [10.29.56.32]) by maili.marvell.com (Postfix) with ESMTP id 7B0475B6927; Thu, 5 Sep 2024 00:46:39 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Vidya Sagar Velumuri , Subject: [PATCH 03/11] common/cnxk: ensure CPTR is 128B aligned Date: Thu, 5 Sep 2024 13:16:23 +0530 Message-ID: <20240905074631.1462357-4-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240905074631.1462357-1-ktejasree@marvell.com> References: <20240905074631.1462357-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: LEOLtYlmwmQtRO7xXiwg5oGyITCC1w0U X-Proofpoint-GUID: LEOLtYlmwmQtRO7xXiwg5oGyITCC1w0U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-05_04,2024-09-04_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph Make sure CPTR is 128B aligned. Signed-off-by: Anoob Joseph --- drivers/common/cnxk/roc_cpt.c | 5 +++++ drivers/common/cnxk/roc_platform.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index aba2a49d19..64fa284b9a 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -1174,6 +1174,11 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, uint64_t *dptr; int i; + if (!plt_is_aligned(sa_cptr, 128)) { + plt_err("Context pointer should be 128B aligned"); + return -EINVAL; + } + /* Use this lcore's LMT line as no one else is using it */ ROC_LMT_BASE_ID_GET(lmt_base, lmt_id); inst = (struct cpt_inst_s *)lmt_base; diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 658bafb935..2b45cc3721 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -185,6 +185,7 @@ plt_thread_is_valid(plt_thread_t thr) #define plt_intr_efds_index_set rte_intr_efds_index_set #define plt_intr_elist_index_get rte_intr_elist_index_get #define plt_intr_elist_index_set rte_intr_elist_index_set +#define plt_is_aligned rte_is_aligned #define plt_alarm_set rte_eal_alarm_set #define plt_alarm_cancel rte_eal_alarm_cancel -- 2.25.1