From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8F2F045909; Thu, 5 Sep 2024 09:47:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 78C9642E61; Thu, 5 Sep 2024 09:47:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7C1B84025C for ; Thu, 5 Sep 2024 09:47:02 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4856Jd7B009118 for ; Thu, 5 Sep 2024 00:46:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=l KFryAxku4fsGHDX0B70ZTazpY2YBApytCINmFGCd+U=; b=CxJtv6t4Z5+JNLEWP oxLloS24HhQ3Ij7HXPwalgmeG6sFYet0WD3CZyC7f3ZKhoZV7FbkFzAjHTxjptLZ qb49NugCYeNyoqQC6mEn92LfChI//6iaenNbN4e9sOB4lY2En9HhYUXIzkatWm4V sfx/FSx4GwIxcV+Z1T1nVmqvl7dpoJVw6Nn7fYv3qR0iVU7kMDSB0TM0CVL+SSZ2 N1zIrxIFLr9H0z8WYCpIEeU2gYY733WsLsbhmKyyfSwHjn3MwKOcAjCwc9/uBNwz TFsAoE/5u+XV19bF622c+2OcLR9tY1mI6ss/AcSDDBIOWxyg0X7xf07l4VoYijvQ iEhkg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 41f79dr975-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 05 Sep 2024 00:46:53 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 5 Sep 2024 00:46:52 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 5 Sep 2024 00:46:52 -0700 Received: from hyd1554.caveonetworks.com (unknown [10.29.56.32]) by maili.marvell.com (Postfix) with ESMTP id 765465B6928; Thu, 5 Sep 2024 00:46:50 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Vidya Sagar Velumuri , Subject: [PATCH 08/11] crypto/cnxk: add PMD API for getting CPTR Date: Thu, 5 Sep 2024 13:16:28 +0530 Message-ID: <20240905074631.1462357-9-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240905074631.1462357-1-ktejasree@marvell.com> References: <20240905074631.1462357-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: x-wPkkicQ4iA6pNdmWF03nQHDL29aKLr X-Proofpoint-GUID: x-wPkkicQ4iA6pNdmWF03nQHDL29aKLr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-05_04,2024-09-04_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph CPTR address is the context address used by hardware. Add PMD API to retrieve the hardware address from rte_cryptodev/rte_security session. Signed-off-by: Anoob Joseph --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 49 +++++++++++++++++++++++ drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h | 42 +++++++++++++++++++ drivers/crypto/cnxk/version.map | 3 ++ 3 files changed, 94 insertions(+) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index d0ad2d9a4b..128f1b1ddd 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -25,7 +25,9 @@ #include "cnxk_se.h" #include "cn10k_cryptodev_ops.h" +#include "cn10k_cryptodev_sec.h" #include "cn9k_cryptodev_ops.h" +#include "cn9k_ipsec.h" #include "rte_pmd_cnxk_crypto.h" @@ -1017,3 +1019,50 @@ rte_pmd_cnxk_crypto_submit(struct rte_pmd_cnxk_crypto_qptr *qptr, void *inst, ui plt_err("Invalid cnxk model"); } + +struct rte_pmd_cnxk_crypto_cptr * +rte_pmd_cnxk_crypto_cptr_get(struct rte_pmd_cnxk_crypto_sess *rte_sess) +{ + if (rte_sess == NULL) { + plt_err("Invalid session pointer"); + return NULL; + } + + if (rte_sess->sec_sess == NULL) { + plt_err("Invalid RTE session pointer"); + return NULL; + } + + if (rte_sess->op_type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { + struct cnxk_ae_sess *ae_sess = PLT_PTR_CAST(rte_sess->crypto_asym_sess); + return PLT_PTR_CAST(&ae_sess->hw_ctx); + } + + if (rte_sess->op_type != RTE_CRYPTO_OP_TYPE_SYMMETRIC) { + plt_err("Invalid crypto operation type"); + return NULL; + } + + if (rte_sess->sess_type == RTE_CRYPTO_OP_WITH_SESSION) { + struct cnxk_se_sess *se_sess = PLT_PTR_CAST(rte_sess->crypto_sym_sess); + return PLT_PTR_CAST(&se_sess->roc_se_ctx.se_ctx); + } + + if (rte_sess->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) { + if (roc_model_is_cn10k()) { + struct cn10k_sec_session *sec_sess = PLT_PTR_CAST(rte_sess->sec_sess); + return PLT_PTR_CAST(&sec_sess->sa); + } + + if (roc_model_is_cn9k()) { + struct cn9k_sec_session *sec_sess = PLT_PTR_CAST(rte_sess->sec_sess); + return PLT_PTR_CAST(&sec_sess->sa); + } + + plt_err("Invalid cnxk model"); + return NULL; + } + + plt_err("Invalid session type"); + return NULL; +} diff --git a/drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h b/drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h index 28d86b5a18..dc5a6d57b0 100644 --- a/drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h +++ b/drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h @@ -23,6 +23,35 @@ */ struct rte_pmd_cnxk_crypto_qptr; +/** + * @brief Crypto CNXK PMD CPTR opaque pointer. + * + * This structure represents the context pointer that would be used to store the hardware context. + */ +struct rte_pmd_cnxk_crypto_cptr; + +/** + * @brief Crypto CNXK PMD session structure. + * + * This structure represents the session structure that would be used to store the session + * information. + */ +struct rte_pmd_cnxk_crypto_sess { + /** Crypto type (symmetric or asymmetric). */ + enum rte_crypto_op_type op_type; + /** Session type (Crypto or security). */ + enum rte_crypto_op_sess_type sess_type; + /** Session pointer. */ + union { + /** Security session pointer. */ + struct rte_security_session *sec_sess; + /** Crypto symmetric session pointer. */ + struct rte_cryptodev_sym_session *crypto_sym_sess; + /** Crypto asymmetric session pointer */ + struct rte_cryptodev_asym_session *crypto_asym_sess; + }; +}; + /** * Get queue pointer of a specific queue in a cryptodev. * @@ -57,4 +86,17 @@ __rte_experimental void rte_pmd_cnxk_crypto_submit(struct rte_pmd_cnxk_crypto_qptr *qptr, void *inst, uint16_t nb_inst); +/** + * Get the HW CPTR pointer from the rte_crypto/rte_security session. + * + * @param rte_sess + * Pointer to the structure holding rte_cryptodev or rte_security session. + * @return + * - On success, pointer to the HW CPTR. + * - NULL on error. + */ +__rte_experimental +struct rte_pmd_cnxk_crypto_cptr *rte_pmd_cnxk_crypto_cptr_get( + struct rte_pmd_cnxk_crypto_sess *rte_sess); + #endif /* _PMD_CNXK_CRYPTO_H_ */ diff --git a/drivers/crypto/cnxk/version.map b/drivers/crypto/cnxk/version.map index 7a77607774..b510ec4847 100644 --- a/drivers/crypto/cnxk/version.map +++ b/drivers/crypto/cnxk/version.map @@ -4,6 +4,9 @@ EXPERIMENTAL { # added in 24.03 rte_pmd_cnxk_crypto_submit; rte_pmd_cnxk_crypto_qptr_get; + + # added in 24.07 + rte_pmd_cnxk_crypto_cptr_get; }; INTERNAL { -- 2.25.1