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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Sep 2024 10:22:19.3258 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f9d8ed2-1bce-4f3b-50b5-08dcce5dc9ed X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6971 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch set is to improve error handling in pmd and under layer. Gavin Li (3): net/mlx5: set rte errno if malloc failed net/mlx5/hws: add log for failing to create rule in HWS net/mlx5/hws: print CQE error syndrome and more information drivers/net/mlx5/hws/mlx5dr_rule.c | 6 ++++++ drivers/net/mlx5/hws/mlx5dr_send.c | 9 ++++++++- drivers/net/mlx5/mlx5_flow_hw.c | 31 +++++++++++++++++++++++------- 3 files changed, 38 insertions(+), 8 deletions(-) -- 2.34.1